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-- $Id: pdp11_sequencer.vhd 708 2015-08-03 06:41:43Z mueller $

--

-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

--

-- This program is free software; you may redistribute and/or modify it under

-- the terms of the GNU General Public License as published by the Free

-- Software Foundation, either version 2, or at your option any later version.

--

-- This program is distributed in the hope that it will be useful, but

-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY

-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

-- for complete details.

--

------------------------------------------------------------------------------

-- Module Name:    pdp11_sequencer - syn

-- Description:    pdp11: CPU sequencer

--

-- Dependencies:   ib_sel

-- Test bench:     tb/tb_pdp11_core (implicit)

-- Target Devices: generic

-- Tool versions:  ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31

--

-- Revision History: 

-- Date         Rev Version  Comment

-- 2015-08-02   708   1.6.5  BUGFIX: proper trap_mmu and trap_ysv handling

-- 2015-08-01   707   1.6.4  set dm_idone in s_(trap_10|op_trap); add dm_vfetch

-- 2015-07-19   702   1.6.3  add DM_STAT_SE, drop SNUM port

-- 2015-07-10   700   1.6.2  use c_cpurust_hbpt

-- 2015-06-26   695   1.6.1  add SNUM (state number) port

-- 2015-05-10   678   1.6    start/stop/suspend overhaul; reset overhaul

-- 2015-02-07   643   1.5.2  s_op_wait: load R0 in DSRC for DR emulation

-- 2014-07-12   569   1.5.1  rename s_opg_div_zero -> s_opg_div_quit;

--                           use DP_STAT.div_quit; set munit_s_div_sr;

--                           BUGFIX: s_opg_div_sr: check for late div_quit

-- 2014-04-20   554   1.5    now vivado compatible (add dummy assigns in procs)

-- 2011-11-18   427   1.4.2  now numeric_std clean

-- 2010-10-23   335   1.4.1  use ib_sel

-- 2010-10-17   333   1.4    use ibus V2 interface

-- 2010-09-18   300   1.3.2  rename (adlm)box->(oalm)unit

-- 2010-06-20   307   1.3.1  rename cpacc to cacc in vm_cntl_type

-- 2010-06-13   305   1.3    remove CPDIN_WE, CPDOUT_WE out ports; set

--                           CNTL.cpdout_we instead of CPDOUT_WE

-- 2010-06-12   304   1.2.8  signal cpuwait when spinning in s_op_wait

-- 2009-05-30   220   1.2.7  final removal of snoopers (were already commented)

-- 2009-05-09   213   1.2.6  BUGFIX: use is_dstkstack1246, stklim for mode=6

-- 2009-05-02   211   1.2.5  BUGFIX: 11/70 spl semantics again in kernel mode

-- 2009-04-26   209   1.2.4  BUGFIX: give interrupts priority over trap handling

-- 2008-12-14   177   1.2.3  BUGFIX: use is_dstkstack124, fix stklim check bug

-- 2008-12-13   176   1.2.2  BUGFIX: use is_pci in s_dstw_inc if DSTDEF='1'

-- 2008-11-30   174   1.2.1  BUGFIX: add updt_dstadsrc; prevent stale DSRC

-- 2008-08-22   161   1.2    rename ubf_ -> ibf_; use iblib

-- 2008-05-03   143   1.1.9  rename _cpursta->_cpurust; cp reset sets now

--                           c_cpurust_reset; proper c_cpurust_vfail handling

-- 2008-04-27   140   1.1.8  BUGFIX: halt cpu in case of a vector fetch error

--                           use cpursta to encode why cpu halts, remove cpufail

-- 2008-04-27   139   1.1.7  BUGFIX: correct bytop handling for address fetches;

--                           BUGFIX: redo mtp flow; add fork_dsta fork and ddst

--                                   reload in s_opa_mtp_pop_w;

-- 2008-04-19   137   1.1.6  BUGFIX: fix loop state in s_rti_getpc_w

-- 2008-03-30   131   1.1.5  BUGFIX: inc/dec by 2 for byte mode -(sp),(sp)+

--                             inc/dec by 2 for @(R)+ and @-(R) also for bytop's

-- 2008-03-02   121   1.1.4  remove snoopers; add waitsusp, redo WAIT handling

-- 2008-02-24   119   1.1.3  add lah,rps,wps command; revamp cp memory access

--                           change WAIT logic, now also bails out on cp command

-- 2008-01-20   112   1.1.2  rename PRESET->BRESET

-- 2008-01-05   110   1.1.1  rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)

-- 2007-12-30   107   1.1    use IB_MREQ/IB_SRES interface now

-- 2007-06-14    56   1.0.1  Use slvtypes.all

-- 2007-05-12    26   1.0    Initial version 

------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.slvtypes.all;

use work.iblib.all;

use work.pdp11.all;

-- ----------------------------------------------------------------------------

entity pdp11_sequencer is               -- CPU sequencer

  port (

    CLK : in slbit;                     -- clock

    GRESET : in slbit;                  -- general reset

    PSW : in psw_type;                  -- processor status

    PC : in slv16;                      -- program counter

    IREG : in slv16;                    -- IREG

    ID_STAT : in decode_stat_type;      -- instr. decoder status

    DP_STAT : in dpath_stat_type;       -- data path status

    CP_CNTL : in cp_cntl_type;          -- console port control

    VM_STAT : in vm_stat_type;          -- virtual memory status port

    INT_PRI : in slv3;                  -- interrupt priority

    INT_VECT : in slv9_2;               -- interrupt vector

    INT_ACK : out slbit;                -- interrupt acknowledge

    CRESET : out slbit;                 -- cpu reset

    BRESET : out slbit;                 -- bus reset

    MMU_MONI : out mmu_moni_type;       -- mmu monitor port

    DP_CNTL : out dpath_cntl_type;      -- data path control

    VM_CNTL : out vm_cntl_type;         -- virtual memory control port

    CP_STAT : out cp_stat_type;         -- console port status

    ESUSP_O : out slbit;                -- external suspend output

    ESUSP_I : in slbit;                 -- external suspend input

    ITIMER : out slbit;                 -- instruction timer

    HBPT : in slbit;                    -- hardware bpt

    IB_MREQ : in ib_mreq_type;          -- ibus request

    IB_SRES : out ib_sres_type;         -- ibus response    

    DM_STAT_SE : out dm_stat_se_type    -- debug and monitor status - sequencer

  );

end pdp11_sequencer;

architecture syn of pdp11_sequencer is

  constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));

  constant cpuerr_ibf_illhlt : integer := 7;

  constant cpuerr_ibf_adderr : integer := 6;

  constant cpuerr_ibf_nxm : integer := 5;

  constant cpuerr_ibf_iobto : integer := 4;

  constant cpuerr_ibf_ysv : integer := 3;

  constant cpuerr_ibf_rsv : integer := 2;

  type state_type is (

    s_idle,

    s_cp_regread,

    s_cp_rps,

    s_cp_memr_w,

    s_cp_memw_w,

    s_ifetch,

    s_ifetch_w,

    s_idecode,

    s_srcr_def,

    s_srcr_def_w,

    s_srcr_inc,

    s_srcr_inc_w,

    s_srcr_dec,

    s_srcr_dec1,

    s_srcr_ind,

    s_srcr_ind1_w,

    s_srcr_ind2,

    s_srcr_ind2_w,

    s_dstr_def,

    s_dstr_def_w,

    s_dstr_inc,

    s_dstr_inc_w,

    s_dstr_dec,

    s_dstr_dec1,

    s_dstr_ind,

    s_dstr_ind1_w,

    s_dstr_ind2,

    s_dstr_ind2_w,

    s_dstw_def,

    s_dstw_def_w,

    s_dstw_inc,

    s_dstw_inc_w,

    s_dstw_incdef_w,

    s_dstw_dec,

    s_dstw_dec1,

    s_dstw_ind,

    s_dstw_ind_w,

    s_dstw_def246,

    s_dsta_inc,

    s_dsta_incdef_w,

    s_dsta_dec,

    s_dsta_dec1,

    s_dsta_ind,

    s_dsta_ind_w,

    s_op_halt,

    s_op_wait,

    s_op_trap,

    s_op_reset,

    s_op_rts,

    s_op_rts_pop,

    s_op_rts_pop_w,

    s_op_spl,

    s_op_mcc,

    s_op_br,

    s_op_mark,

    s_op_mark1,

    s_op_mark_pop,

    s_op_mark_pop_w,

    s_op_sob,

    s_op_sob1,

    s_opg_gen,

    s_opg_gen_rmw_w,

    s_opg_mul,

    s_opg_mul1,

    s_opg_div,

    s_opg_div_cn,

    s_opg_div_cr,

    s_opg_div_sq,

    s_opg_div_sr,

    s_opg_div_quit,

    s_opg_ash,

    s_opg_ash_cn,

    s_opg_ashc,

    s_opg_ashc_cn,

    s_opg_ashc_wl,

    s_opa_jsr,

    s_opa_jsr1,

    s_opa_jsr_push,

    s_opa_jsr_push_w,

    s_opa_jsr2,

    s_opa_jmp,

    s_opa_mtp,

    s_opa_mtp_pop_w,

    s_opa_mtp_reg,

    s_opa_mtp_mem,

    s_opa_mtp_mem_w,

    s_opa_mfp_reg,

    s_opa_mfp_mem,

    s_opa_mfp_mem_w,

    s_opa_mfp_dec,

    s_opa_mfp_push,

    s_opa_mfp_push_w,

    s_trap_4,

    s_trap_10,

    s_trap_disp,

    s_int_ext,

    s_int_getpc,

    s_int_getpc_w,

    s_int_getps,

    s_int_getps_w,

    s_int_getsp,

    s_int_decsp,

    s_int_pushps,

    s_int_pushps_w,

    s_int_pushpc,

    s_int_pushpc_w,

    s_rti_getpc,

    s_rti_getpc_w,

    s_rti_getps,

    s_rti_getps_w,

    s_rti_newpc,

    s_vmerr,

    s_cpufail

  );

  signal R_STATE : state_type := s_idle;  -- state register

  signal N_STATE : state_type := s_idle;

  signal R_STATUS : cpustat_type := cpustat_init;

  signal N_STATUS : cpustat_type := cpustat_init;

  signal R_CPUERR : cpuerr_type := cpuerr_init;

  signal N_CPUERR : cpuerr_type := cpuerr_init;

  signal R_IDSTAT : decode_stat_type := decode_stat_init;

  signal N_IDSTAT : decode_stat_type := decode_stat_init;

  signal R_VMSTAT : vm_stat_type := vm_stat_init;

  signal IBSEL_CPUERR : slbit := '0';

begin

  SEL : ib_sel

    generic map (

      IB_ADDR => ibaddr_cpuerr)

    port map (

      CLK     => CLK,

      IB_MREQ => IB_MREQ,

      SEL     => IBSEL_CPUERR

    );

  proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)

    variable idout : slv16 := (others=>'0');

  begin

    idout := (others=>'0');

    if IBSEL_CPUERR = '1' then

      idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;

      idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;

      idout(cpuerr_ibf_nxm)    := R_CPUERR.nxm;

      idout(cpuerr_ibf_iobto)  := R_CPUERR.iobto;

      idout(cpuerr_ibf_ysv)    := R_CPUERR.ysv;

      idout(cpuerr_ibf_rsv)    := R_CPUERR.rsv;

    end if;

    IB_SRES.dout <= idout;

    IB_SRES.ack  <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all

    IB_SRES.busy <= '0';

  end process proc_ibres;

  proc_status: process (CLK)

  begin

    if rising_edge(CLK) then

      if GRESET = '1' then

        R_STATUS <= cpustat_init;

        R_CPUERR <= cpuerr_init;

        R_IDSTAT <= decode_stat_init;

        R_VMSTAT <= vm_stat_init;

      else

        R_STATUS <= N_STATUS;

        R_CPUERR <= N_CPUERR;

        R_IDSTAT <= N_IDSTAT;

        R_VMSTAT <= VM_STAT;

      end if;

    end if;

  end process proc_status;

  proc_state: process (CLK)

  begin

    if rising_edge(CLK) then

      if GRESET = '1' then

        R_STATE <= s_idle;

      else

        R_STATE <= N_STATE;

      end if;

    end if;

  end process proc_state;

  proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL,

                      ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,

                      R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,

                      INT_PRI, INT_VECT, ESUSP_I, HBPT)

    variable nstate : state_type;

    variable nstatus : cpustat_type := cpustat_init;

    variable ncpuerr : cpuerr_type := cpuerr_init;

    variable ndpcntl : dpath_cntl_type := dpath_cntl_init;

    variable nvmcntl : vm_cntl_type := vm_cntl_init;

    variable nidstat : decode_stat_type := decode_stat_init;

    variable nmmumoni : mmu_moni_type := mmu_moni_init;

    variable imemok : boolean;

    variable bytop : slbit := '0';           -- local bytop  access flag

    variable macc  : slbit := '0';           -- local modify access flag

    variable lvector : slv9_2 := (others=>'0'); -- local trap/interrupt vector

    variable brcode : slv4 := (others=>'0'); -- reduced br opcode (15,10-8)

    variable brcond : slbit := '0';          -- br condition value

    variable is_kmode : slbit := '0';        -- cmode is kernel mode

    variable is_dstkstack1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6

    variable int_pending : slbit := '0';     -- an interrupt is pending

    variable idm_idone   : slbit := '0';     -- idone  for dm_stat_se

    variable idm_vfetch  : slbit := '0';     -- vfetch for dm_stat_se

    alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high

    alias SRCDEF : slbit is IREG(9);           -- src register mode defered

    alias SRCREG : slv3 is IREG(8 downto 6);   -- src register number

    alias DSTMODF : slv3 is IREG(5 downto 3);  -- dst register full mode

    alias DSTMOD : slv2 is IREG(5 downto 4);   -- dst register mode high

    alias DSTDEF : slbit is IREG(3);           -- dst register mode defered

    alias DSTREG : slv3 is IREG(2 downto 0);   -- dst register number

    procedure do_memread_i(nstate  : inout state_type;

                           ndpcntl : inout dpath_cntl_type;

                           nvmcntl : inout vm_cntl_type;

                           wstate  : in state_type) is

    begin

      ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc;       -- VA = PC

      nvmcntl.dspace := '0';

      nvmcntl.req := '1';

      ndpcntl.gpr_pcinc := '1';                      -- (pc)++

      nstate := wstate;

    end procedure do_memread_i;

    procedure do_memread_d(nstate  : inout state_type;

                           nvmcntl : inout vm_cntl_type;

                           wstate  : in state_type;

                           bytop   : in slbit := '0';

                           macc    : in slbit := '0';

                           is_pci  : in slbit := '0') is

    begin

      nvmcntl.dspace := not is_pci;        -- ispace if pc immediate modes

--      bytop := R_IDSTAT.is_bytop and not is_addr;

      nvmcntl.bytop := bytop;

      nvmcntl.macc  := macc;

      nvmcntl.req   := '1';

      nstate := wstate;

    end procedure do_memread_d;

    procedure do_memread_srcinc(nstate   : inout state_type;

                                ndpcntl  : inout dpath_cntl_type;

                                nvmcntl  : inout vm_cntl_type;

                                wstate   : in state_type;

                                nmmumoni : inout mmu_moni_type;

                                updt_sp  : in slbit := '0') is

    begin

      ndpcntl.ounit_asel := c_ounit_asel_dsrc;   -- OUNIT A=DSRC

      ndpcntl.ounit_const := "000000010";        -- OUNIT const=2

      ndpcntl.ounit_bsel := c_ounit_bsel_const;  -- OUNIT B=const

      ndpcntl.dres_sel := c_dpath_res_ounit;     -- DRES = OUNIT

      ndpcntl.dsrc_sel := c_dpath_dsrc_res;      -- DSRC = DRES

      ndpcntl.dsrc_we := '1';                    -- update DSRC

      if updt_sp = '1' then

        nmmumoni.regmod := '1';

        nmmumoni.isdec := '0';

        ndpcntl.gpr_adst := c_gpr_sp;            -- update SP too

        ndpcntl.gpr_we := '1';

      end if;

      ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC

      nvmcntl.dspace := '1';

      nvmcntl.req := '1';

      nstate := wstate;

    end procedure do_memread_srcinc;

    procedure do_memwrite(nstate  : inout state_type;

                          nvmcntl : inout vm_cntl_type;

                          wstate  : in state_type;

                          macc    : in slbit :='0') is

    begin

      nvmcntl.dspace := '1';

      nvmcntl.bytop := R_IDSTAT.is_bytop;

      nvmcntl.wacc := '1';

      nvmcntl.macc := macc;

      nvmcntl.req := '1';

      nstate := wstate;

    end procedure do_memwrite;

    procedure do_memcheck(nstate  : inout state_type;

                          nstatus : inout cpustat_type;

                          mok     : out boolean) is

    begin

      nstate  := nstate;                -- dummy to add driver (vivado)

      nstatus := nstatus;               -- "

      mok := false;

      if VM_STAT.ack = '1' then

        mok := true;

        if VM_STAT.trap_mmu = '1' then  -- remember trap_mmu, may happen on any

          nstatus.trap_mmu := '1';      --   memory access of an instruction

        end if;

        if VM_STAT.trap_ysv = '1' then  -- remember trap_ysv (on any access)

          if R_CPUERR.ysv = '0' then      -- ysv trap when cpuerr not yet set

            nstatus.trap_ysv := '1';

          end if;

        end if;

      elsif VM_STAT.err='1' or VM_STAT.fail='1' then

        nstate := s_vmerr;

      end if;

    end procedure do_memcheck;

    procedure do_const_opsize(ndpcntl : inout dpath_cntl_type;

                              bytop   : in slbit;

                              isdef   : in slbit;

                              regnum  : in slv3) is

    begin

      ndpcntl := ndpcntl;               -- dummy to add driver (vivado)

      if bytop='0' or isdef='1' or

         regnum=c_gpr_pc or regnum=c_gpr_sp then

        ndpcntl.ounit_const := "000000010";

      else

        ndpcntl.ounit_const := "000000001";

      end if;

    end procedure do_const_opsize;

    procedure do_fork_dstr(nstate : inout state_type;

                           idstat : in decode_stat_type) is

    begin

      case idstat.fork_dstr is

        when c_fork_dstr_def => nstate := s_dstr_def;

        when c_fork_dstr_inc => nstate := s_dstr_inc;

        when c_fork_dstr_dec => nstate := s_dstr_dec;

        when c_fork_dstr_ind => nstate := s_dstr_ind;

        when others => nstate := s_cpufail;

      end case;

    end procedure do_fork_dstr;

    procedure do_fork_opg(nstate : inout state_type;

                          idstat : in decode_stat_type) is

    begin

      case idstat.fork_opg is

        when c_fork_opg_gen  => nstate := s_opg_gen;

        when c_fork_opg_wdef => nstate := s_dstw_def;

        when c_fork_opg_winc => nstate := s_dstw_inc;

        when c_fork_opg_wdec => nstate := s_dstw_dec;

        when c_fork_opg_wind => nstate := s_dstw_ind;

        when c_fork_opg_mul  => nstate := s_opg_mul;

        when c_fork_opg_div  => nstate := s_opg_div;

        when c_fork_opg_ash  => nstate := s_opg_ash;

        when c_fork_opg_ashc => nstate := s_opg_ashc;

        when others => nstate := s_cpufail;

      end case;

    end procedure do_fork_opg;

    procedure do_fork_opa(nstate : inout state_type;

                          idstat : in decode_stat_type) is

    begin

      case idstat.fork_opa is

        when c_fork_opa_jmp => nstate := s_opa_jmp;

        when c_fork_opa_jsr => nstate := s_opa_jsr;

        when c_fork_opa_mtp => nstate := s_opa_mtp_mem;

        when c_fork_opa_mfp_reg => nstate := s_opa_mfp_reg;

        when c_fork_opa_mfp_mem => nstate := s_opa_mfp_mem;

        when others => nstate := s_cpufail;

      end case;

    end procedure do_fork_opa;

    procedure do_fork_next(nstate   : inout state_type;

                           nstatus  : inout cpustat_type;

                           nmmumoni : inout mmu_moni_type) is

    begin

      nmmumoni.idone := '1';

      if unsigned(INT_PRI) > unsigned(PSW.pri) then

        nstate := s_idle;

      elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or

            R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or

            PSW.tflag='1' then

        nstate := s_trap_disp;

      elsif R_STATUS.cpugo='1' and        -- running

            R_STATUS.cpususp='0' and      --   and not suspended

            not R_STATUS.cmdbusy='1' then --   and no cmd pending

        nstate := s_ifetch;                               -- fetch next

      else

        nstate := s_idle;                                 -- otherwise idle

      end if;

    end procedure do_fork_next;

    procedure do_fork_next_pref(nstate   : inout state_type;

                                nstatus  : inout cpustat_type;

                                ndpcntl  : inout dpath_cntl_type;

                                nvmcntl  : inout vm_cntl_type;

                                nmmumoni : inout mmu_moni_type) is

    begin

      ndpcntl := ndpcntl;               -- dummy to add driver (vivado)

      nvmcntl := nvmcntl;               -- "

      nmmumoni.idone := '1';

      if unsigned(INT_PRI) > unsigned(PSW.pri) then

        nstate := s_idle;

      elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or

            R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or

            PSW.tflag='1' then

        nstate := s_trap_disp;

      elsif R_STATUS.cpugo='1' and       -- running

            R_STATUS.cpususp='0' and      --   and not suspended

            not R_STATUS.cmdbusy='1' then --   and no cmd pending

        nvmcntl.req := '1';                 -- read next instruction

        ndpcntl.gpr_pcinc := '1';           -- inc PC

        nmmumoni.istart := '1';             -- signal istart to MMU

        nstate := s_ifetch_w;               -- next: wait for fetched instruction

      else

        nstate := s_idle;                   -- otherwise idle

      end if;

    end procedure do_fork_next_pref;

    procedure do_start_int(nstate  : inout state_type;

                           ndpcntl : inout dpath_cntl_type;

                           vector  : in slv9_2) is

    begin

      ndpcntl.dtmp_sel := c_dpath_dtmp_psw;    -- DTMP = PSW 

      ndpcntl.dtmp_we := '1';

      ndpcntl.ounit_azero := '1';              -- OUNIT A = 0

      ndpcntl.ounit_const := vector & "00";    -- vector

      ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)

      ndpcntl.dres_sel := c_dpath_res_ounit;   -- DRES = OUNIT

      ndpcntl.dsrc_sel := c_dpath_dsrc_res;    -- DSRC = DRES

      ndpcntl.dsrc_we := '1';                  -- DSRC = vector

      nstate := s_int_getpc;

    end procedure do_start_int;

  begin

    nstate  := R_STATE;

    nstatus := R_STATUS;

    ncpuerr := R_CPUERR;

    nstatus.cpuwait := '0';             -- wait flag 0 unless set in s_op_wait

    -- itimer pulse logic:

    --   if neither running nor suspended --> free run, set itimer = 1

    --   otherwise clear to ensure single cycle pulses generated by

    --   s_idecode or s_op_wait

    if R_STATUS.cpugo='0' and R_STATUS.cpususp='0' then

      nstatus.itimer := '1';

    else

      nstatus.itimer := '0';

    end if;

    nstatus.creset := '0';              -- ensure single cycle pulse

    nstatus.breset := '0';              -- dito

    nstatus.intack := '0';              -- dito

    nidstat := R_IDSTAT;

    if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !

      ncpuerr := cpuerr_init;

    end if;

    int_pending := '0';

    if unsigned(INT_PRI) > unsigned(PSW.pri) then

      int_pending := '1';

    end if;

    idm_idone  := '0';

    idm_vfetch := '0';

    imemok := false;

    nmmumoni := mmu_moni_init;

    nmmumoni.pc := PC;

    macc  := '0';

    bytop := '0';

    brcode := IREG(15) & IREG(10 downto 8);

    brcond := '1';

    is_kmode := '0';

    is_dstkstack1246 := '0';

    if PSW.cmode = c_psw_kmode then

      is_kmode := '1';

      if DSTREG = c_gpr_sp and

         (DSTMODF="001" or DSTMODF="010" or

          DSTMODF="100" or DSTMODF="110") then

        is_dstkstack1246 := '1';

      end if;

    end if;

    lvector := (others=>'0');

    nvmcntl := vm_cntl_init;

    nvmcntl.dspace := '1';                -- DEFAULT

    nvmcntl.mode := PSW.cmode;            -- DEFAULT

    nvmcntl.intrsv := R_STATUS.do_intrsv; -- DEFAULT

    ndpcntl := dpath_cntl_init;

    ndpcntl.gpr_asrc := SRCREG;           -- DEFAULT

    ndpcntl.gpr_adst := DSTREG;           -- DEFAULT

    ndpcntl.gpr_mode := PSW.cmode;        -- DEFAULT

    ndpcntl.gpr_rset := PSW.rset;         -- DEFAULT

    ndpcntl.gpr_we := '0';                -- DEFAULT

    ndpcntl.gpr_bytop := '0';             -- DEFAULT

    ndpcntl.gpr_pcinc := '0';             -- DEFAULT

    ndpcntl.psr_ccwe := '0';              -- DEFAULT

    ndpcntl.psr_we := '0';                -- DEFAULT

    ndpcntl.psr_func := "000";            -- DEFAULT

    ndpcntl.dsrc_sel := c_dpath_dsrc_src;

    ndpcntl.dsrc_we := '0';

    ndpcntl.ddst_sel := c_dpath_ddst_dst;

    ndpcntl.ddst_we := '0';

    ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;

    ndpcntl.dtmp_we := '0';

    ndpcntl.ounit_asel  := c_ounit_asel_ddst;

    ndpcntl.ounit_azero := '0';            -- DEFAULT

    ndpcntl.ounit_const := (others=>'0');  -- DEFAULT

    ndpcntl.ounit_bsel  := c_ounit_bsel_const;

    ndpcntl.ounit_opsub := '0';            -- DEFAULT

    ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC

    ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC

    ndpcntl.aunit_cimod  := R_IDSTAT.aunit_cimod;  -- STATIC

    ndpcntl.aunit_cc1op  := R_IDSTAT.aunit_cc1op;  -- STATIC

    ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC

    ndpcntl.aunit_bytop  := R_IDSTAT.is_bytop;     -- STATIC

    ndpcntl.lunit_func   := R_IDSTAT.lunit_func;   -- STATIC

    ndpcntl.lunit_bytop  := R_IDSTAT.is_bytop;     -- STATIC

    ndpcntl.munit_func := R_IDSTAT.munit_func;     -- STATIC

    ndpcntl.ireg_we := '0';

    ndpcntl.cres_sel := R_IDSTAT.res_sel;        -- DEFAULT

    ndpcntl.dres_sel := c_dpath_res_ounit;

    ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;

    if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then

      nstatus.cmdbusy := '1';

      nstatus.cpfunc  := CP_CNTL.func;

      nstatus.cprnum  := CP_CNTL.rnum;

    end if;

    if R_STATUS.cmdack = '1' then

      nstatus.cmdack  := '0';

      nstatus.cmderr  := '0';

      nstatus.cmdmerr := '0';

    end if;

    case R_STATE is