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# $Id: tb_pdp11core_stim.dat 716 2015-12-22 21:44:33Z mueller $
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2 |
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#
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# Revision History:
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# Date Rev Version Comment
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34 |
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# 2015-12-22 716 2.7 comment out test 20.13 (fails since r708)
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30 |
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# 2015-05-08 675 2.6 start/stop/suspend overhaul
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28 |
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# 2014-12-26 621 2.5 adopt wmembe,ribr,wibr emulation to new 4k window
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| 8 |
27 |
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# 2014-12-20 614 2.4 adopted to rlink v4
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25 |
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# 2014-07-13 569 2.3 after ECO-026: correct test 31.1 wrong V=1 cases
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# correct test 37.2: 2 V=1 cases have regs now updated
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2 |
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# 2010-06-20 308 2.2.1 add wibrb, ribr, wibr based tests
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| 12 |
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# 2010-06-13 305 2.2 adopt to new rri address and function semantics
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| 13 |
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# 2009-11-22 252 2.1.14 change SSR0 expects, adapt to ECO-021.
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| 14 |
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# 2009-05-02 211 2.1.13 add nop after spl in pirq test, 11/70 spl now !!
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# 2008-08-29 163 2.1.12 add wtlam to harvest attn after sto in test 13
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# 2008-04-27 139 2.1.11 adapt expected ssr1 after mtpi/d after ECO-009 fix
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| 17 |
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# 2008-03-15 125 2.1.10 exclude some tests from simh ([[off/on]]
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# 2008-03-09 124 2.1.9 fixed addr-mode in code 34, shifted 47+50
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# 2008-03-02 121 2.1.8 add meory access error tests
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# add Code 13, testing WAIT and bwm/brm while CPU runs
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| 21 |
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# 2008-02-24 119 2.1.7 add tests for lah,rps,wps; use rps,wps
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| 22 |
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# use 22bit mode for nxm test (now needed!)
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| 23 |
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# 2008-02-23 118 2.1.6 for nxm tests use mmu and page below i/o-page
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| 24 |
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# in code 35 use access to 160000 to test trap
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| 25 |
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# 2007-09-23 84 2.1.5 use .reset to make it re-executable
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# 2007-09-16 83 2.1.4 clear CPUERR in beginning of test 20 {runs in FPGA}
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# 2007-09-02 79 2.1.3 add .mode command (for pi_rri use)
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# 2007-08-25 75 2.1.2 add .cpmon/.rpmon (for use with rri)
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| 29 |
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# 2007-08-16 74 2.1.1 adapt to changed LAM handling
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| 30 |
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# 2007-08-12 73 2.1 use wtgo (revised conv_stim)
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| 31 |
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# 2007-08-03 71 2.0 convert to command mode with conv_stim
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| 32 |
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# 2007-07-08 65 1.2 removed 1st 'delay' parameter; use .to_(cmd|stp|go)
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| 33 |
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# 2007-06-10 51 1.1 consolidate w11a test bench
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# 2007-05-13 29 1.0 initial version (imported)
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#
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| 36 |
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.mode pdpcp
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| 37 |
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.tocmd 50
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| 38 |
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.tostp 100
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| 39 |
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.togo 5000
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| 40 |
9 |
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.rlmon 0
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2 |
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.rbmon 0
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.scntl 13 0
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#
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| 44 |
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.reset
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| 45 |
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.wait 10
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.anena 1
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| 47 |
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#
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| 48 |
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C "Code 0" Some elementary initial tests
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| 49 |
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C write registers
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| 50 |
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#
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| 51 |
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wr0 000001 -- set r0,..,r7
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| 52 |
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wr1 000101 --
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| 53 |
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wr2 000201 --
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| 54 |
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wr3 000301 --
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| 55 |
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wr4 000401 --
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| 56 |
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wr5 000501 --
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| 57 |
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wsp 000601 --
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| 58 |
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wpc 000701 --
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| 59 |
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#
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| 60 |
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C read registers
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| 61 |
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#
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rr0 d=000001 -- ! r0
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| 63 |
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rr1 d=000101 -- ! r1
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| 64 |
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rr2 d=000201 -- ! r2
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| 65 |
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rr3 d=000301 -- ! r3
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| 66 |
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rr4 d=000401 -- ! r4
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| 67 |
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rr5 d=000501 -- ! r5
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| 68 |
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rsp d=000601 -- ! sp
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rpc d=000701 -- ! pc
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#
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C write memory
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#
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wal 002000 -- write mem(2000,...,2006)
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bwm 4
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| 75 |
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007700 --
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007710 --
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| 77 |
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007720 --
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007730 --
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| 79 |
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#
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C read memory
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| 81 |
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#
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wal 002000
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brm 4
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d=007700 -- ! mem(2000)
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| 85 |
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d=007710 -- ! mem(2002)
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| 86 |
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d=007720 -- ! mem(2004)
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| 87 |
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d=007730 -- ! mem(2006)
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| 88 |
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#
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C write/read PSW via various mechanisms
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C via wps/rps
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| 91 |
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#
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| 92 |
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wps 000017
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rps d=000017
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wps 000000
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rps d=000000
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#
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C via 16bit cp addressing (wal 177776)
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#
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wal 177776
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wm 000017 -- set all cc flags in psw
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rm d=000017 -- ! psw
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rps d=000017
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| 103 |
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wm 000000 -- clear psw
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| 104 |
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rm d=000000 -- ! psw
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rps d=000000
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#
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C via 22bit cp addressing (wal 177776; wah 177)
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#
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| 109 |
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wal 177776
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wah 000177
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wm 000017 -- set all cc flags in psw
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| 112 |
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rm d=000017 -- ! psw
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| 113 |
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rps d=000017
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| 114 |
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wm 000000 -- clear psw
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| 115 |
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rm d=000000 -- ! psw
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| 116 |
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rps d=000000
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| 117 |
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#
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C via ibr (ibrb 177700)
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#
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| 120 |
28 |
wfjm |
wibr 177776 000017 -- set all cc flags in psw
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ribr 177776 d=000017 -- ! psw
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| 122 |
2 |
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rps d=000017
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| 123 |
28 |
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wibr 177776 000000 -- set all cc flags in psw
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| 124 |
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ribr 177776 d=000000 -- ! psw
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| 125 |
2 |
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rps d=000000
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| 126 |
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#
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| 127 |
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C write register set 1, sm,um stack
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| 128 |
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#
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| 129 |
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wps 004000 -- psw: cm=kernel, set=1
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| 130 |
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wr0 010001 -- set r0,..,r5 [[r10]]
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| 131 |
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wr1 010101 -- [[r11]]
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| 132 |
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wr2 010201 -- [[r12]]
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| 133 |
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wr3 010301 -- [[r13]]
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| 134 |
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wr4 010401 -- [[r14]]
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| 135 |
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wr5 010501 -- [[r15]]
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| 136 |
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wps 044000 -- psw: cm=super(01),set=1
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| 137 |
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wsp 010601 -- set ssp [[ssp]]
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| 138 |
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wps 144000 -- psw: cm=user(11),set=1
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| 139 |
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wsp 110601 -- set usp [[usp]]
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#
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C read all registers set 0/1, km,sm,um stack
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#
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wps 000000 -- psw: cm=kernel(00),set=0
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| 144 |
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rr0 d=000001 -- ! r0
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rr1 d=000101 -- ! r1
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| 146 |
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rr2 d=000201 -- ! r2
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rr3 d=000301 -- ! r3
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| 148 |
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rr4 d=000401 -- ! r4
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| 149 |
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rr5 d=000501 -- ! r5
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| 150 |
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rsp d=000601 -- ! ksp
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| 151 |
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rpc d=000701 -- ! pc
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wps 040000 -- psw: cm=super(01),set=0
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| 153 |
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rsp d=010601 -- ! ssp [[ssp]]
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| 154 |
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wps 140000 -- psw: cm=user(11),set=0
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| 155 |
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rsp d=110601 -- ! usp [[usp]]
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| 156 |
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wps 144000 -- psw: cm=user(11),set=1
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| 157 |
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rr0 d=010001 -- ! r0 [[r10]]
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| 158 |
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rr1 d=010101 -- ! r1 [[r11]]
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| 159 |
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rr2 d=010201 -- ! r2 [[r12]]
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| 160 |
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rr3 d=010301 -- ! r3 [[r13]]
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| 161 |
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rr4 d=010401 -- ! r4 [[r14]]
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| 162 |
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rr5 d=010501 -- ! r5 [[r15]]
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| 163 |
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#
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C write IB space: MMU SAR supervisor mode (16 bit regs)
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| 165 |
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#
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wal 172240 -- set first three SM I space address regs
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bwm 3
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012340
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012342
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012344
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#
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C read IB space: MMU SAR supervisor mode (16 bit regs)
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| 173 |
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#
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wal 172240 -- ! verify first three SM I space address regs
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brm 3
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d=012340
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| 177 |
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d=012342
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| 178 |
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d=012344
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| 179 |
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#
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| 180 |
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C read IB space via ibr: MMU SAR supervisor mode (16 bit regs)
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| 181 |
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#
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| 182 |
28 |
wfjm |
ribr 172240 d=012340
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ribr 172242 d=012342
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ribr 172244 d=012344
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2 |
wfjm |
#
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| 186 |
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C byte write IB space via ibr: MMU SAR supervisor mode (16 bit regs)
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| 187 |
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#
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| 188 |
28 |
wfjm |
wmembe 101 -- write low byte (set sticky flag)
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| 189 |
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wibr 172240 177000
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| 190 |
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wibr 172242 177002
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| 191 |
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wibr 172244 177004
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| 192 |
2 |
wfjm |
wal 172240 -- ! verify
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| 193 |
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brm 3
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| 194 |
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d=012000
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d=012002
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| 196 |
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d=012004
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| 197 |
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#
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| 198 |
28 |
wfjm |
wmembe 110 -- write high byte (set sticky flag)
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| 199 |
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wibr 172240 000377
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| 200 |
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wibr 172242 022377
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| 201 |
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wibr 172244 044377
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| 202 |
2 |
wfjm |
wal 172240 -- ! verify
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| 203 |
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brm 3
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| 204 |
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d=000000
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| 205 |
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d=022002
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| 206 |
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d=044004
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| 207 |
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#
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| 208 |
28 |
wfjm |
wmembe 011 -- write high and low byte
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| 209 |
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wibr 172240 012340
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| 210 |
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wibr 172242 012342
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| 211 |
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wibr 172244 012344
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| 212 |
2 |
wfjm |
wal 172240 -- ! verify
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| 213 |
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brm 3
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| 214 |
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d=012340
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| 215 |
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d=012342
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| 216 |
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d=012344
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| 217 |
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#
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| 218 |
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#[[off]] - this tests cp not the cpu - meaningless in simh
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| 219 |
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#
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| 220 |
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C test access error handling to memory (use 17740000)
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| 221 |
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C with wm/rm
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| 222 |
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#
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| 223 |
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wal 140000
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| 224 |
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wah 000177
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| 225 |
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.merr 1
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| 226 |
27 |
wfjm |
.sdef s=01000001
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| 227 |
2 |
wfjm |
wm 000000
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| 228 |
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rm d=-
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| 229 |
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.merr 0
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| 230 |
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.sdef s=00000000,01110000
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| 231 |
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#
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| 232 |
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C with bwm/brm
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| 233 |
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#
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| 234 |
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wal 140000
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| 235 |
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wah 000177
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| 236 |
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.merr 1
|
| 237 |
27 |
wfjm |
.sdef s=01000001
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| 238 |
2 |
wfjm |
bwm 2
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| 239 |
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000000
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| 240 |
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000000
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| 241 |
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.merr 0
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| 242 |
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.sdef s=00000000,01110000
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| 243 |
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#
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| 244 |
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wal 140000
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| 245 |
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wah 000177
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| 246 |
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.merr 1
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| 247 |
27 |
wfjm |
.sdef s=01000001
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| 248 |
2 |
wfjm |
brm 2
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| 249 |
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d=-
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| 250 |
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d=-
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| 251 |
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.merr 0
|
| 252 |
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.sdef s=00000000,01110000
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| 253 |
|
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#
|
| 254 |
30 |
wfjm |
C test access error handling to IB space (use 00160016)
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| 255 |
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C (is above ibd_ibmon decoded range, and below other debug stuff)
|
| 256 |
2 |
wfjm |
C with wm/rm
|
| 257 |
30 |
wfjm |
wal 160016
|
| 258 |
2 |
wfjm |
.merr 1
|
| 259 |
27 |
wfjm |
.sdef s=01000001
|
| 260 |
2 |
wfjm |
wm 000000
|
| 261 |
|
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rm d=-
|
| 262 |
|
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.merr 0
|
| 263 |
|
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.sdef s=00000000,01110000
|
| 264 |
|
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C with bwm/brm
|
| 265 |
|
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#
|
| 266 |
30 |
wfjm |
wal 160016
|
| 267 |
2 |
wfjm |
.merr 1
|
| 268 |
27 |
wfjm |
.sdef s=01000001
|
| 269 |
2 |
wfjm |
bwm 2
|
| 270 |
|
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000000
|
| 271 |
|
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000000
|
| 272 |
|
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.merr 0
|
| 273 |
|
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.sdef s=00000000,01110000
|
| 274 |
|
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#
|
| 275 |
30 |
wfjm |
wal 160016
|
| 276 |
2 |
wfjm |
.merr 1
|
| 277 |
27 |
wfjm |
.sdef s=01000001
|
| 278 |
2 |
wfjm |
brm 2
|
| 279 |
|
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d=-
|
| 280 |
|
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d=-
|
| 281 |
|
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.merr 0
|
| 282 |
|
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.sdef s=00000000,01110000
|
| 283 |
|
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#[[on]]
|
| 284 |
|
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#-----------------------------------------------------------------------------
|
| 285 |
|
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C Setup trap catchers
|
| 286 |
|
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#
|
| 287 |
|
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wal 000004 -- vectors: 4...34 (trap catcher)
|
| 288 |
|
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bwm 14
|
| 289 |
|
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000006 -- PC:06 ; vector 4
|
| 290 |
|
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000000 -- PS:0
|
| 291 |
|
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000012 -- PC:12 ; vector 10
|
| 292 |
|
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000000 -- PS:0
|
| 293 |
|
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000016 -- PC:16 ; vector 14 (T bit; BPT)
|
| 294 |
|
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000000 -- PS:0
|
| 295 |
|
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000022 -- PC:22 ; vector 20 (IOT)
|
| 296 |
|
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000000 -- PS:0
|
| 297 |
|
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000026 -- PC:26 ; vector 24 (Power fail, not used)
|
| 298 |
|
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000000 -- PS:0
|
| 299 |
|
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000032 -- PC:32 ; vector 30 (EMT)
|
| 300 |
|
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000000 -- PS:0
|
| 301 |
|
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000036 -- PC:36 ; vector 34 (TRAP)
|
| 302 |
|
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000000 -- PS:0
|
| 303 |
|
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wal 000240 -- vectors: 240,244,250 (trap catcher)
|
| 304 |
|
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bwm 6
|
| 305 |
|
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000242 -- PC:242 ; vector 240 (PIRQ)
|
| 306 |
|
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000000 -- PS:0
|
| 307 |
|
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000246 -- PC:246 ; vector 244 (FPU)
|
| 308 |
|
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000000 -- PS:0
|
| 309 |
|
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000252 -- PC:252 ; vector 250 (MMU)
|
| 310 |
|
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000000 -- PS:0
|
| 311 |
|
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#
|
| 312 |
|
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C Setup MMU
|
| 313 |
|
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#
|
| 314 |
|
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wal 172300 -- kernel I space DR
|
| 315 |
|
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bwm 8
|
| 316 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 317 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 318 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 319 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 320 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 321 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 322 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 323 |
|
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077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 324 |
|
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wal 172340 -- kernel I space AR
|
| 325 |
|
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bwm 8
|
| 326 |
|
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000000 -- 0
|
| 327 |
|
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000200 -- 200 020000 base
|
| 328 |
|
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000400 -- 400 040000 base
|
| 329 |
|
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000600 -- 600 060000 base
|
| 330 |
|
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001000 -- 1000 100000 base
|
| 331 |
|
|
001200 -- 1200 120000 base
|
| 332 |
|
|
001400 -- 1400 140000 base
|
| 333 |
|
|
177600 -- 176000 (map to I/O page)
|
| 334 |
|
|
#-----------------------------------------------------------------------------
|
| 335 |
|
|
C Setup code 1 [base 2100] (very basics: cont,start; 'simple' instructions)
|
| 336 |
|
|
#
|
| 337 |
|
|
wal 002100 -- code test 1: (sec+clc+halt)
|
| 338 |
|
|
bwm 3
|
| 339 |
|
|
000261 -- sec
|
| 340 |
|
|
000250 -- cln
|
| 341 |
|
|
000000 -- halt
|
| 342 |
|
|
#-----
|
| 343 |
|
|
wal 002120 -- code test 2: (4 *inc R2, starting from -2)
|
| 344 |
|
|
bwm 5
|
| 345 |
|
|
005202 -- inc r2
|
| 346 |
|
|
005202 -- inc r2
|
| 347 |
|
|
005202 -- inc r2
|
| 348 |
|
|
005202 -- inc r2
|
| 349 |
|
|
#2130
|
| 350 |
|
|
000000 -- halt
|
| 351 |
|
|
#-----
|
| 352 |
|
|
wal 002140 -- code test 3: (dec r3; bne -2; halt)
|
| 353 |
|
|
bwm 3
|
| 354 |
|
|
005303 -- dec r3
|
| 355 |
|
|
001376 -- bne -2
|
| 356 |
|
|
000000 -- halt
|
| 357 |
|
|
#-----
|
| 358 |
|
|
wal 002160 -- code test 4: (inc r1; sob r0,-2; halt)
|
| 359 |
|
|
bwm 3
|
| 360 |
|
|
005201 -- inc r1
|
| 361 |
|
|
077002 -- sob r0,-2
|
| 362 |
|
|
000000 -- halt
|
| 363 |
|
|
#
|
| 364 |
30 |
wfjm |
C Exec code 1 (very basics: start; 'simple' instructions)
|
| 365 |
2 |
wfjm |
C Exec test 1.1 (sec+clc+halt)
|
| 366 |
|
|
#
|
| 367 |
|
|
wpc 002100 -- pc=2100
|
| 368 |
|
|
wps 000010 -- psw: set N flag
|
| 369 |
30 |
wfjm |
sta -- start @ 2100
|
| 370 |
2 |
wfjm |
wtgo
|
| 371 |
|
|
rpc d=002106 -- ! pc
|
| 372 |
|
|
rps d=000001 -- ! N cleared, C set now
|
| 373 |
|
|
#
|
| 374 |
|
|
C Exec test 1.2 (4 *inc R2, starting from -2)
|
| 375 |
|
|
#
|
| 376 |
|
|
wr2 177776 -- r2=-2
|
| 377 |
30 |
wfjm |
cres
|
| 378 |
2 |
wfjm |
stapc 002120 -- start @ 2120
|
| 379 |
|
|
wtgo
|
| 380 |
|
|
rr2 d=000002 -- ! r2=2
|
| 381 |
|
|
rpc d=002132 -- ! pc
|
| 382 |
|
|
#
|
| 383 |
|
|
C Exec test 1.3 (dec r3; bne -2; halt)
|
| 384 |
|
|
#
|
| 385 |
|
|
wr3 000002 -- r3=2
|
| 386 |
30 |
wfjm |
cres
|
| 387 |
2 |
wfjm |
stapc 002140 -- start @ 2140
|
| 388 |
|
|
wtgo
|
| 389 |
|
|
rr3 d=000000 -- ! r3=0
|
| 390 |
|
|
rpc d=002146 -- ! pc
|
| 391 |
|
|
#
|
| 392 |
|
|
C Exec test 1.4 (inc r1; sob r0,-2; halt)
|
| 393 |
|
|
#
|
| 394 |
|
|
wr0 000002 -- r0=2
|
| 395 |
|
|
wr1 000000 -- r1=0
|
| 396 |
30 |
wfjm |
cres
|
| 397 |
2 |
wfjm |
stapc 002160 -- start @ 2160
|
| 398 |
|
|
wtgo
|
| 399 |
|
|
rr0 d=000000 -- ! r0=0
|
| 400 |
|
|
rr1 d=000002 -- ! r1=2
|
| 401 |
|
|
rpc d=002166 -- ! pc
|
| 402 |
|
|
#-----------------------------------------------------------------------------
|
| 403 |
|
|
C Setup code 2 [base 2200] (bpt against trap catcher @14)
|
| 404 |
|
|
#
|
| 405 |
|
|
wal 002200 -- code:
|
| 406 |
|
|
bwm 4
|
| 407 |
|
|
000257 -- cl(nzvc)
|
| 408 |
|
|
000261 -- sec
|
| 409 |
|
|
000003 -- bpt
|
| 410 |
|
|
000000 -- halt
|
| 411 |
|
|
#
|
| 412 |
|
|
C Exec code 2 (bpt against trap catcher @14)
|
| 413 |
|
|
#
|
| 414 |
|
|
wsp 001400 -- sp=1400
|
| 415 |
30 |
wfjm |
cres
|
| 416 |
2 |
wfjm |
stapc 002200 -- start @ 2200
|
| 417 |
|
|
wtgo
|
| 418 |
|
|
rsp d=001374 -- ! sp
|
| 419 |
|
|
rpc d=000020 -- ! pc
|
| 420 |
|
|
wal 001374
|
| 421 |
|
|
brm 2
|
| 422 |
|
|
d=002206 -- ! (sp) old pc
|
| 423 |
|
|
d=000341 -- ! 2(sp) old ps
|
| 424 |
|
|
#-----------------------------------------------------------------------------
|
| 425 |
|
|
C Setup code 3 [base 2300] (bpt against trap handler doing inc r0; rtt)
|
| 426 |
|
|
#
|
| 427 |
|
|
wal 002300 -- code:
|
| 428 |
|
|
bwm 4
|
| 429 |
|
|
000257 -- cl(nzvc)
|
| 430 |
|
|
000003 -- bpt
|
| 431 |
|
|
005201 -- inc r1
|
| 432 |
|
|
000000 -- halt
|
| 433 |
|
|
wal 000014 -- vector: 14
|
| 434 |
|
|
bwm 2
|
| 435 |
|
|
002320 -- PC:2320
|
| 436 |
|
|
000002 -- PS:2
|
| 437 |
|
|
wal 002320 -- code (trap 14):
|
| 438 |
|
|
bwm 3
|
| 439 |
|
|
005200 -- inc r0
|
| 440 |
|
|
000006 -- rtt
|
| 441 |
|
|
000000 -- halt
|
| 442 |
|
|
#
|
| 443 |
|
|
C Exec code 3 (bpt against trap handler doing inc r0; rtt)
|
| 444 |
|
|
#
|
| 445 |
|
|
wr0 000000 -- r0=0
|
| 446 |
|
|
wr1 000000 -- r1=0
|
| 447 |
|
|
wsp 001400 -- sp=1400
|
| 448 |
30 |
wfjm |
cres
|
| 449 |
2 |
wfjm |
stapc 002300 -- start @ 2300
|
| 450 |
|
|
wtgo
|
| 451 |
|
|
rr0 d=000001 -- ! r0
|
| 452 |
|
|
rr1 d=000001 -- ! r1
|
| 453 |
|
|
rsp d=001400 -- ! sp
|
| 454 |
|
|
rpc d=002310 -- ! pc
|
| 455 |
|
|
#-----------------------------------------------------------------------------
|
| 456 |
|
|
C Setup code 4 [base 2400] (enable T-trap on handler of code 3; run 2* inc r1)
|
| 457 |
|
|
#
|
| 458 |
|
|
wal 002400
|
| 459 |
|
|
bwm 4
|
| 460 |
|
|
000006 -- rtt
|
| 461 |
|
|
005201 -- inc r1
|
| 462 |
|
|
005201 -- inc r1
|
| 463 |
|
|
000000 -- halt
|
| 464 |
|
|
#
|
| 465 |
|
|
C Exec code 4 (enable T-trap on handler of code 3; run 2* inc r1)
|
| 466 |
|
|
#
|
| 467 |
|
|
wr0 000000 -- r0=0
|
| 468 |
|
|
wr1 000000 -- r1=0
|
| 469 |
|
|
wsp 001374 -- sp=1374
|
| 470 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
| 471 |
|
|
bwm 2
|
| 472 |
|
|
002402 -- start address
|
| 473 |
|
|
000020 -- set T flag in PSW
|
| 474 |
30 |
wfjm |
cres
|
| 475 |
2 |
wfjm |
stapc 002400 -- start @ 2400 -> rtt -> 2402 from stack
|
| 476 |
|
|
wtgo
|
| 477 |
|
|
rr0 d=000002 -- ! r0
|
| 478 |
|
|
rr1 d=000002 -- ! r1
|
| 479 |
|
|
rsp d=001400 -- ! sp
|
| 480 |
|
|
rpc d=002410 -- ! pc
|
| 481 |
|
|
#
|
| 482 |
30 |
wfjm |
cres -- console reset (to clear T flag)
|
| 483 |
2 |
wfjm |
wal 000014 -- vector: 14 -> trap catcher again
|
| 484 |
|
|
bwm 2
|
| 485 |
|
|
000016 -- PC:16
|
| 486 |
|
|
000000 -- PS:0
|
| 487 |
|
|
#-----------------------------------------------------------------------------
|
| 488 |
|
|
C Setup code 5 [base 2500] (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
|
| 489 |
|
|
#
|
| 490 |
|
|
wal 002500 -- code:
|
| 491 |
|
|
bwm 6
|
| 492 |
|
|
011001 -- mov (r0),r1
|
| 493 |
|
|
012002 -- mov (r0)+,r2
|
| 494 |
|
|
012003 -- mov (r0)+,r3
|
| 495 |
|
|
014004 -- mov -(r0),r4
|
| 496 |
|
|
013005 -- mov @(r0)+,r5
|
| 497 |
|
|
000000 -- halt
|
| 498 |
|
|
#
|
| 499 |
|
|
wal 002540 -- data:
|
| 500 |
|
|
bwm 2
|
| 501 |
|
|
000070 --
|
| 502 |
|
|
002550 --
|
| 503 |
|
|
wal 002550 -- data:
|
| 504 |
|
|
bwm 2
|
| 505 |
|
|
000072 --
|
| 506 |
|
|
000074 --
|
| 507 |
|
|
#
|
| 508 |
|
|
C Exec code 5 (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
|
| 509 |
|
|
#
|
| 510 |
|
|
wr0 002540 -- r0=2540
|
| 511 |
|
|
wr1 000000 -- r1=0
|
| 512 |
|
|
wr2 000000 -- r2=0
|
| 513 |
|
|
wr3 000000 -- r3=0
|
| 514 |
|
|
wr4 000000 -- r4=0
|
| 515 |
|
|
wr5 000000 -- r5=0
|
| 516 |
|
|
wsp 001400 -- sp=1400
|
| 517 |
30 |
wfjm |
cres
|
| 518 |
2 |
wfjm |
stapc 002500 -- start @ 2500
|
| 519 |
|
|
wtgo
|
| 520 |
|
|
rr0 d=002544 -- ! r0
|
| 521 |
|
|
rr1 d=000070 -- ! r1
|
| 522 |
|
|
rr2 d=000070 -- ! r2
|
| 523 |
|
|
rr3 d=002550 -- ! r3
|
| 524 |
|
|
rr4 d=002550 -- ! r4
|
| 525 |
|
|
rr5 d=000072 -- ! r5
|
| 526 |
|
|
rsp d=001400 -- ! sp
|
| 527 |
|
|
rpc d=002514 -- ! pc
|
| 528 |
|
|
#-----------------------------------------------------------------------------
|
| 529 |
|
|
C Setup code 6 [base 2600] (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
|
| 530 |
|
|
#
|
| 531 |
|
|
wal 002600 -- code:
|
| 532 |
|
|
bwm 11
|
| 533 |
|
|
016001 -- mov 2(r0),r1
|
| 534 |
|
|
000002
|
| 535 |
|
|
017002 -- mov @2(r0),r2
|
| 536 |
|
|
000002
|
| 537 |
|
|
012703 -- mov (pc)+,r3 ; #377
|
| 538 |
|
|
000377
|
| 539 |
|
|
013704 -- mov @(pc)+,r4 ; @#2552 (in previous code !)
|
| 540 |
|
|
002552
|
| 541 |
|
|
#2620
|
| 542 |
|
|
112705 -- movb (pc)+,r5 ; #377
|
| 543 |
|
|
000377
|
| 544 |
|
|
000000 -- halt
|
| 545 |
|
|
#
|
| 546 |
|
|
C Exec code 6 (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
|
| 547 |
|
|
#
|
| 548 |
|
|
wr0 002540 -- r0=2540 (in previous code !)
|
| 549 |
|
|
wr1 000000 -- r1=0
|
| 550 |
|
|
wr2 000000 -- r2=0
|
| 551 |
|
|
wr3 000000 -- r3=0
|
| 552 |
|
|
wr4 000000 -- r4=0
|
| 553 |
|
|
wr5 000000 -- r5=0
|
| 554 |
|
|
wsp 001400 -- sp=1400
|
| 555 |
30 |
wfjm |
cres
|
| 556 |
2 |
wfjm |
stapc 002600 -- start @ 2600
|
| 557 |
|
|
wtgo
|
| 558 |
|
|
rr0 d=002540 -- ! r0
|
| 559 |
|
|
rr1 d=002550 -- ! r1
|
| 560 |
|
|
rr2 d=000072 -- ! r2
|
| 561 |
|
|
rr3 d=000377 -- ! r3
|
| 562 |
|
|
rr4 d=000074 -- ! r4
|
| 563 |
|
|
rr5 d=177777 -- ! r5
|
| 564 |
|
|
rsp d=001400 -- ! sp
|
| 565 |
|
|
rpc d=002626 -- ! pc
|
| 566 |
|
|
#-----------------------------------------------------------------------------
|
| 567 |
|
|
C Setup code 7 [base 2700] (dstw modes: mov rn,xxx: all non-r modes)
|
| 568 |
|
|
#
|
| 569 |
|
|
wal 002700 -- code:
|
| 570 |
|
|
bwm 18
|
| 571 |
|
|
012710 -- mov #110,(r0) (to 2750)
|
| 572 |
|
|
000110
|
| 573 |
|
|
012721 -- mov #120,(r1)+ (to 2752)
|
| 574 |
|
|
000120
|
| 575 |
|
|
012732 -- mov #130,@(r2)+ (to 2754)
|
| 576 |
|
|
000130
|
| 577 |
|
|
012743 -- mov #140,-(r3) (to 2756)
|
| 578 |
|
|
000140
|
| 579 |
|
|
#2720
|
| 580 |
|
|
012754 -- mov #150,@-(r4) (to 2760)
|
| 581 |
|
|
000150
|
| 582 |
|
|
012760 -- mov #160,12(r0) (to 2762)
|
| 583 |
|
|
000160
|
| 584 |
|
|
000012
|
| 585 |
|
|
012770 -- mov #170,@24(r0) (to 2764)
|
| 586 |
|
|
000170
|
| 587 |
|
|
000024
|
| 588 |
|
|
#2740
|
| 589 |
|
|
010546 -- mov r5,-(r6)
|
| 590 |
|
|
000000 -- halt
|
| 591 |
|
|
#
|
| 592 |
|
|
wal 002770 -- data:
|
| 593 |
|
|
bwm 3
|
| 594 |
|
|
002754 -- mem(2770)=2754
|
| 595 |
|
|
002760 -- mem(2772)=2760
|
| 596 |
|
|
002764 -- mem(2774)=2764
|
| 597 |
|
|
#
|
| 598 |
|
|
C Exec code 7 (dstw modes: mov rn,xxx: all non-r modes)
|
| 599 |
|
|
#
|
| 600 |
|
|
wr0 002750 -- r0=2750
|
| 601 |
|
|
wr1 002752 -- r1=2752
|
| 602 |
|
|
wr2 002770 -- r2=2770
|
| 603 |
|
|
wr3 002760 -- r3=2760
|
| 604 |
|
|
wr4 002774 -- r4=2774
|
| 605 |
|
|
wr5 000666 -- r5=666
|
| 606 |
|
|
wsp 001400 -- sp=1400
|
| 607 |
30 |
wfjm |
cres
|
| 608 |
2 |
wfjm |
stapc 002700 -- start @ 2700
|
| 609 |
|
|
wtgo
|
| 610 |
|
|
rr0 d=002750 -- ! r0
|
| 611 |
|
|
rr1 d=002754 -- ! r1
|
| 612 |
|
|
rr2 d=002772 -- ! r2
|
| 613 |
|
|
rr3 d=002756 -- ! r3
|
| 614 |
|
|
rr4 d=002772 -- ! r4
|
| 615 |
|
|
rr5 d=000666 -- ! r5
|
| 616 |
|
|
rsp d=001376 -- ! sp
|
| 617 |
|
|
rpc d=002744 -- ! pc
|
| 618 |
|
|
wal 002750
|
| 619 |
|
|
brm 7
|
| 620 |
|
|
d=000110 -- ! mem(2750)=110
|
| 621 |
|
|
d=000120 -- ! mem(2752)=120
|
| 622 |
|
|
d=000130 -- ! mem(2754)=130
|
| 623 |
|
|
d=000140 -- ! mem(2756)=140
|
| 624 |
|
|
d=000150 -- ! mem(2760)=150
|
| 625 |
|
|
d=000160 -- ! mem(2762)=160
|
| 626 |
|
|
d=000170 -- ! mem(2764)=170
|
| 627 |
|
|
wal 001376
|
| 628 |
|
|
rmi d=000666 -- ! mem(sp)=666
|
| 629 |
|
|
#-----------------------------------------------------------------------------
|
| 630 |
|
|
C Setup code 10 [base 3000] (dstm modes: inc xxx: all non-r modes)
|
| 631 |
|
|
#
|
| 632 |
|
|
wal 003000 -- code:
|
| 633 |
|
|
bwm 10
|
| 634 |
|
|
005210 -- inc (r0) (to 3050)
|
| 635 |
|
|
005221 -- inc (r1)+ (to 3052)
|
| 636 |
|
|
005232 -- inc @(r2)+ (to 3054)
|
| 637 |
|
|
005243 -- inc -(r3) (to 3056)
|
| 638 |
|
|
005254 -- inc @-(r4) (to 3060)
|
| 639 |
|
|
005260 -- inc 12(r0) (to 3062)
|
| 640 |
|
|
000012
|
| 641 |
|
|
005270 -- inc @24(r0) (to 3064)
|
| 642 |
|
|
#3020
|
| 643 |
|
|
000024
|
| 644 |
|
|
000000 -- halt
|
| 645 |
|
|
#
|
| 646 |
|
|
wal 003050 -- data:
|
| 647 |
|
|
bwm 7
|
| 648 |
|
|
000110 -- mem(3050)=110
|
| 649 |
|
|
000120 -- mem(3052)=120
|
| 650 |
|
|
000130 -- mem(3054)=130
|
| 651 |
|
|
000140 -- mem(3056)=140
|
| 652 |
|
|
000150 -- mem(3060)=150
|
| 653 |
|
|
000160 -- mem(3062)=160
|
| 654 |
|
|
000170 -- mem(3064)=170
|
| 655 |
|
|
wal 003070 -- data:
|
| 656 |
|
|
bwm 3
|
| 657 |
|
|
003054 -- mem(3070)=3054
|
| 658 |
|
|
003060 -- mem(3072)=3060
|
| 659 |
|
|
003064 -- mem(3074)=3064
|
| 660 |
|
|
#
|
| 661 |
|
|
C Exec code 10 (dstm modes: inc xxx: all non-r modes)
|
| 662 |
|
|
#
|
| 663 |
|
|
wr0 003050 -- r0=3050
|
| 664 |
|
|
wr1 003052 -- r1=3052
|
| 665 |
|
|
wr2 003070 -- r2=3070
|
| 666 |
|
|
wr3 003060 -- r3=3060
|
| 667 |
|
|
wr4 003074 -- r4=3074
|
| 668 |
|
|
wsp 001400 -- sp=1400
|
| 669 |
30 |
wfjm |
cres
|
| 670 |
2 |
wfjm |
stapc 003000 -- start @ 3000
|
| 671 |
|
|
wtgo
|
| 672 |
|
|
rr0 d=003050 -- ! r0
|
| 673 |
|
|
rr1 d=003054 -- ! r1
|
| 674 |
|
|
rr2 d=003072 -- ! r2
|
| 675 |
|
|
rr3 d=003056 -- ! r3
|
| 676 |
|
|
rr4 d=003072 -- ! r4
|
| 677 |
|
|
rpc d=003024 -- ! pc
|
| 678 |
|
|
wal 003050
|
| 679 |
|
|
brm 7
|
| 680 |
|
|
d=000111 -- ! mem(3050)=111
|
| 681 |
|
|
d=000121 -- ! mem(3052)=121
|
| 682 |
|
|
d=000131 -- ! mem(3054)=131
|
| 683 |
|
|
d=000141 -- ! mem(3056)=141
|
| 684 |
|
|
d=000151 -- ! mem(3060)=151
|
| 685 |
|
|
d=000161 -- ! mem(3062)=161
|
| 686 |
|
|
d=000171 -- ! mem(3064)=171
|
| 687 |
|
|
#-----------------------------------------------------------------------------
|
| 688 |
|
|
C Setup code 11 [base 3100; use 31-32] (dsta modes: jsr pc,xxx: all non-r modes)
|
| 689 |
|
|
#
|
| 690 |
|
|
wal 003100 -- code:
|
| 691 |
|
|
bwm 10
|
| 692 |
|
|
004710 -- jsr pc,(r0) (to 3210) r0->3210
|
| 693 |
|
|
004721 -- jsr pc,(r1)+ (to 3220) r1->3220
|
| 694 |
|
|
004732 -- jsr pc,@(r2)+ (to 3230) r2->3140->3230
|
| 695 |
|
|
004743 -- jsr pc,-(r3) (to 3240) r3->3242
|
| 696 |
|
|
004754 -- jsr pc,@-(r4) (to 3250) r4->3142->3250
|
| 697 |
|
|
004760 -- jsr pc,50(r0) (to 3260) r0->3210+50->3260
|
| 698 |
|
|
000050
|
| 699 |
|
|
004770 -- jsr pc,@-44(r0) (to 3270) r0->3210-44->3144->3270
|
| 700 |
|
|
#3120
|
| 701 |
|
|
177734
|
| 702 |
|
|
000000 -- halt
|
| 703 |
|
|
#
|
| 704 |
|
|
wal 003140 -- data:
|
| 705 |
|
|
bwm 3
|
| 706 |
|
|
003230 -- mem(3140)=3230
|
| 707 |
|
|
003250 -- mem(3142)=3250
|
| 708 |
|
|
003270 -- mem(3144)=3270
|
| 709 |
|
|
#
|
| 710 |
|
|
wal 003210 -- code:
|
| 711 |
|
|
bwm 28
|
| 712 |
|
|
012725 -- mov #110,(r5)+
|
| 713 |
|
|
000110
|
| 714 |
|
|
000207 -- rts pc
|
| 715 |
|
|
000000 -- halt
|
| 716 |
|
|
#3220
|
| 717 |
|
|
012725 -- mov #120,(r5)+
|
| 718 |
|
|
000120
|
| 719 |
|
|
000207 -- rts pc
|
| 720 |
|
|
000000 -- halt
|
| 721 |
|
|
012725 -- mov #130,(r5)+
|
| 722 |
|
|
000130
|
| 723 |
|
|
000207 -- rts pc
|
| 724 |
|
|
000000 -- halt
|
| 725 |
|
|
#3240
|
| 726 |
|
|
012725 -- mov #140,(r5)+
|
| 727 |
|
|
000140
|
| 728 |
|
|
000207 -- rts pc
|
| 729 |
|
|
000000 -- halt
|
| 730 |
|
|
012725 -- mov #150,(r5)+
|
| 731 |
|
|
000150
|
| 732 |
|
|
000207 -- rts pc
|
| 733 |
|
|
000000 -- halt
|
| 734 |
|
|
#3260
|
| 735 |
|
|
012725 -- mov #160,(r5)+
|
| 736 |
|
|
000160
|
| 737 |
|
|
000207 -- rts pc
|
| 738 |
|
|
000000 -- halt
|
| 739 |
|
|
012725 -- mov #170,(r5)+
|
| 740 |
|
|
000170
|
| 741 |
|
|
000207 -- rts pc
|
| 742 |
|
|
000000 -- halt
|
| 743 |
|
|
#
|
| 744 |
|
|
C Exec code 11 (dsta modes: jsr pc,xxx: all non-r modes)
|
| 745 |
|
|
#
|
| 746 |
|
|
wr0 003210 -- r0=3210
|
| 747 |
|
|
wr1 003220 -- r1=3220
|
| 748 |
|
|
wr2 003140 -- r2=3140
|
| 749 |
|
|
wr3 003242 -- r3=3242
|
| 750 |
|
|
wr4 003144 -- r4=3144
|
| 751 |
|
|
wr5 003160 -- r5=3160
|
| 752 |
|
|
wsp 001400 -- sp=1400
|
| 753 |
30 |
wfjm |
cres
|
| 754 |
2 |
wfjm |
stapc 003100 -- start @ 3100
|
| 755 |
|
|
wtgo
|
| 756 |
|
|
rr0 d=003210 -- ! r0=3210
|
| 757 |
|
|
rr1 d=003222 -- ! r1=3222
|
| 758 |
|
|
rr2 d=003142 -- ! r2=3142
|
| 759 |
|
|
rr3 d=003240 -- ! r3=3240
|
| 760 |
|
|
rr4 d=003142 -- ! r4=3142
|
| 761 |
|
|
rr5 d=003176 -- ! r5=3176
|
| 762 |
|
|
rsp d=001400 -- ! sp
|
| 763 |
|
|
rpc d=003124 -- ! pc
|
| 764 |
|
|
wal 003160
|
| 765 |
|
|
brm 7
|
| 766 |
|
|
d=000110 -- ! mem(3160)=110
|
| 767 |
|
|
d=000120 -- ! mem(3162)=120
|
| 768 |
|
|
d=000130 -- ! mem(3164)=130
|
| 769 |
|
|
d=000140 -- ! mem(3166)=140
|
| 770 |
|
|
d=000150 -- ! mem(3170)=150
|
| 771 |
|
|
d=000160 -- ! mem(3172)=160
|
| 772 |
|
|
d=000170 -- ! mem(3174)=170
|
| 773 |
|
|
#-----------------------------------------------------------------------------
|
| 774 |
|
|
C Setup code 12 [base 3300; use 33-34] (PSW access via sex,clx,spl,mov, and clr)
|
| 775 |
|
|
#
|
| 776 |
|
|
wal 003300 -- code:
|
| 777 |
|
|
bwm 23
|
| 778 |
|
|
011025 -- mov (r0),(r5)+
|
| 779 |
|
|
012710 -- mov #030000,(r0) ; write full PSW: pmode=um
|
| 780 |
|
|
030000
|
| 781 |
|
|
011025 -- mov (r0),(r5)+
|
| 782 |
|
|
000263 -- se(v,c)
|
| 783 |
|
|
011025 -- mov (r0),(r5)+
|
| 784 |
|
|
000237 -- spl 7
|
| 785 |
|
|
011025 -- mov (r0),(r5)+
|
| 786 |
|
|
#3320
|
| 787 |
|
|
000274 -- se(n,z)
|
| 788 |
|
|
011025 -- mov (r0),(r5)+
|
| 789 |
|
|
000233 -- spl 3
|
| 790 |
|
|
011025 -- mov (r0),(r5)+
|
| 791 |
|
|
000241 -- clc
|
| 792 |
|
|
011025 -- mov (r0),(r5)+
|
| 793 |
|
|
112710 -- movb #40,(r0) ; write PSW_low (set pri=1)
|
| 794 |
|
|
000040
|
| 795 |
|
|
#3340
|
| 796 |
|
|
011025 -- mov (r0),(r5)+
|
| 797 |
|
|
112711 -- movb #20,(r1) ; write PSW_high: pmode=sm
|
| 798 |
|
|
000020
|
| 799 |
|
|
011025 -- mov (r0),(r5)+
|
| 800 |
|
|
005010 -- clr (r0)
|
| 801 |
|
|
011025 -- mov (r0),(r5)+
|
| 802 |
|
|
000000 -- halt
|
| 803 |
|
|
#
|
| 804 |
|
|
C Exec code 12 (PSW access via sex,clx,spl,mov, and clr)
|
| 805 |
|
|
#
|
| 806 |
|
|
wps 000017 -- psw: set all condition codes (to check psw clear @ start)
|
| 807 |
|
|
#
|
| 808 |
|
|
wr0 177776 -- r0=177776
|
| 809 |
|
|
wr1 177777 -- r1=177777
|
| 810 |
|
|
wr5 003400 -- r5=3400
|
| 811 |
|
|
wsp 001400 -- sp=1400
|
| 812 |
30 |
wfjm |
cres
|
| 813 |
2 |
wfjm |
stapc 003300 -- start @ 3300
|
| 814 |
|
|
wtgo
|
| 815 |
|
|
rr5 d=003424 -- ! r5=3424
|
| 816 |
|
|
rpc d=003356 -- ! pc
|
| 817 |
|
|
wal 003400
|
| 818 |
|
|
brm 10
|
| 819 |
|
|
d=000340 -- ! mem(3400) after start
|
| 820 |
|
|
d=030000 -- ! mem(3402) after mov #030000,(r0)
|
| 821 |
|
|
d=030003 -- ! mem(3404) after se(v,c) (VC)
|
| 822 |
|
|
d=030341 -- ! mem(3406) after spl 7 (pri=7,C)
|
| 823 |
|
|
d=030355 -- ! mem(3410) after se(n,z) (pri=7,NZC)
|
| 824 |
|
|
d=030141 -- ! mem(3412) after spl 3 (pri=3,C)
|
| 825 |
|
|
d=030140 -- ! mem(3414) after clc (pri=3)
|
| 826 |
|
|
d=030040 -- ! mem(3416) after movb #40,(r0) (pri=1)
|
| 827 |
|
|
d=010040 -- ! mem(3420) after movb #20,(r1) pmode=sm
|
| 828 |
|
|
d=000000 -- ! mem(3422) after clr (r0)
|
| 829 |
|
|
#-----------------------------------------------------------------------------
|
| 830 |
|
|
C Setup code 13 [base 3500] (test WAIT and rdma (bwm/rwm while CPU running)
|
| 831 |
|
|
#
|
| 832 |
|
|
#[[off]] - can't emulate 'sto' command in simh, rdma meaningless in simh
|
| 833 |
|
|
#
|
| 834 |
|
|
wal 003500 -- code 13.1 (to be stepped)
|
| 835 |
|
|
bwm 4
|
| 836 |
|
|
000001 -- wait
|
| 837 |
|
|
000001 -- wait
|
| 838 |
|
|
000001 -- wait
|
| 839 |
|
|
000000 -- halt
|
| 840 |
|
|
#
|
| 841 |
|
|
wal 003520 -- code 13.2 (busy loop)
|
| 842 |
|
|
bwm 3
|
| 843 |
|
|
005700 -- tst r0
|
| 844 |
|
|
001776 -- beq .-1
|
| 845 |
|
|
000000 -- halt
|
| 846 |
|
|
#
|
| 847 |
|
|
wal 003540 -- code 13.3 (just a WAIT)
|
| 848 |
|
|
bwm 2
|
| 849 |
|
|
000001 -- wait
|
| 850 |
|
|
000000 -- halt
|
| 851 |
|
|
#
|
| 852 |
|
|
C Exec code 13.1a (run WAIT)
|
| 853 |
|
|
#
|
| 854 |
30 |
wfjm |
cres
|
| 855 |
2 |
wfjm |
stapc 003500 -- start @ 3500
|
| 856 |
|
|
.wait 20 -- let it go
|
| 857 |
|
|
rpc d=003502 -- ! should hang here ...
|
| 858 |
|
|
.wait 20 -- let it go
|
| 859 |
|
|
rpc d=003502 -- ! should hang here ...
|
| 860 |
27 |
wfjm |
.sdef s=00001000
|
| 861 |
2 |
wfjm |
sto
|
| 862 |
27 |
wfjm |
.sdef s=00000000,01110000
|
| 863 |
2 |
wfjm |
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
|
| 864 |
|
|
rpc d=003502 -- ! should stay there ...
|
| 865 |
|
|
#
|
| 866 |
|
|
C Exec code 13.1b (step WAIT)
|
| 867 |
|
|
wpc 003500 -- pc=3500
|
| 868 |
|
|
step -- step over 1st WAIT
|
| 869 |
|
|
rpc d=003502 -- !
|
| 870 |
|
|
step -- step over 2nd WAIT
|
| 871 |
|
|
rpc d=003504 -- !
|
| 872 |
|
|
step -- step over 3rd WAIT
|
| 873 |
|
|
rpc d=003506 -- !
|
| 874 |
|
|
step -- step over HALT
|
| 875 |
|
|
rpc d=003510 -- !
|
| 876 |
|
|
#
|
| 877 |
|
|
C Exec code 13.2 (test bwm/brm while CPU busy looping)
|
| 878 |
|
|
wr0 000000 -- r0=0
|
| 879 |
30 |
wfjm |
cres
|
| 880 |
2 |
wfjm |
stapc 003520 -- start @ 3520
|
| 881 |
|
|
#
|
| 882 |
|
|
wal 003560 -- write data while CPU active
|
| 883 |
|
|
bwm 8
|
| 884 |
|
|
003560
|
| 885 |
|
|
003562
|
| 886 |
|
|
003564
|
| 887 |
|
|
003566
|
| 888 |
|
|
003570
|
| 889 |
|
|
003572
|
| 890 |
|
|
003574
|
| 891 |
|
|
003576
|
| 892 |
|
|
wal 003560 -- read data while CPU active
|
| 893 |
|
|
brm 8
|
| 894 |
|
|
d=003560
|
| 895 |
|
|
d=003562
|
| 896 |
|
|
d=003564
|
| 897 |
|
|
d=003566
|
| 898 |
|
|
d=003570
|
| 899 |
|
|
d=003572
|
| 900 |
|
|
d=003574
|
| 901 |
|
|
d=003576
|
| 902 |
|
|
#
|
| 903 |
|
|
wr0 000001 -- r0=1 --> should end loop
|
| 904 |
|
|
wtgo
|
| 905 |
|
|
rpc d=003526 -- !
|
| 906 |
|
|
#
|
| 907 |
|
|
C Exec code 13.3 (test bwm/brm while CPU on WAIT)
|
| 908 |
|
|
#
|
| 909 |
30 |
wfjm |
cres
|
| 910 |
2 |
wfjm |
stapc 003540 -- start @ 3540
|
| 911 |
|
|
#
|
| 912 |
|
|
wal 003560 -- write data while CPU active
|
| 913 |
|
|
bwm 8
|
| 914 |
|
|
073560
|
| 915 |
|
|
073562
|
| 916 |
|
|
073564
|
| 917 |
|
|
073566
|
| 918 |
|
|
073570
|
| 919 |
|
|
073572
|
| 920 |
|
|
073574
|
| 921 |
|
|
073576
|
| 922 |
|
|
wal 003560 -- read data while CPU active
|
| 923 |
|
|
brm 8
|
| 924 |
|
|
d=073560
|
| 925 |
|
|
d=073562
|
| 926 |
|
|
d=073564
|
| 927 |
|
|
d=073566
|
| 928 |
|
|
d=073570
|
| 929 |
|
|
d=073572
|
| 930 |
|
|
d=073574
|
| 931 |
|
|
d=073576
|
| 932 |
|
|
#
|
| 933 |
27 |
wfjm |
.sdef s=00001000
|
| 934 |
2 |
wfjm |
sto
|
| 935 |
27 |
wfjm |
.sdef s=00000000,01110000
|
| 936 |
2 |
wfjm |
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
|
| 937 |
|
|
rpc d=003542 -- !
|
| 938 |
|
|
#[[on]]
|
| 939 |
|
|
#-----------------------------------------------------------------------------
|
| 940 |
|
|
# Setup code 14 --- code 14 doesn't exist anymore...
|
| 941 |
|
|
#-----------------------------------------------------------------------------
|
| 942 |
|
|
C Setup code 15 [base 3600; use 36-37] (test 4 traps)
|
| 943 |
|
|
#
|
| 944 |
|
|
wal 003600 -- code:
|
| 945 |
|
|
bwm 5
|
| 946 |
|
|
000003 -- bpt (to 14)
|
| 947 |
|
|
000004 -- iot (to 20)
|
| 948 |
|
|
104077 -- emt 77 (to 30)
|
| 949 |
|
|
104477 -- trap 77 (to 34)
|
| 950 |
|
|
000000 -- halt
|
| 951 |
|
|
#
|
| 952 |
|
|
wal 003620 -- code: trap handlers
|
| 953 |
|
|
bwm 11
|
| 954 |
|
|
010025 -- mov r0,(r5)+ (@ 3620)
|
| 955 |
|
|
000405 -- br .+10
|
| 956 |
|
|
010125 -- mov r1,(r5)+ (@ 3624)
|
| 957 |
|
|
000403 -- br .+6
|
| 958 |
|
|
010225 -- mov r2,(r5)+ (@ 3630)
|
| 959 |
|
|
000401 -- br .+2
|
| 960 |
|
|
010325 -- mov r3,(r5)+ (@ 3634)
|
| 961 |
|
|
#3640
|
| 962 |
|
|
011604 -- mov (sp),r4 ; r4 points after instruction
|
| 963 |
|
|
016425 -- mov -2(r4),(r5)+ ; load instruction
|
| 964 |
|
|
177776
|
| 965 |
|
|
000002 -- rti
|
| 966 |
|
|
#
|
| 967 |
|
|
wal 000014 -- vector: 14+20
|
| 968 |
|
|
bwm 4
|
| 969 |
|
|
003620 -- PC:3620
|
| 970 |
|
|
000000 -- PS:0
|
| 971 |
|
|
003624 -- PC:3624
|
| 972 |
|
|
000000 -- PS:0
|
| 973 |
|
|
wal 000030 -- vector: 30+34
|
| 974 |
|
|
bwm 4
|
| 975 |
|
|
003630 -- PC:3630
|
| 976 |
|
|
000000 -- PS:0
|
| 977 |
|
|
003634 -- PC:3634
|
| 978 |
|
|
000000 -- PS:0
|
| 979 |
|
|
#
|
| 980 |
|
|
C Exec code 15 (test 4 traps)
|
| 981 |
|
|
#
|
| 982 |
|
|
wr0 000011 -- r0=11
|
| 983 |
|
|
wr1 000022 -- r1=22
|
| 984 |
|
|
wr2 000033 -- r2=33
|
| 985 |
|
|
wr3 000044 -- r3=44
|
| 986 |
|
|
wr5 003700 -- r5=3700
|
| 987 |
|
|
wsp 001400 -- sp=140
|
| 988 |
30 |
wfjm |
cres
|
| 989 |
2 |
wfjm |
stapc 003600 -- start @ 3600
|
| 990 |
|
|
wtgo
|
| 991 |
|
|
rr5 d=003720 -- ! r5=3720
|
| 992 |
|
|
rsp d=001400 -- ! sp
|
| 993 |
|
|
rpc d=003612 -- ! pc
|
| 994 |
|
|
wal 003700
|
| 995 |
|
|
brm 8
|
| 996 |
|
|
d=000011 -- ! mem(3700)=11
|
| 997 |
|
|
d=000003 -- ! mem(3702)=3
|
| 998 |
|
|
d=000022 -- ! mem(3704)=22
|
| 999 |
|
|
d=000004 -- ! mem(3706)=4
|
| 1000 |
|
|
d=000033 -- ! mem(3710)=33
|
| 1001 |
|
|
d=104077 -- ! mem(3712)=104077
|
| 1002 |
|
|
d=000044 -- ! mem(3714)=44
|
| 1003 |
|
|
d=104477 -- ! mem(3716)=104477
|
| 1004 |
|
|
wal 000014 -- vector: 14+20 -> trap catcher again
|
| 1005 |
|
|
bwm 4
|
| 1006 |
|
|
000016 -- PC:16
|
| 1007 |
|
|
000000 -- PS:0
|
| 1008 |
|
|
000022 -- PC:22
|
| 1009 |
|
|
000000 -- PS:0
|
| 1010 |
|
|
wal 000030 -- vector: 30+34 -> trap catcher again
|
| 1011 |
|
|
bwm 4
|
| 1012 |
|
|
000032 -- PC:32
|
| 1013 |
|
|
000000 -- PS:0
|
| 1014 |
|
|
000036 -- PC:36
|
| 1015 |
|
|
000000 -- PS:0
|
| 1016 |
|
|
#-----------------------------------------------------------------------------
|
| 1017 |
|
|
C Setup code 16 [base 4000] (enable MMU, check ssr1, ssr2 response)
|
| 1018 |
|
|
#
|
| 1019 |
|
|
wal 172516 -- SSR3
|
| 1020 |
|
|
wmi 000002 -- I/D enabled for sm only (to check CRESET)
|
| 1021 |
|
|
wal 177572 -- SSR0
|
| 1022 |
|
|
wmi 000001 -- set enable bit
|
| 1023 |
|
|
#
|
| 1024 |
|
|
wal 004000 -- code (to be single stepped...)
|
| 1025 |
|
|
bwm 7
|
| 1026 |
|
|
011105 -- mov (r1),r5
|
| 1027 |
|
|
012105 -- mov (r1)+,r5
|
| 1028 |
|
|
014105 -- mov -(r1),r5
|
| 1029 |
|
|
012122 -- mov (r1)+,(r2)+
|
| 1030 |
|
|
112105 -- movb (r1)+,r5
|
| 1031 |
|
|
112721 -- movb #200,(r1)+
|
| 1032 |
|
|
000200
|
| 1033 |
|
|
#
|
| 1034 |
|
|
wal 004030 -- code test 1:
|
| 1035 |
|
|
wmi 000000 -- halt
|
| 1036 |
|
|
#
|
| 1037 |
|
|
wal 004040 -- data:
|
| 1038 |
|
|
bwm 2
|
| 1039 |
|
|
000001
|
| 1040 |
|
|
000300
|
| 1041 |
|
|
#
|
| 1042 |
|
|
C Exec code 16 (enable MMU, check ssr1, ssr2 response)
|
| 1043 |
|
|
#
|
| 1044 |
|
|
wr1 004040 -- r1=4040
|
| 1045 |
|
|
wr2 004060 -- r2=4060
|
| 1046 |
|
|
wsp 001400 -- sp=1400
|
| 1047 |
|
|
wpc 004000 -- pc=4000
|
| 1048 |
|
|
step -- step (mov (r1),r5)
|
| 1049 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1050 |
|
|
brm 3
|
| 1051 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 1052 |
|
|
d=000000 -- ! SSR1:
|
| 1053 |
|
|
d=004000 -- ! SSR2: 4000 (eff. PC)
|
| 1054 |
|
|
rr1 d=004040 -- ! r1
|
| 1055 |
|
|
rr5 d=000001 -- ! r5
|
| 1056 |
|
|
step -- step (mov (r1)+,r5)
|
| 1057 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1058 |
|
|
brm 3
|
| 1059 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 1060 |
|
|
d=000021 -- ! SSR1: rb none; ra=1,+2
|
| 1061 |
|
|
d=004002 -- ! SSR2: 4002 (eff. PC)
|
| 1062 |
|
|
rr1 d=004042 -- ! r1
|
| 1063 |
|
|
rr5 d=000001 -- ! r5
|
| 1064 |
|
|
step -- step (mov -(r1),r5)
|
| 1065 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1066 |
|
|
brm 3
|
| 1067 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 1068 |
|
|
d=000361 -- ! SSR1: rb none; ra=1,-2
|
| 1069 |
|
|
d=004004 -- ! SSR2: 4004 (eff. PC)
|
| 1070 |
|
|
rr1 d=004040 -- ! r1
|
| 1071 |
|
|
rr5 d=000001 -- ! r5
|
| 1072 |
|
|
step -- step (mov (r1)+,(r2)+)
|
| 1073 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1074 |
|
|
brm 3
|
| 1075 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 1076 |
|
|
d=011021 -- ! SSR1: rb=2,2; ra=1,2
|
| 1077 |
|
|
d=004006 -- ! SSR2: 4006 (eff. PC)
|
| 1078 |
|
|
rr1 d=004042 -- ! r1
|
| 1079 |
|
|
rr2 d=004062 -- ! r2
|
| 1080 |
|
|
step -- step (movb (r1)+,r5)
|
| 1081 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1082 |
|
|
brm 3
|
| 1083 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 1084 |
|
|
d=000011 -- ! SSR1: rb=none; ra=1,1
|
| 1085 |
|
|
d=004010 -- ! SSR2: 4010 (eff. PC)
|
| 1086 |
|
|
rr1 d=004043 -- ! r1
|
| 1087 |
|
|
rr5 d=177700 -- ! r5
|
| 1088 |
|
|
step -- step (movb #200,(r1)+)
|
| 1089 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1090 |
|
|
brm 3
|
| 1091 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 1092 |
|
|
d=004427 -- ! SSR1: rb=1,1; ra=7,2
|
| 1093 |
|
|
d=004012 -- ! SSR2: 4012 (eff. PC)
|
| 1094 |
|
|
rr1 d=004044 -- ! r1
|
| 1095 |
|
|
#
|
| 1096 |
|
|
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start)
|
| 1097 |
|
|
#
|
| 1098 |
|
|
wps 000000 -- psw: set pri=0
|
| 1099 |
30 |
wfjm |
cres
|
| 1100 |
2 |
wfjm |
stapc 004030 -- start @ 4030 (just HALT, testing console reset)
|
| 1101 |
|
|
wtgo
|
| 1102 |
|
|
rpc d=004032 -- ! pc=4032
|
| 1103 |
|
|
rps d=000340 -- ! psw: reset by CRESET
|
| 1104 |
|
|
wal 172516 -- SSR3
|
| 1105 |
|
|
rmi d=000000 -- ! cleared by CRESET
|
| 1106 |
|
|
wal 177572 -- SSR0
|
| 1107 |
|
|
rmi d=000000 -- ! cleared by CRESET
|
| 1108 |
|
|
#-----------------------------------------------------------------------------
|
| 1109 |
|
|
C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test)
|
| 1110 |
|
|
#
|
| 1111 |
|
|
wal 004100 -- code: (length 70)
|
| 1112 |
|
|
bwm 32
|
| 1113 |
|
|
010124 -- mov r1,(r4)+ (#4711, #123456)
|
| 1114 |
|
|
020124 -- cmp r1,(r4)+ (#4711, #123456)
|
| 1115 |
|
|
020224 -- cmp r2,(r4)+ (#123456,#4711)
|
| 1116 |
|
|
020124 -- cmp r1,(r4)+ (#4711, #4711)
|
| 1117 |
|
|
005024 -- clr (r4)+ (#123456)
|
| 1118 |
|
|
030124 -- bit r1,(r4)+ (#4711, #11)
|
| 1119 |
|
|
030124 -- bit r1,(r4)+ (#4711, #66)
|
| 1120 |
|
|
040124 -- bic r1,(r4)+ (#4711, #123456)
|
| 1121 |
|
|
#4120
|
| 1122 |
|
|
050124 -- bis r1,(r4)+ (#4711, #123456)
|
| 1123 |
|
|
060124 -- add r1,(r4)+ (#4711, #123456)
|
| 1124 |
|
|
160124 -- sub r1,(r4)+ (#4711, #123456)
|
| 1125 |
|
|
005124 -- com (r4)+ (#123456)
|
| 1126 |
|
|
005224 -- inc (r4)+ (#123456)
|
| 1127 |
|
|
005324 -- dec (r4)+ (#123456)
|
| 1128 |
|
|
005424 -- neg (r4)+ (#123456)
|
| 1129 |
|
|
005724 -- tst (r4)+ (#123456)
|
| 1130 |
|
|
#4140
|
| 1131 |
|
|
006024 -- ror (r4)+ (#100201) Cin=0; Cout=1
|
| 1132 |
|
|
006024 -- ror (r4)+ (#002201) Cin=1; Cout=1
|
| 1133 |
|
|
006124 -- rol (r4)+ (#100200) Cin=1; Cout=1
|
| 1134 |
|
|
006224 -- asr (r4)+ (#200)
|
| 1135 |
|
|
006224 -- asr (r4)+ (#100200)
|
| 1136 |
|
|
006324 -- asl (r4)+ (#200)
|
| 1137 |
|
|
006324 -- asl (r4)+ (#100200)
|
| 1138 |
|
|
060124 -- add r1,(r4)+ (#4711, #077777)
|
| 1139 |
|
|
#4160
|
| 1140 |
|
|
005524 -- adc (r4)+ (#200)
|
| 1141 |
|
|
160124 -- sub r1,(r4)+ (#4711, #4700)
|
| 1142 |
|
|
005624 -- sbc (r4)+ (#200)
|
| 1143 |
|
|
000324 -- swap (r4)+ (#111000)
|
| 1144 |
|
|
006724 -- sxt (r4)+ (#111111 with N=1)
|
| 1145 |
|
|
074124 -- xor r1,(r4)+ (#070707,#4711)
|
| 1146 |
|
|
006724 -- sxt (r4)+ (#111111 with N=0)
|
| 1147 |
|
|
000000 -- halt
|
| 1148 |
|
|
#
|
| 1149 |
|
|
wal 000014 -- vector: 14
|
| 1150 |
|
|
bwm 2
|
| 1151 |
|
|
004270 -- PC:4270
|
| 1152 |
|
|
000000 -- PS:0
|
| 1153 |
|
|
#-----
|
| 1154 |
|
|
wal 004270 -- code: (trap 14):
|
| 1155 |
|
|
bwm 3
|
| 1156 |
|
|
016625 -- mov 2(sp),(r5)+
|
| 1157 |
|
|
000002
|
| 1158 |
|
|
000006 -- rtt
|
| 1159 |
|
|
#-----
|
| 1160 |
|
|
wal 004300 -- data 1: (length 66)
|
| 1161 |
|
|
bwm 31
|
| 1162 |
|
|
123456 --
|
| 1163 |
|
|
123456 --
|
| 1164 |
|
|
004711 --
|
| 1165 |
|
|
004711 --
|
| 1166 |
|
|
123456 --
|
| 1167 |
|
|
000011 --
|
| 1168 |
|
|
000066 --
|
| 1169 |
|
|
123456 --
|
| 1170 |
|
|
#4320
|
| 1171 |
|
|
123456 --
|
| 1172 |
|
|
123456 --
|
| 1173 |
|
|
123456 --
|
| 1174 |
|
|
123456 --
|
| 1175 |
|
|
123456 --
|
| 1176 |
|
|
123456 --
|
| 1177 |
|
|
123456 --
|
| 1178 |
|
|
123456 --
|
| 1179 |
|
|
#4340
|
| 1180 |
|
|
100201 --
|
| 1181 |
|
|
002201 --
|
| 1182 |
|
|
100200 --
|
| 1183 |
|
|
000200 --
|
| 1184 |
|
|
100200 --
|
| 1185 |
|
|
000200 --
|
| 1186 |
|
|
100200 --
|
| 1187 |
|
|
177000 --
|
| 1188 |
|
|
#4360
|
| 1189 |
|
|
000200 --
|
| 1190 |
|
|
004701 --
|
| 1191 |
|
|
000200 --
|
| 1192 |
|
|
111000 --
|
| 1193 |
|
|
111111 --
|
| 1194 |
|
|
070707 --
|
| 1195 |
|
|
111111 --
|
| 1196 |
|
|
#
|
| 1197 |
|
|
C Exec code 17 (basic instruction and cc test)
|
| 1198 |
|
|
#
|
| 1199 |
|
|
wr1 004711 -- r1=4711
|
| 1200 |
|
|
wr2 123456 -- r2=123456
|
| 1201 |
|
|
wr4 004300 -- r4=4300
|
| 1202 |
|
|
wr5 004500 -- r5=4500
|
| 1203 |
|
|
wsp 001374 -- sp=1374
|
| 1204 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
| 1205 |
|
|
bwm 2
|
| 1206 |
|
|
004100 -- start address (code 17 @ 4100)
|
| 1207 |
|
|
000020 -- set T flag in PSW
|
| 1208 |
30 |
wfjm |
cres
|
| 1209 |
2 |
wfjm |
stapc 004274 -- start @ 4274 -> rtt -> 4100 from stack
|
| 1210 |
|
|
wtgo
|
| 1211 |
|
|
rr1 d=004711 -- ! r1=4711
|
| 1212 |
|
|
rr2 d=123456 -- ! r2=123456
|
| 1213 |
|
|
rr4 d=004376 -- ! r4=4376
|
| 1214 |
|
|
rr5 d=004576 -- ! r5=4576
|
| 1215 |
|
|
rsp d=001400 -- ! sp=1400
|
| 1216 |
|
|
rpc d=004200 -- ! pc=4200
|
| 1217 |
|
|
wal 004300
|
| 1218 |
|
|
brm 31
|
| 1219 |
|
|
d=004711 -- ! mem(4300)=004711; mov r1,(r4)+ (#4711, #123456)
|
| 1220 |
|
|
d=123456 -- ! mem(4302)=123456; cmp r1,(r4)+ (#4711, #123456)
|
| 1221 |
|
|
d=004711 -- ! mem(4304)=004711; cmp r1,(r4)+ (#123456,#4711)
|
| 1222 |
|
|
d=004711 -- ! mem(4306)=004711; cmp r1,(r4)+ (#4711, #4711)
|
| 1223 |
|
|
d=000000 -- ! mem(4310)=000000; clr (r4)+ (#123456)
|
| 1224 |
|
|
d=000011 -- ! mem(4312)=000011; bit r1,(r4)+ (#4711, #11)
|
| 1225 |
|
|
d=000066 -- ! mem(4314)=000066; bit r1,(r4)+ (#4711, #66)
|
| 1226 |
|
|
d=123046 -- ! mem(4316)=123046; bic r1,(r4)+ (#4711, #123456)
|
| 1227 |
|
|
d=127757 -- ! mem(4320)=127757; bis r1,(r4)+ (#4711, #123456)
|
| 1228 |
|
|
d=130367 -- ! mem(4322)=130367; add r1,(r4)+ (#4711, #123456)
|
| 1229 |
|
|
d=116545 -- ! mem(4324)=116545; sub r1,(r4)+ (#4711, #123456)
|
| 1230 |
|
|
d=054321 -- ! mem(4326)=054321; com (r4)+ (#123456)
|
| 1231 |
|
|
d=123457 -- ! mem(4330)=123457; inc (r4)+ (#123456)
|
| 1232 |
|
|
d=123455 -- ! mem(4332)=123455; dec (r4)+ (#123456)
|
| 1233 |
|
|
d=054322 -- ! mem(4334)=054322; neg (r4)+ (#123456)
|
| 1234 |
|
|
d=123456 -- ! mem(4336)=123456; tst (r4)+ (#123456)
|
| 1235 |
|
|
d=040100 -- ! mem(4340)=040100; ror (r4)+ (#100201)
|
| 1236 |
|
|
d=101100 -- ! mem(4342)=101100; ror (r4)+ (#002201)
|
| 1237 |
|
|
d=000401 -- ! mem(4344)=000401; rol (r4)+ (#100200)
|
| 1238 |
|
|
d=000100 -- ! mem(4346)=000100; asr (r4)+ (#200)
|
| 1239 |
|
|
d=140100 -- ! mem(4350)=140100; asr (r4)+ (#100200)
|
| 1240 |
|
|
d=000400 -- ! mem(4352)=000400; asl (r4)+ (#200)
|
| 1241 |
|
|
d=000400 -- ! mem(4354)=000400; asl (r4)+ (#100200)
|
| 1242 |
|
|
d=003711 -- ! mem(4356)=003711; add r1,(r4)+ (#4711, ,#177000)
|
| 1243 |
|
|
d=000201 -- ! mem(4360)=000201; adc (r4)+ (#200)
|
| 1244 |
|
|
d=177770 -- ! mem(4362)=177770; sub r1,(r4)+ (#4711, #4701)
|
| 1245 |
|
|
d=000177 -- ! mem(4364)=000177; sbc (r4)+ (#200)
|
| 1246 |
|
|
d=000222 -- ! mem(4366)=000222; swap (r4)+ (#111000)
|
| 1247 |
|
|
d=177777 -- ! mem(4370)=177777; sxt (r4)+ (#111111)
|
| 1248 |
|
|
d=074016 -- ! mem(4372)=074016; xor r1,(r4)+ (#070707)
|
| 1249 |
|
|
d=000000 -- ! mem(4374)=000000; sxt (r4)+ (#111111)
|
| 1250 |
|
|
#
|
| 1251 |
|
|
wal 004500 -- NZVC
|
| 1252 |
|
|
brm 31
|
| 1253 |
|
|
d=000020 -- ! mem(4500)=0000; mov r1,(r4)+ (#4711, #123456)
|
| 1254 |
|
|
d=000021 -- ! mem(4502)=000C; cmp r1,(r4)+ (#4711, #123456)
|
| 1255 |
|
|
d=000030 -- ! mem(4504)=N000; cmp r1,(r4)+ (#123456,#4711)
|
| 1256 |
|
|
d=000024 -- ! mem(4506)=0Z00; cmp r1,(r4)+ (#4711, #4711)
|
| 1257 |
|
|
d=000024 -- ! mem(4510)=0Z00; clr (r4)+ (#123456)
|
| 1258 |
|
|
d=000020 -- ! mem(4512)=0000; bit r1,(r4)+ (#4711, #11)
|
| 1259 |
|
|
d=000024 -- ! mem(4514)=0Z00; bit r1,(r4)+ (#4711, #66)
|
| 1260 |
|
|
d=000030 -- ! mem(4516)=N000; bic r1,(r4)+ (#4711, #123456)
|
| 1261 |
|
|
d=000030 -- ! mem(4520)=N000; bis r1,(r4)+ (#4711, #123456)
|
| 1262 |
|
|
d=000030 -- ! mem(4522)=N000; add r1,(r4)+ (#4711, #123456)
|
| 1263 |
|
|
d=000030 -- ! mem(4524)=N000; sub r1,(r4)+ (#4711, #123456)
|
| 1264 |
|
|
d=000021 -- ! mem(4526)=000C; com (r4)+ (#123456)
|
| 1265 |
|
|
d=000031 -- ! mem(4530)=N00C; inc (r4)+ (#123456) keep C!
|
| 1266 |
|
|
d=000031 -- ! mem(4532)=N00C; dec (r4)+ (#123456) keep C!
|
| 1267 |
|
|
d=000021 -- ! mem(4534)=000C; neg (r4)+ (#123456)
|
| 1268 |
|
|
d=000030 -- ! mem(4536)=N000; tst (r4)+ (#123456)
|
| 1269 |
|
|
d=000023 -- ! mem(4540)=00VC; ror (r4)+ (#100201)
|
| 1270 |
|
|
d=000031 -- ! mem(4542)=N00C; ror (r4)+ (#002201)
|
| 1271 |
|
|
d=000023 -- ! mem(4544)=00VC; rol (r4)+ (#100200)
|
| 1272 |
|
|
d=000020 -- ! mem(4546)=0000; asr (r4)+ (#200)
|
| 1273 |
|
|
d=000032 -- ! mem(4550)=N0V0; asr (r4)+ (#100200)
|
| 1274 |
|
|
d=000020 -- ! mem(4552)=0000; asl (r4)+ (#200)
|
| 1275 |
|
|
d=000023 -- ! mem(4554)=00VC; asl (r4)+ (#100200)
|
| 1276 |
|
|
d=000021 -- ! mem(4556)=000C; add r1,(r4)+ (#4711, ,#177000)
|
| 1277 |
|
|
d=000020 -- ! mem(4560)=0000; adc (r4)+ (#200)
|
| 1278 |
|
|
d=000031 -- ! mem(4562)=N00C; sub r1,(r4)+ (#4711, #4701)
|
| 1279 |
|
|
d=000020 -- ! mem(4564)=0000; sbc (r4)+ (#200)
|
| 1280 |
|
|
d=000030 -- ! mem(4566)=N000; swap (r4)+ (#111000)
|
| 1281 |
|
|
d=000030 -- ! mem(4570)=N000; sxt (r4)+ (#111111 with N=1)
|
| 1282 |
|
|
d=000020 -- ! mem(4572)=0000; xor r1,(r4)+ (#4711, #070707)
|
| 1283 |
|
|
d=000024 -- ! mem(4574)=0Z00; sxt (r4)+ (#111111 with N=0)
|
| 1284 |
|
|
#
|
| 1285 |
30 |
wfjm |
cres -- console reset (to clear T flag)
|
| 1286 |
2 |
wfjm |
wal 000014 -- vector: 14 -> trap catcher again
|
| 1287 |
|
|
bwm 2
|
| 1288 |
|
|
000016 -- PC:16
|
| 1289 |
|
|
000000 -- PS:0
|
| 1290 |
|
|
#-----------------------------------------------------------------------------
|
| 1291 |
|
|
C Setup code 20 [base 4700] (check CPUERR and error handling)
|
| 1292 |
|
|
#[[off]]
|
| 1293 |
|
|
wal 004700 -- code (to be single stepped...)
|
| 1294 |
|
|
bwm 11
|
| 1295 |
|
|
010025 -- mov r0,(r5)+ (@ 4777)
|
| 1296 |
|
|
010025 -- mov r0,(r5)+ (@ 150000)
|
| 1297 |
|
|
010025 -- mov r0,(r5)+ (@ 160000)
|
| 1298 |
|
|
000101 -- jmp r1
|
| 1299 |
|
|
004701 -- jsr pc,r1
|
| 1300 |
|
|
000000 -- halt
|
| 1301 |
|
|
014321 -- mov -(r3),(r1)+ (@ 20000)
|
| 1302 |
|
|
024321 -- cmp -(r3),(r1)+ (@ 20400)
|
| 1303 |
|
|
#4720
|
| 1304 |
|
|
064321 -- add -(r3),(r1)+ (@ 20000)
|
| 1305 |
|
|
010046 -- mov r0,-(sp) (@ 340)
|
| 1306 |
|
|
000004 -- iot (with sp=342,...)
|
| 1307 |
|
|
#
|
| 1308 |
|
|
wal 000004 -- vector: 4+10 (trap catch)
|
| 1309 |
|
|
bwm 4
|
| 1310 |
|
|
000006 -- PC:6
|
| 1311 |
|
|
000000 -- PS:0
|
| 1312 |
|
|
000012 -- PC:12
|
| 1313 |
|
|
000000 -- PS:0
|
| 1314 |
|
|
#----------
|
| 1315 |
|
|
C Exec code 20 (check CPUERR and error handling)
|
| 1316 |
|
|
C Exec test 20.1 (odd address abort)
|
| 1317 |
30 |
wfjm |
cres -- console reset
|
| 1318 |
2 |
wfjm |
wps 000000 -- psw: clear
|
| 1319 |
|
|
wal 001374 -- clean stack
|
| 1320 |
|
|
bwm 2
|
| 1321 |
|
|
000000 --
|
| 1322 |
|
|
000000 --
|
| 1323 |
|
|
wal 177766 -- check initial CPUERR (=0!)
|
| 1324 |
|
|
rm d=000000 -- !
|
| 1325 |
|
|
wr0 000011 -- r0=11
|
| 1326 |
|
|
wr5 004775 -- r5=4775
|
| 1327 |
|
|
wsp 001400 -- sp=1400
|
| 1328 |
|
|
wpc 004700 -- pc=4700
|
| 1329 |
|
|
step -- step (mov r0,(r5)+): trap 4 + CPUERR.adderr set [[s:2]]
|
| 1330 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1331 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1332 |
|
|
wal 001374 -- check stack
|
| 1333 |
|
|
brm 2
|
| 1334 |
|
|
d=004702 -- ! pc=4702
|
| 1335 |
|
|
d=000000 -- ! ps=0
|
| 1336 |
|
|
wal 177766 -- check CPUERR
|
| 1337 |
|
|
rm d=000100 -- ! CPUERR: (adderr=1)
|
| 1338 |
|
|
wm 000000 -- any write access will clear CPUERR
|
| 1339 |
|
|
rm d=000000 -- ! CPUERR: 0
|
| 1340 |
|
|
#----------
|
| 1341 |
|
|
C Exec test 20.2 (non-existent memory abort)
|
| 1342 |
|
|
wal 172354 -- kernel I space AR(6)
|
| 1343 |
|
|
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
|
| 1344 |
|
|
wal 177572 -- SSR0
|
| 1345 |
|
|
wmi 000001 -- enable
|
| 1346 |
|
|
wal 172516 -- SSR3
|
| 1347 |
|
|
wmi 000020 -- ena_22bit=1
|
| 1348 |
|
|
#
|
| 1349 |
|
|
wr5 140000 -- r5=140000
|
| 1350 |
|
|
wsp 001400 -- sp=1400
|
| 1351 |
|
|
wpc 004702 -- pc=4702
|
| 1352 |
|
|
step -- step (mov r0,(r5)+): trap 4 + CPUERR.nxm set [[s:2]]
|
| 1353 |
|
|
rpc d=000006 -- ! pc= 6 (trap 4 catch)
|
| 1354 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1355 |
|
|
wal 177766 -- check CPUERR
|
| 1356 |
|
|
rm d=000040 -- ! CPUERR: (nxm=1)
|
| 1357 |
|
|
wm 000000 -- any write access will clear CPUERR
|
| 1358 |
|
|
rm d=000000 -- ! CPUERR: 0
|
| 1359 |
|
|
#
|
| 1360 |
|
|
wal 177572 -- SSR0
|
| 1361 |
|
|
wmi 000000 -- disable
|
| 1362 |
|
|
wal 172354 -- kernel I space AR(6)
|
| 1363 |
|
|
wm 001400 -- 1400 140000 base (default 1-to-1 map)
|
| 1364 |
|
|
#----------
|
| 1365 |
|
|
C Exec test 20.3 (I/O bus timeout abort)
|
| 1366 |
|
|
wr5 160000 -- r5=160000
|
| 1367 |
|
|
wsp 001400 -- sp=1400
|
| 1368 |
|
|
wpc 004704 -- pc=4704
|
| 1369 |
|
|
step -- step (mov r0,(r5)+): trap 4 + CPUERR.iobto set [[s:2]]
|
| 1370 |
|
|
rpc d=000006 -- ! pc= 6 (trap 4 catch)
|
| 1371 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1372 |
|
|
wal 177766 -- check CPUERR
|
| 1373 |
|
|
rm d=000020 -- ! CPUERR: (iobto=1)
|
| 1374 |
|
|
wm 000000 -- clear CPUERR
|
| 1375 |
|
|
#----------
|
| 1376 |
|
|
C Exec test 20.4 (address error abort after jmp r1)
|
| 1377 |
|
|
wsp 001400 -- sp=1400
|
| 1378 |
|
|
wpc 004706 -- pc=4706
|
| 1379 |
|
|
step -- step (jmp r1): trap 10 [[s:2]]
|
| 1380 |
|
|
rpc d=000012 -- ! pc=12 (trap 10 catch)
|
| 1381 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1382 |
|
|
wal 177766 -- check CPUERR
|
| 1383 |
|
|
rm d=000000 -- ! CPUERR: none
|
| 1384 |
|
|
wm 000000 -- clear CPUERR
|
| 1385 |
|
|
#----------
|
| 1386 |
|
|
C Exec test 20.5 (address error abort after jsr pc,r1)
|
| 1387 |
|
|
wsp 001400 -- sp=1400
|
| 1388 |
|
|
wpc 004710 -- pc=4710
|
| 1389 |
|
|
step -- step (jsr pc,r1): trap 10 [[s:2]]
|
| 1390 |
|
|
rpc d=000012 -- ! pc=12 (trap 10 catch)
|
| 1391 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1392 |
|
|
wal 177766 -- check CPUERR
|
| 1393 |
|
|
rm d=000000 -- ! CPUERR: none
|
| 1394 |
|
|
wm 000000 -- clear CPUERR
|
| 1395 |
|
|
#----------
|
| 1396 |
|
|
C Exec test 20.6 (halt in user mode)
|
| 1397 |
|
|
wsp 001400 -- sp=1400 (kernel)
|
| 1398 |
|
|
wpc 004712 -- pc=4712
|
| 1399 |
|
|
wps 170000 -- psw: cmode=pmode=11 (user)
|
| 1400 |
|
|
step -- step (halt): trap 4 + CPUERR.illhlt set [[s:2]]
|
| 1401 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1402 |
|
|
rsp d=001374 -- ! sp=1374 (now kernel again...)
|
| 1403 |
|
|
wal 001374 -- check stack
|
| 1404 |
|
|
brm 2
|
| 1405 |
|
|
d=004714 -- !
|
| 1406 |
|
|
d=170000 -- !
|
| 1407 |
|
|
wal 177766 -- check CPUERR
|
| 1408 |
|
|
rm d=000200 -- ! CPUERR: (illhlt=1)
|
| 1409 |
|
|
wm 000000 -- clear CPUERR
|
| 1410 |
|
|
#
|
| 1411 |
|
|
wps 000000 -- psw: cmode=pmode=0 (kernel)
|
| 1412 |
|
|
#----------
|
| 1413 |
|
|
#
|
| 1414 |
|
|
# test mmu aborts
|
| 1415 |
|
|
#
|
| 1416 |
|
|
wal 000250 -- vector: 250 -> trap catcher
|
| 1417 |
|
|
bwm 2
|
| 1418 |
|
|
000252 -- PC:252
|
| 1419 |
|
|
000000 -- PS:0
|
| 1420 |
|
|
#
|
| 1421 |
|
|
wal 177572 -- SSR0
|
| 1422 |
|
|
wmi 000001 -- enable
|
| 1423 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1424 |
|
|
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
|
| 1425 |
|
|
#----------
|
| 1426 |
|
|
C Exec test 20.7 (non resident abort)
|
| 1427 |
|
|
wr1 020000 -- r1=20000
|
| 1428 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
| 1429 |
|
|
wsp 001400 -- sp=1400
|
| 1430 |
|
|
wpc 004714 -- pc=4714
|
| 1431 |
|
|
step -- step (mov -(r3),(r1)+): abort to 250 [[s:2]]
|
| 1432 |
|
|
rr1 d=020002 -- ! r1=20002 (inc done before trap (here dstw))
|
| 1433 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
| 1434 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
| 1435 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1436 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1437 |
|
|
brm 3
|
| 1438 |
|
|
d=100003 -- ! SSR0: (abo_nonres=1,seg=1,ena=1)
|
| 1439 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
| 1440 |
|
|
d=004714 -- ! SSR2: 4714 (eff. PC)
|
| 1441 |
|
|
#
|
| 1442 |
|
|
wal 177572 -- SSR0
|
| 1443 |
|
|
wmi 000001 -- enable and clear error bits
|
| 1444 |
|
|
#----------
|
| 1445 |
|
|
C Exec test 20.8 (segment length violation abort)
|
| 1446 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1447 |
|
|
wmi 001406 -- slf=3; ed=0(up); acf=6 (w/r)
|
| 1448 |
|
|
#
|
| 1449 |
|
|
wr1 020400 -- r1=20400
|
| 1450 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
| 1451 |
|
|
wsp 001400 -- sp=1400
|
| 1452 |
|
|
wpc 004716 -- pc=4716
|
| 1453 |
|
|
step -- step (cmp -(r3),(r1)+): abort to 250 [[s:2]]
|
| 1454 |
|
|
rr1 d=020402 -- ! r1=20402 (inc done before trap (here dstr))
|
| 1455 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
| 1456 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
| 1457 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1458 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1459 |
|
|
brm 3
|
| 1460 |
|
|
d=040003 -- ! SSR0: (abo_length=1,seg=1,ena=1)
|
| 1461 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
| 1462 |
|
|
d=004716 -- ! SSR2: 4716 (eff. PC)
|
| 1463 |
|
|
#
|
| 1464 |
|
|
wal 177572 -- SSR0
|
| 1465 |
|
|
wmi 000001 -- enable and clear error bits
|
| 1466 |
|
|
#----------
|
| 1467 |
|
|
C Exec test 20.9 (read-only abort)
|
| 1468 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1469 |
|
|
wmi 077402 -- slf=127; ed=0(up); acf=2 (read-only)
|
| 1470 |
|
|
#
|
| 1471 |
|
|
wr1 020000 -- r1=20000
|
| 1472 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
| 1473 |
|
|
wsp 001400 -- sp=1400
|
| 1474 |
|
|
wpc 004720 -- pc=4720
|
| 1475 |
|
|
step -- step (add -(r3),(r1)+): abort to 250 [[s:2]]
|
| 1476 |
|
|
rr1 d=020002 -- ! r1=20000 (inc done before trap (here dstm))
|
| 1477 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
| 1478 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
| 1479 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1480 |
|
|
wal 177572 -- check SSR0/1/2
|
| 1481 |
|
|
brm 3
|
| 1482 |
|
|
d=020003 -- ! SSR0: (abo_rdonly=1,seg=1,ena=1)
|
| 1483 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
| 1484 |
|
|
d=004720 -- ! SSR2: 4720 (eff. PC)
|
| 1485 |
|
|
#
|
| 1486 |
|
|
# mmu back to default setup, disable
|
| 1487 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1488 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
| 1489 |
|
|
wal 177572 -- SSR0
|
| 1490 |
|
|
wmi 000000 -- disable
|
| 1491 |
|
|
#----------
|
| 1492 |
|
|
#
|
| 1493 |
|
|
# test mmu trap
|
| 1494 |
|
|
#
|
| 1495 |
|
|
wal 177572 -- SSR0
|
| 1496 |
|
|
wmi 001001 -- enable, trap enable
|
| 1497 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1498 |
|
|
wmi 077404 -- slf=127; ed=0(up); acf=4 (r/w, trap on r/w)
|
| 1499 |
|
|
#----------
|
| 1500 |
|
|
C Exec test 20.10 (trap on write)
|
| 1501 |
|
|
wr1 020000 -- r1=20000
|
| 1502 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
| 1503 |
|
|
wsp 001400 -- sp=1400
|
| 1504 |
|
|
wpc 004714 -- pc=4714
|
| 1505 |
|
|
step -- step (mov -(r3),(r1)+): trap to 250 [[s:2]]
|
| 1506 |
|
|
rr1 d=020002 -- ! r1=20002 (inc done before trap)
|
| 1507 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
| 1508 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
| 1509 |
|
|
rsp d=001374 -- ! sp=1374
|
| 1510 |
|
|
wal 020000 -- check target area
|
| 1511 |
|
|
rm d=000016 -- ! mem(20000)=16
|
| 1512 |
|
|
wm 000000 -- clean tainted memory
|
| 1513 |
|
|
wal 177572 -- check SSR0
|
| 1514 |
|
|
brm 3
|
| 1515 |
|
|
d=011001 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=0,ena=1)
|
| 1516 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
| 1517 |
|
|
d=004714 -- ! SSR2: 4714 (eff. PC)
|
| 1518 |
|
|
#----------
|
| 1519 |
|
|
C Exec test 20.11 (2nd write, should not trap again)
|
| 1520 |
|
|
wr1 020002 -- r1=20002
|
| 1521 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
| 1522 |
|
|
wsp 001400 -- sp=1400
|
| 1523 |
|
|
wpc 004714 -- pc=4714
|
| 1524 |
|
|
step -- step (mov -(r3),(r1)+): no trap [[s:2]]
|
| 1525 |
|
|
rr1 d=020004 -- ! r1=20004 (inc done before trap)
|
| 1526 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
| 1527 |
|
|
rpc d=004716 -- ! pc=252 (trap 250 catch)
|
| 1528 |
|
|
rsp d=001400 -- ! sp=1374
|
| 1529 |
|
|
wal 020002 -- check target area
|
| 1530 |
|
|
rm d=000016 -- ! mem(20002)=16
|
| 1531 |
|
|
wm 000000 -- clean tainted memory
|
| 1532 |
|
|
wal 177572 -- check SSR0
|
| 1533 |
|
|
brm 3
|
| 1534 |
|
|
d=011003 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=1,ena=1)
|
| 1535 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
| 1536 |
|
|
d=004714 -- ! SSR2: 4714 (eff. PC)
|
| 1537 |
|
|
#
|
| 1538 |
|
|
# mmu back to default setup, disable
|
| 1539 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1540 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
| 1541 |
|
|
wal 177572 -- SSR0
|
| 1542 |
|
|
wmi 000000 -- disable
|
| 1543 |
|
|
#----------
|
| 1544 |
|
|
#
|
| 1545 |
|
|
# now test stack limit logic
|
| 1546 |
|
|
#
|
| 1547 |
|
|
C Exec test 20.12 (red stack abort when pushing data to stack)
|
| 1548 |
|
|
wr0 123456 -- r0=123456
|
| 1549 |
|
|
wsp 000340 -- sp=340
|
| 1550 |
|
|
wpc 004722 -- pc=4722
|
| 1551 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
| 1552 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1553 |
|
|
rsp d=000000 -- ! sp=0
|
| 1554 |
|
|
wal 000336 -- check that stack wasn't written
|
| 1555 |
|
|
rm d=000000 -- ! mem(336) untainted
|
| 1556 |
|
|
wal 000000 -- check emergency stack at 0,2
|
| 1557 |
|
|
brm 2
|
| 1558 |
|
|
d=004724 -- ! mem(0): PC
|
| 1559 |
|
|
d=000010 -- ! mem(2): PS
|
| 1560 |
|
|
wal 177766 -- check CPUERR
|
| 1561 |
|
|
rm d=000004 -- ! CPUERR: (rsv=1)
|
| 1562 |
|
|
wm 000000 -- clear CPUERR
|
| 1563 |
|
|
#----------
|
| 1564 |
|
|
C Exec test 20.13 (red stack abort on 2nd word of interrupt/trap push)
|
| 1565 |
34 |
wfjm |
#wps 000017 -- psw: set all cc flags
|
| 1566 |
|
|
#wsp 000342 -- sp=342
|
| 1567 |
|
|
#wpc 004724 -- pc=4724
|
| 1568 |
|
|
#step -- step (iot): abort to 4 [[s:2]]
|
| 1569 |
|
|
#rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1570 |
|
|
#rsp d=000000 -- ! sp=0
|
| 1571 |
|
|
#wal 000336 -- check stack
|
| 1572 |
|
|
#brm 2
|
| 1573 |
|
|
# d=000000 -- ! mem(336) untainted
|
| 1574 |
|
|
# d=000017 -- ! mem(340) PS of 1st attempt
|
| 1575 |
|
|
#wal 000000 -- check emergency stack at 0,2
|
| 1576 |
|
|
#brm 2
|
| 1577 |
|
|
# d=004726 -- ! mem(0): PC
|
| 1578 |
|
|
# d=000000 -- ! mem(2): PS (will be 0, orgininal PS lost !!)
|
| 1579 |
|
|
#wal 177766 -- check CPUERR
|
| 1580 |
|
|
#rm d=000004 -- ! CPUERR: (rsv=1)
|
| 1581 |
|
|
#wm 000000 -- clear CPUERR
|
| 1582 |
2 |
wfjm |
#----------
|
| 1583 |
|
|
C Exec test 20.14 (yellow stack trap when pushing data to stack; sp=400)
|
| 1584 |
|
|
wps 000017 -- psw: set all cc flags
|
| 1585 |
|
|
wr0 123456 -- r0=123456
|
| 1586 |
|
|
wsp 000400 -- sp=400
|
| 1587 |
|
|
wpc 004722 -- pc=4722
|
| 1588 |
|
|
step -- step (mov r0,-(sp)): trap to 4
|
| 1589 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1590 |
|
|
rsp d=000372 -- ! sp=372
|
| 1591 |
|
|
wal 000372 -- check stack
|
| 1592 |
|
|
brm 3
|
| 1593 |
|
|
d=004724 -- ! mem(372) PC of trapped instruction
|
| 1594 |
|
|
d=000011 -- ! mem(374) PS of trapped instruction
|
| 1595 |
|
|
d=123456 -- ! mem(376) pushed word
|
| 1596 |
|
|
wal 177766 -- check CPUERR
|
| 1597 |
|
|
rm d=000010 -- ! CPUERR: (ysv=1)
|
| 1598 |
|
|
wm 000000 -- clear CPUERR
|
| 1599 |
|
|
#----------
|
| 1600 |
|
|
C Exec test 20.15 (yellow stack trap on 2nd word of interrupt/trap push; sp=402)
|
| 1601 |
|
|
wps 000017 -- psw: set all cc flags
|
| 1602 |
|
|
wsp 000402 -- sp=402
|
| 1603 |
|
|
wpc 004724 -- pc=4724
|
| 1604 |
|
|
step -- step (iot): abort to 4 [[s:2]]
|
| 1605 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1606 |
|
|
rsp d=000372 -- ! sp=372
|
| 1607 |
|
|
wal 000372 -- check stack
|
| 1608 |
|
|
brm 4
|
| 1609 |
|
|
d=000022 -- ! mem(372) PC of IOT handler
|
| 1610 |
|
|
d=000000 -- ! mem(374) PS of IOT handler
|
| 1611 |
|
|
d=004726 -- ! mem(376) PC of IOT trap
|
| 1612 |
|
|
d=000017 -- ! mem(400) PS of IOT trap
|
| 1613 |
|
|
wal 177766 -- check CPUERR
|
| 1614 |
|
|
rm d=000010 -- ! CPUERR: (ysv=1)
|
| 1615 |
|
|
wm 000000 -- clear CPUERR
|
| 1616 |
|
|
#----------
|
| 1617 |
|
|
# now test red stack escalation
|
| 1618 |
|
|
#
|
| 1619 |
|
|
C Exec test 20.16 (red stack escalation: abort kernel stack odd; sp=1001)
|
| 1620 |
|
|
wr0 123456 -- r0=123456
|
| 1621 |
|
|
wsp 001001 -- sp=1001
|
| 1622 |
|
|
wpc 004722 -- pc=4722
|
| 1623 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
| 1624 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1625 |
|
|
rsp d=000000 -- ! sp=0
|
| 1626 |
|
|
wal 000000 -- check emergency stack at 0,2
|
| 1627 |
|
|
brm 2
|
| 1628 |
|
|
d=004724 -- ! mem(0): PC
|
| 1629 |
|
|
d=000010 -- ! mem(2): PS
|
| 1630 |
|
|
wal 177766 -- check CPUERR
|
| 1631 |
|
|
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
|
| 1632 |
|
|
wm 000000 -- clear CPUERR
|
| 1633 |
|
|
#----------
|
| 1634 |
|
|
C Exec test 20.17 (red stack escalation: abort kernel stack in non-mem)
|
| 1635 |
|
|
wal 172354 -- kernel I space AR(6)
|
| 1636 |
|
|
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
|
| 1637 |
|
|
wal 177572 -- SSR0
|
| 1638 |
|
|
wmi 000001 -- enable
|
| 1639 |
|
|
wal 172516 -- SSR3
|
| 1640 |
|
|
wmi 000020 -- ena_22bit=1
|
| 1641 |
|
|
#
|
| 1642 |
|
|
wr0 123456 -- r0=123456
|
| 1643 |
|
|
wsp 140004 -- sp=140004
|
| 1644 |
|
|
wpc 004722 -- pc=4722
|
| 1645 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
| 1646 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1647 |
|
|
rsp d=000000 -- ! sp=0
|
| 1648 |
|
|
wal 000000 -- check emergency stack at 0,2
|
| 1649 |
|
|
brm 2
|
| 1650 |
|
|
d=004724 -- ! mem(0): PC
|
| 1651 |
|
|
d=000010 -- ! mem(2): PS
|
| 1652 |
|
|
wal 177766 -- check CPUERR
|
| 1653 |
|
|
rm d=000044 -- ! CPUERR: (rsv=1,nxm=1)
|
| 1654 |
|
|
wm 000000 -- clear CPUERR
|
| 1655 |
|
|
#
|
| 1656 |
|
|
wal 177572 -- SSR0
|
| 1657 |
|
|
wmi 000000 -- disable
|
| 1658 |
|
|
wal 172354 -- kernel I space AR(6)
|
| 1659 |
|
|
wm 001400 -- 1400 140000 base (default 1-to-1 map)
|
| 1660 |
|
|
#----------
|
| 1661 |
|
|
C Exec test 20.18 (red stack escalation: abort kernel stack iob-to;sp=160004)
|
| 1662 |
|
|
wr0 123456 -- r0=123456
|
| 1663 |
|
|
wsp 160004 -- sp=160004
|
| 1664 |
|
|
wpc 004722 -- pc=4722
|
| 1665 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
| 1666 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1667 |
|
|
rsp d=000000 -- ! sp=0
|
| 1668 |
|
|
wal 000000 -- check emergency stack at 0,2
|
| 1669 |
|
|
brm 2
|
| 1670 |
|
|
d=004724 -- ! mem(0): PC
|
| 1671 |
|
|
d=000010 -- ! mem(2): PS
|
| 1672 |
|
|
wal 177766 -- check CPUERR
|
| 1673 |
|
|
rm d=000024 -- ! CPUERR: (rsv=1,iobto=1)
|
| 1674 |
|
|
wm 000000 -- clear CPUERR
|
| 1675 |
|
|
#----------
|
| 1676 |
|
|
C Exec test 20.19 (red stack escalation: abort kernel stack mmu abort;sp=020004)
|
| 1677 |
|
|
#
|
| 1678 |
|
|
wal 177572 -- SSR0
|
| 1679 |
|
|
wmi 000001 -- enable
|
| 1680 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1681 |
|
|
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
|
| 1682 |
|
|
#
|
| 1683 |
|
|
wr0 123456 -- r0=123456
|
| 1684 |
|
|
wsp 020004 -- sp=020004
|
| 1685 |
|
|
wpc 004722 -- pc=4722
|
| 1686 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
| 1687 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
| 1688 |
|
|
rsp d=000000 -- ! sp=0
|
| 1689 |
|
|
wal 020002 -- check that stack wasn't written
|
| 1690 |
|
|
rm d=000000 -- ! mem(20002) untainted
|
| 1691 |
|
|
wal 000000 -- check emergency stack at 0,2
|
| 1692 |
|
|
brm 2
|
| 1693 |
|
|
d=004724 -- ! mem(0): PC
|
| 1694 |
|
|
d=000010 -- ! mem(2): PS
|
| 1695 |
|
|
wal 177766 -- check CPUERR
|
| 1696 |
|
|
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
|
| 1697 |
|
|
wm 000000 -- clear CPUERR
|
| 1698 |
|
|
# mmu back to default setup
|
| 1699 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
| 1700 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
| 1701 |
|
|
wal 177572 -- SSR0
|
| 1702 |
|
|
wmi 000000 -- disable
|
| 1703 |
|
|
wal 172516 -- SSR3
|
| 1704 |
|
|
wmi 000000 -- disable
|
| 1705 |
|
|
#
|
| 1706 |
|
|
#[[on]]
|
| 1707 |
|
|
#-----------------------------------------------------------------------------
|
| 1708 |
|
|
C Setup code 21 [base 4740] (MTPx/MFPx; MMU for user mode with I/D)
|
| 1709 |
|
|
#
|
| 1710 |
|
|
#use setting as for test 22
|
| 1711 |
|
|
wal 177600 -- user I space DR
|
| 1712 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 1713 |
|
|
wal 177620 -- user D space DR
|
| 1714 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 1715 |
|
|
wal 177640 -- user I space AR
|
| 1716 |
|
|
wmi 000053 -- 53 -> maps 0 -> 5300
|
| 1717 |
|
|
wal 177660 -- user D space AR
|
| 1718 |
|
|
wmi 000055 -- 55 -> maps 0 -> 5500
|
| 1719 |
|
|
wal 177572 -- SSR0
|
| 1720 |
|
|
wmi 000001 -- set enable bit
|
| 1721 |
|
|
wal 172516 -- SSR3
|
| 1722 |
|
|
wmi 000001 -- enable D space for user mode
|
| 1723 |
|
|
#
|
| 1724 |
|
|
wal 004740 -- code (to be single stepped...)
|
| 1725 |
|
|
bwm 6
|
| 1726 |
|
|
006610 -- mtpi (r0)
|
| 1727 |
|
|
106610 -- mtpd (r0)
|
| 1728 |
|
|
006606 -- mtpi r6
|
| 1729 |
|
|
006510 -- mfpi (r0)
|
| 1730 |
|
|
106510 -- mfpd (r0)
|
| 1731 |
|
|
006506 -- mfpi r6
|
| 1732 |
|
|
#
|
| 1733 |
|
|
C Exec code 21 (MTPx/MFPx; MMU for user mode with I/D)
|
| 1734 |
|
|
#
|
| 1735 |
|
|
wps 030000 -- psw: cmode=0, pmode=11
|
| 1736 |
|
|
wal 001372 -- setup kernel stack
|
| 1737 |
|
|
bwm 3
|
| 1738 |
|
|
012300 --
|
| 1739 |
|
|
001230 --
|
| 1740 |
|
|
000666 --
|
| 1741 |
|
|
wr0 000002 -- r0=2
|
| 1742 |
|
|
wsp 001372 -- sp=1372
|
| 1743 |
|
|
#
|
| 1744 |
|
|
wpc 004740 -- pc=4740
|
| 1745 |
|
|
step -- step (mtpi (r0))
|
| 1746 |
|
|
rpc d=004742 -- ! pc=next
|
| 1747 |
|
|
rsp d=001374 -- ! sp=1374 (one popped)
|
| 1748 |
|
|
wal 005302 -- user I base
|
| 1749 |
|
|
rm d=012300 -- ! mem_ui(2) = 012300
|
| 1750 |
|
|
#
|
| 1751 |
|
|
step -- step (mtpd (r0))
|
| 1752 |
|
|
rpc d=004744 -- ! pc=next
|
| 1753 |
|
|
rsp d=001376 -- ! sp=1376 (one popped)
|
| 1754 |
|
|
wal 005502 -- user D base
|
| 1755 |
|
|
rm d=001230 -- ! mem_ud(2) = 001230
|
| 1756 |
|
|
#
|
| 1757 |
|
|
step -- step (mtpi r6)
|
| 1758 |
|
|
rpc d=004746 -- ! pc=next
|
| 1759 |
|
|
rsp d=001400 -- ! sp=1400 (one popped)
|
| 1760 |
|
|
wps 170000 -- psw: cmode=11, pmode=11
|
| 1761 |
|
|
rsp d=000666 -- ! sp_um=666 [[usp]]
|
| 1762 |
|
|
wps 030000 -- psw: cmode=0, pmode=11
|
| 1763 |
|
|
#
|
| 1764 |
|
|
wal 001374 -- clear stack
|
| 1765 |
|
|
bwm 3
|
| 1766 |
|
|
000000 --
|
| 1767 |
|
|
000000 --
|
| 1768 |
|
|
000000 --
|
| 1769 |
|
|
#
|
| 1770 |
|
|
step -- step (mfpi (r0))
|
| 1771 |
|
|
rpc d=004750 -- ! pc=next
|
| 1772 |
|
|
rsp d=001376 -- ! sp=1376 (one pushed)
|
| 1773 |
|
|
wal 001376 -- top of stack
|
| 1774 |
|
|
rm d=012300 -- !
|
| 1775 |
|
|
#
|
| 1776 |
|
|
step -- step (mfpd (r0))
|
| 1777 |
|
|
rpc d=004752 -- ! pc=next
|
| 1778 |
|
|
rsp d=001374 -- ! sp=1374 (one pushed)
|
| 1779 |
|
|
wal 001374 -- top of stack
|
| 1780 |
|
|
rm d=001230 -- !
|
| 1781 |
|
|
#
|
| 1782 |
|
|
step -- step (mtpi r6)
|
| 1783 |
|
|
rpc d=004754 -- ! pc=next
|
| 1784 |
|
|
rsp d=001372 -- ! sp=1372 (one pushed)
|
| 1785 |
|
|
wal 001372 -- top of stack
|
| 1786 |
|
|
rm d=000666 -- !
|
| 1787 |
|
|
#
|
| 1788 |
|
|
wal 005302 -- clean tainted memory
|
| 1789 |
|
|
wm 000000 --
|
| 1790 |
|
|
wal 005502 --
|
| 1791 |
|
|
wm 000000 --
|
| 1792 |
|
|
#
|
| 1793 |
|
|
wps 000000 -- psw: cmode=pmode=0 (kernel)
|
| 1794 |
|
|
#-----------------------------------------------------------------------------
|
| 1795 |
|
|
C Setup code 22 [base 5000, use 50-57] (MMU ; run user mode code with I/D)
|
| 1796 |
|
|
#
|
| 1797 |
|
|
wal 177600 -- user I space DR
|
| 1798 |
|
|
wmi 000002 -- slf=0; ed=0(up); acf=2(read-only)
|
| 1799 |
|
|
wal 177620 -- user D space DR
|
| 1800 |
|
|
wmi 000006 -- slf=0; ed=0(up); acf=6(w/r)
|
| 1801 |
|
|
wal 177640 -- user I space AR
|
| 1802 |
|
|
wmi 000053 -- 53 -> maps 0 -> 5300
|
| 1803 |
|
|
wal 177660 -- user D space AR
|
| 1804 |
|
|
wmi 000055 -- 55 -> maps 0 -> 5500
|
| 1805 |
|
|
wal 177572 -- SSR0
|
| 1806 |
|
|
wmi 000001 -- set enable bit
|
| 1807 |
|
|
wal 172516 -- SSR3
|
| 1808 |
|
|
wmi 000001 -- enable D space for user mode
|
| 1809 |
|
|
#
|
| 1810 |
|
|
wal 005000 -- code (kernel):
|
| 1811 |
|
|
bwm 5
|
| 1812 |
|
|
012746 -- mov #144000,-(sp) ;PS for RTI
|
| 1813 |
|
|
174000 -- cmode=11,pmode=11,rset=1
|
| 1814 |
|
|
012746 -- mov #0,-(sp) ;PC for RTI
|
| 1815 |
|
|
000000 --
|
| 1816 |
|
|
000002 -- rti
|
| 1817 |
|
|
#-----
|
| 1818 |
|
|
wal 000034 -- vector: 34 (TRAP)
|
| 1819 |
|
|
bwm 2
|
| 1820 |
|
|
005020 -- PC:5020
|
| 1821 |
|
|
000340 -- PS: pri=7
|
| 1822 |
|
|
#-----
|
| 1823 |
|
|
wal 005020 -- code (kernel, trap 34):
|
| 1824 |
|
|
bwm 4
|
| 1825 |
|
|
011600 -- mov (sp),r0
|
| 1826 |
|
|
006560 -- mfpi -2(r0)
|
| 1827 |
|
|
177776
|
| 1828 |
|
|
000000 -- halt
|
| 1829 |
|
|
#-----
|
| 1830 |
|
|
wal 000250 -- vector: 250 (MMU)
|
| 1831 |
|
|
bwm 2
|
| 1832 |
|
|
005040 -- PC:5040
|
| 1833 |
|
|
000340 -- PS: pri=7
|
| 1834 |
|
|
#-----
|
| 1835 |
|
|
wal 005040 -- code (kernel, trap 4):
|
| 1836 |
|
|
bwm 68
|
| 1837 |
|
|
005337 -- dec @#5256
|
| 1838 |
|
|
005256
|
| 1839 |
|
|
001001 -- bne .+2
|
| 1840 |
|
|
000000 -- halt
|
| 1841 |
|
|
013700 -- mov ssr0,r0
|
| 1842 |
|
|
177572
|
| 1843 |
|
|
042700 -- bic #177741,r0 ; clear all but id+asn fields
|
| 1844 |
|
|
177741
|
| 1845 |
|
|
#5060
|
| 1846 |
|
|
062700 -- add #177600,r0 ; user DR address base
|
| 1847 |
|
|
177600
|
| 1848 |
|
|
# 5 23 062710 0 -- add #400,(r0)
|
| 1849 |
|
|
# 5 23 000400 0
|
| 1850 |
|
|
105260 -- incb 1(r0) ; odd address IB access fails !!
|
| 1851 |
|
|
000001
|
| 1852 |
|
|
010025 -- mov r0,(r5)+
|
| 1853 |
|
|
012025 -- mov (r0),(r5)+
|
| 1854 |
|
|
013700 -- mov ssr1,r0
|
| 1855 |
|
|
177574
|
| 1856 |
|
|
#5100
|
| 1857 |
|
|
010025 -- mov r0,(r5)+
|
| 1858 |
|
|
012701 -- mov #2,r1
|
| 1859 |
|
|
000002
|
| 1860 |
|
|
052737 -- bis #004000,psw
|
| 1861 |
|
|
004000
|
| 1862 |
|
|
177776
|
| 1863 |
|
|
005046 -- clr -(sp)
|
| 1864 |
|
|
106506 -- mfpd sp
|
| 1865 |
|
|
#5120
|
| 1866 |
|
|
010546 -- mov r5,-(sp)
|
| 1867 |
|
|
010446 -- mov r4,-(sp)
|
| 1868 |
|
|
010346 -- mov r3,-(sp)
|
| 1869 |
|
|
010246 -- mov r2,-(sp)
|
| 1870 |
|
|
010146 -- mov r1,-(sp)
|
| 1871 |
|
|
010046 -- mov r0,-(sp)
|
| 1872 |
|
|
042737 -- bic #004000,psw
|
| 1873 |
|
|
004000
|
| 1874 |
|
|
#5140
|
| 1875 |
|
|
177776
|
| 1876 |
|
|
010002 -- L1: mov r0,r2
|
| 1877 |
|
|
110003 -- movb r0,r3
|
| 1878 |
|
|
042702 -- bic #177770,r2 ; mask regnum field
|
| 1879 |
|
|
177770
|
| 1880 |
|
|
006302 -- asl r2
|
| 1881 |
|
|
060602 -- add sp,r2 ; address of reg on stack
|
| 1882 |
|
|
006203 -- asr r3 ; shift delta field down 3 bit
|
| 1883 |
|
|
#5160
|
| 1884 |
|
|
006203 -- asr r3
|
| 1885 |
|
|
006203 -- asr r3
|
| 1886 |
|
|
160312 -- sub r3,(r2) ; correct register contents
|
| 1887 |
|
|
000300 -- swap r0
|
| 1888 |
|
|
077114 -- sob r1,L1 (.-12)
|
| 1889 |
|
|
052737 -- bis #004000,psw
|
| 1890 |
|
|
004000
|
| 1891 |
|
|
177776
|
| 1892 |
|
|
#5200
|
| 1893 |
|
|
012600 -- mov (sp)+,r0
|
| 1894 |
|
|
012601 -- mov (sp)+,r1
|
| 1895 |
|
|
012602 -- mov (sp)+,r2
|
| 1896 |
|
|
012603 -- mov (sp)+,r3
|
| 1897 |
|
|
012604 -- mov (sp)+,r4
|
| 1898 |
|
|
012605 -- mov (sp)+,r5
|
| 1899 |
|
|
106606 -- mtpd sp
|
| 1900 |
|
|
005726 -- tst (sp)+
|
| 1901 |
|
|
#5220
|
| 1902 |
|
|
042737 -- bic #004000,psw
|
| 1903 |
|
|
004000
|
| 1904 |
|
|
177776
|
| 1905 |
|
|
013700 -- mov ssr2,r0
|
| 1906 |
|
|
177576
|
| 1907 |
|
|
010025 -- mov r0,(r5)+
|
| 1908 |
|
|
010016 -- mov r0,(sp)
|
| 1909 |
|
|
042737 -- bic #160000,ssr0 ; clear abort bits
|
| 1910 |
|
|
#5240
|
| 1911 |
|
|
160000
|
| 1912 |
|
|
177572
|
| 1913 |
|
|
000002 -- rti
|
| 1914 |
|
|
000000 -- halt
|
| 1915 |
|
|
#-----
|
| 1916 |
|
|
wal 005256 -- data (kernel):
|
| 1917 |
|
|
wmi 000003 -- stop at 3rd call of MMU handler
|
| 1918 |
|
|
#-----
|
| 1919 |
|
|
wal 005300 -- code (user):
|
| 1920 |
|
|
bwm 8
|
| 1921 |
|
|
012706 -- mov #100,sp
|
| 1922 |
|
|
000100
|
| 1923 |
|
|
005000 -- clr r0
|
| 1924 |
|
|
012701 -- mov #074,r1
|
| 1925 |
|
|
000074
|
| 1926 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 74
|
| 1927 |
|
|
000137 -- jmp @#74
|
| 1928 |
|
|
000074
|
| 1929 |
|
|
#
|
| 1930 |
|
|
wal 005374 -- .=5374
|
| 1931 |
|
|
bwm 4
|
| 1932 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 76
|
| 1933 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 100
|
| 1934 |
|
|
#5400
|
| 1935 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 102
|
| 1936 |
|
|
104417 -- trap 17
|
| 1937 |
|
|
#
|
| 1938 |
|
|
wal 005500 -- data (user):
|
| 1939 |
|
|
bwm 4
|
| 1940 |
|
|
002001 -- mem_ud(0)=02001
|
| 1941 |
|
|
002002 -- mem_ud(2)=02002
|
| 1942 |
|
|
002003 -- mem_ud(4)=02003
|
| 1943 |
|
|
002004 -- mem_ud(6)=02004
|
| 1944 |
|
|
wal 005574 -- data (user):
|
| 1945 |
|
|
bwm 4
|
| 1946 |
|
|
000300 -- mem_ud(074)=0300
|
| 1947 |
|
|
000300 -- mem_ud(076)=0300
|
| 1948 |
|
|
000300 -- mem_ud(100)=0300
|
| 1949 |
|
|
000300 -- mem_ud(102)=0300
|
| 1950 |
|
|
#
|
| 1951 |
|
|
C Exec code 22 (MMU ; run user mode code with I/D)
|
| 1952 |
|
|
wr5 005260 -- r5=5260
|
| 1953 |
|
|
wsp 001400 -- sp=1400
|
| 1954 |
|
|
wpc 005000 -- pc=5000
|
| 1955 |
30 |
wfjm |
sta -- start @ 5000
|
| 1956 |
2 |
wfjm |
wtgo
|
| 1957 |
|
|
rsp d=001372 -- ! sp
|
| 1958 |
|
|
rpc d=005030 -- ! pc (halt in TRAP handler)
|
| 1959 |
|
|
wal 001372 -- check stack (1372)
|
| 1960 |
|
|
brm 3
|
| 1961 |
|
|
d=104417 -- ! TRAP instruction
|
| 1962 |
|
|
d=000104 -- ! PC trap
|
| 1963 |
|
|
d=174000 -- ! PS trap
|
| 1964 |
|
|
#
|
| 1965 |
|
|
wal 005256 --
|
| 1966 |
|
|
brm 9
|
| 1967 |
|
|
d=000001 -- ! mem(5256) (mmu 3 - trap count)
|
| 1968 |
|
|
d=177620 -- ! mem(5260) (1st trap: address fixed DR)
|
| 1969 |
|
|
d=000406 -- ! mem(5262) (1st trap: new content of DR)
|
| 1970 |
|
|
d=010420 -- ! mem(5264) (1st trap: ssr1: ra=0,2;rb=1,2)
|
| 1971 |
|
|
d=000076 -- ! mem(5266) (1st trap: ssr2: pc)
|
| 1972 |
|
|
d=177600 -- ! mem(5270) (2nd trap: address fixed DR)
|
| 1973 |
|
|
d=000402 -- ! mem(5272) (2nd trap: new content of DR)
|
| 1974 |
|
|
d=000000 -- ! mem(5274) (2nd trap: ssr1: none)
|
| 1975 |
|
|
d=000100 -- ! mem(5276) (2nd trap: ssr2: pc)
|
| 1976 |
|
|
#
|
| 1977 |
|
|
wal 005574
|
| 1978 |
|
|
brm 4
|
| 1979 |
|
|
d=002301 -- ! mem(5574)=02301 was mem_ud(074)
|
| 1980 |
|
|
d=002302 -- ! mem(5576)=02302 was mem_ud(076)
|
| 1981 |
|
|
d=002303 -- ! mem(5600)=02303 was mem_ud(100)
|
| 1982 |
|
|
d=002304 -- ! mem(5602)=02304 was mem_ud(102)
|
| 1983 |
|
|
#
|
| 1984 |
|
|
wal 000034 -- vector: 34 -> trap catcher again
|
| 1985 |
|
|
bwm 2
|
| 1986 |
|
|
000036 -- PC:36
|
| 1987 |
|
|
000000 -- PS:0
|
| 1988 |
|
|
wal 000250 -- vector: 250 -> trap catcher again
|
| 1989 |
|
|
bwm 2
|
| 1990 |
|
|
000252 -- PC:252
|
| 1991 |
|
|
000000 -- PS:0
|
| 1992 |
|
|
#
|
| 1993 |
|
|
wps 000000 -- psw: cmode=pmode=0 (kernel)
|
| 1994 |
|
|
#-----------------------------------------------------------------------------
|
| 1995 |
|
|
C Setup code 23 [base 5700; use 57-63] (test cmp and conditional branch)
|
| 1996 |
|
|
#
|
| 1997 |
|
|
wal 005700 -- code test 1:
|
| 1998 |
|
|
bwm 5
|
| 1999 |
|
|
012012 -- mov (r0)+,(r2) ; load PSW from table
|
| 2000 |
|
|
004737 -- jsr pc,@#6000
|
| 2001 |
|
|
006000
|
| 2002 |
|
|
077104 -- sob r1,-4
|
| 2003 |
|
|
000000 -- halt
|
| 2004 |
|
|
#
|
| 2005 |
|
|
wal 005720 -- code test 2:
|
| 2006 |
|
|
bwm 6
|
| 2007 |
|
|
000230 -- spl 0
|
| 2008 |
|
|
005720 -- tst (r0)+ ; verify tst response
|
| 2009 |
|
|
004737 -- jsr pc,@#6000
|
| 2010 |
|
|
006000
|
| 2011 |
|
|
077104 -- sob r1,-4
|
| 2012 |
|
|
000000 -- halt
|
| 2013 |
|
|
#
|
| 2014 |
|
|
wal 005740 -- code test 3:
|
| 2015 |
|
|
bwm 6
|
| 2016 |
|
|
000230 -- spl 0
|
| 2017 |
|
|
022020 -- cmp (r0+),(r0)+ ; verify cmp response
|
| 2018 |
|
|
004737 -- jsr pc,@#6000
|
| 2019 |
|
|
006000
|
| 2020 |
|
|
077104 -- sob r1,-4
|
| 2021 |
|
|
000000 -- halt
|
| 2022 |
|
|
#
|
| 2023 |
|
|
# test 1 test 2 test 3
|
| 2024 |
|
|
# - C V Z N < = > < = >
|
| 2025 |
|
|
# code branch condition mask 1 2 3 4 5 1 2 3 1 2 3 4 5 6 7
|
| 2026 |
|
|
# BNE if Z = 0 000004 y y y y y y y y y y y y
|
| 2027 |
|
|
# BEQ if Z = 1 000010 y y y
|
| 2028 |
|
|
# BGE if (N xor V) = 0 000020 y y y y y y y y y
|
| 2029 |
|
|
# BLT if (N xor V) = 1 000040 y y y y y y
|
| 2030 |
|
|
# BGT if (Z or (N xor V)) = 0 000100 y y y y y y
|
| 2031 |
|
|
# BLE if (Z or (N xor V)) = 1 000200 y y y y y y y y y
|
| 2032 |
|
|
# BPL if N = 0 000400 y y y y y y y y y y
|
| 2033 |
|
|
# BMI if N = 1 001000 y y y y y
|
| 2034 |
|
|
# BHI if (C or Z) = 0 002000 y y y y y y y y
|
| 2035 |
|
|
# BLOS if (C or Z) = 1 004000 y y y y y y y
|
| 2036 |
|
|
# BVC if V = 0 010000 y y y y y y y y y y y y
|
| 2037 |
|
|
# BVS if V = 1 020000 y y y
|
| 2038 |
|
|
# BCC if C = 0 (aka BHIS) 040000 y y y y y y y y y y y
|
| 2039 |
|
|
# BCS if C = 1 (aka BLO) 100000 y y y y
|
| 2040 |
|
|
#
|
| 2041 |
|
|
wal 006000 -- code check:
|
| 2042 |
|
|
bwm 63
|
| 2043 |
|
|
011203 -- mov (r2),r3 ; save PSW
|
| 2044 |
|
|
012704 -- mov #177774,r4 ; set pattern store
|
| 2045 |
|
|
177774 --
|
| 2046 |
|
|
010312 -- mov r3,(r2) ; restore PSW
|
| 2047 |
|
|
001003 -- bne .+3
|
| 2048 |
|
|
042704 -- bic #000004,r4
|
| 2049 |
|
|
000004 --
|
| 2050 |
|
|
010312 -- mov r3,(r2)
|
| 2051 |
|
|
#6020
|
| 2052 |
|
|
001403 -- beq .+3
|
| 2053 |
|
|
042704 -- bic #000010,r4
|
| 2054 |
|
|
000010 --
|
| 2055 |
|
|
010312 -- mov r3,(r2)
|
| 2056 |
|
|
002003 -- bge .+3
|
| 2057 |
|
|
042704 -- bic #000020,r4
|
| 2058 |
|
|
000020 --
|
| 2059 |
|
|
010312 -- mov r3,(r2)
|
| 2060 |
|
|
#6040
|
| 2061 |
|
|
002403 -- blt .+3
|
| 2062 |
|
|
042704 -- bic #000040,r4
|
| 2063 |
|
|
000040 --
|
| 2064 |
|
|
010312 -- mov r3,(r2)
|
| 2065 |
|
|
003003 -- bgt .+3
|
| 2066 |
|
|
042704 -- bic #000100,r4
|
| 2067 |
|
|
000100 --
|
| 2068 |
|
|
010312 -- mov r3,(r2)
|
| 2069 |
|
|
#6060
|
| 2070 |
|
|
003403 -- ble .+3
|
| 2071 |
|
|
042704 -- bic #000200,r4
|
| 2072 |
|
|
000200 --
|
| 2073 |
|
|
010312 -- mov r3,(r2)
|
| 2074 |
|
|
100003 -- bpl .+3
|
| 2075 |
|
|
042704 -- bic #000400,r4
|
| 2076 |
|
|
000400 --
|
| 2077 |
|
|
010312 -- mov r3,(r2)
|
| 2078 |
|
|
#6100
|
| 2079 |
|
|
100403 -- bmi .+3
|
| 2080 |
|
|
042704 -- bic #001000,r4
|
| 2081 |
|
|
001000 --
|
| 2082 |
|
|
010312 -- mov r3,(r2)
|
| 2083 |
|
|
101003 -- bhi .+3
|
| 2084 |
|
|
042704 -- bic #002000,r4
|
| 2085 |
|
|
002000 --
|
| 2086 |
|
|
010312 -- mov r3,(r2)
|
| 2087 |
|
|
#6120
|
| 2088 |
|
|
101403 -- blos .+3
|
| 2089 |
|
|
042704 -- bic #004000,r4
|
| 2090 |
|
|
004000 --
|
| 2091 |
|
|
010312 -- mov r3,(r2)
|
| 2092 |
|
|
102003 -- bvc .+3
|
| 2093 |
|
|
042704 -- bic #010000,r4
|
| 2094 |
|
|
010000 --
|
| 2095 |
|
|
010312 -- mov r3,(r2)
|
| 2096 |
|
|
#6140
|
| 2097 |
|
|
102403 -- bvs .+3
|
| 2098 |
|
|
042704 -- bic #020000,r4
|
| 2099 |
|
|
020000 --
|
| 2100 |
|
|
010312 -- mov r3,(r2)
|
| 2101 |
|
|
103003 -- bcc .+3
|
| 2102 |
|
|
042704 -- bic #040000,r4
|
| 2103 |
|
|
040000 --
|
| 2104 |
|
|
010312 -- mov r3,(r2)
|
| 2105 |
|
|
#6160
|
| 2106 |
|
|
103403 -- bcs .+3
|
| 2107 |
|
|
042704 -- bic #100000,r4
|
| 2108 |
|
|
100000 --
|
| 2109 |
|
|
010312 -- mov r3,(r2)
|
| 2110 |
|
|
010325 -- mov r3,(r5)+
|
| 2111 |
|
|
010425 -- mov r4,(r5)+
|
| 2112 |
|
|
000207 -- rts pc
|
| 2113 |
|
|
#
|
| 2114 |
|
|
wal 006200 -- data test 1:
|
| 2115 |
|
|
bwm 5
|
| 2116 |
|
|
000000 -- PSW - no cc
|
| 2117 |
|
|
000001 -- PSW - C=1
|
| 2118 |
|
|
000002 -- PSW - V=1
|
| 2119 |
|
|
000004 -- PSW - Z=1
|
| 2120 |
|
|
000010 -- PSW - N=1
|
| 2121 |
|
|
#
|
| 2122 |
|
|
wal 006220 -- data test 2:
|
| 2123 |
|
|
bwm 3
|
| 2124 |
|
|
177777 -- tst -1
|
| 2125 |
|
|
000000 -- tst 0
|
| 2126 |
|
|
000001 -- tst 1
|
| 2127 |
|
|
#
|
| 2128 |
|
|
wal 006230 -- data test 3:
|
| 2129 |
|
|
bwm 14
|
| 2130 |
|
|
000001 -- cmp 1,2
|
| 2131 |
|
|
000002
|
| 2132 |
|
|
000001 -- cmp 1,1
|
| 2133 |
|
|
000001
|
| 2134 |
|
|
#6240
|
| 2135 |
|
|
000002 -- cmp 2,1
|
| 2136 |
|
|
000001
|
| 2137 |
|
|
177777 -- cmp -1,2
|
| 2138 |
|
|
000002
|
| 2139 |
|
|
000002 -- cmp 2,-1
|
| 2140 |
|
|
177777
|
| 2141 |
|
|
100000 -- cmp 100000,077777
|
| 2142 |
|
|
077777
|
| 2143 |
|
|
#6260
|
| 2144 |
|
|
077777 -- cmp 077777,100000
|
| 2145 |
|
|
100000
|
| 2146 |
|
|
#
|
| 2147 |
|
|
C Exec code 23 (test cmp and conditional branch)
|
| 2148 |
|
|
C Exec test 23.1 (explict cc setting)
|
| 2149 |
|
|
#
|
| 2150 |
|
|
wr0 006200 -- r0=6200 (input data)
|
| 2151 |
|
|
wr1 000005 -- r1=5
|
| 2152 |
|
|
wr2 177776 -- r2=177776 (PS address)
|
| 2153 |
|
|
wr5 006300 -- r5=6300 (output data)
|
| 2154 |
|
|
wsp 001400 -- sp=1400
|
| 2155 |
30 |
wfjm |
cres
|
| 2156 |
2 |
wfjm |
stapc 005700 -- start @ 5700
|
| 2157 |
|
|
wtgo
|
| 2158 |
|
|
rr0 d=006212 -- ! r0
|
| 2159 |
|
|
rr1 d=000000 -- ! r1
|
| 2160 |
|
|
rr5 d=006324 -- ! r5
|
| 2161 |
|
|
rsp d=001400 -- ! sp
|
| 2162 |
|
|
rpc d=005712 -- ! pc
|
| 2163 |
|
|
wal 006300 -- use BCC/BCS naming below
|
| 2164 |
|
|
brm 10
|
| 2165 |
|
|
d=000000 -- ! mem(6300) 1 PS: none
|
| 2166 |
|
|
d=052524 -- ! mem(6302) 1 BNE,BGE,BGT,BPL,BHI,BVC,BCC
|
| 2167 |
|
|
d=000001 -- ! mem(6304) 2 PS: C=1
|
| 2168 |
|
|
d=114524 -- ! mem(6306) 2 BNE,BGE,BGT,BPL,BLOS,BVC,BCS
|
| 2169 |
|
|
d=000002 -- ! mem(6310) 3 PS: V=1
|
| 2170 |
|
|
d=062644 -- ! mem(6312) 3 BNE,BLT,BLE,BPL,BHI,BVS,BCC
|
| 2171 |
|
|
d=000004 -- ! mem(6314) 4 PS: Z=1
|
| 2172 |
|
|
d=054630 -- ! mem(6316) 4 BEQ,BGE,BLE,BPL,BLOS,BVC,BCC
|
| 2173 |
|
|
d=000010 -- ! mem(6320) 5 PS: N=1
|
| 2174 |
|
|
d=053244 -- ! mem(6322) 5 BNE,BLT,BLE,BMI,BHI,BVC,BCC
|
| 2175 |
|
|
#
|
| 2176 |
|
|
C Exec test 23.2 (tst testing)
|
| 2177 |
|
|
#
|
| 2178 |
|
|
wr0 006220 -- r0=6220 (input data)
|
| 2179 |
|
|
wr1 000003 -- r1=3
|
| 2180 |
|
|
wr2 177776 -- r2=177776 (PS address)
|
| 2181 |
|
|
wr5 006330 -- sp=6330 (output data)
|
| 2182 |
|
|
wsp 001400 -- sp=1400
|
| 2183 |
30 |
wfjm |
cres
|
| 2184 |
2 |
wfjm |
stapc 005720 -- start @ 5720
|
| 2185 |
|
|
wtgo
|
| 2186 |
|
|
rr0 d=006226 -- ! r0
|
| 2187 |
|
|
rr1 d=000000 -- ! r1
|
| 2188 |
|
|
rr5 d=006344 -- ! r5
|
| 2189 |
|
|
rsp d=001400 -- ! sp
|
| 2190 |
|
|
rpc d=005734 -- ! pc
|
| 2191 |
|
|
wal 006330 -- use BHIS(BCC)/BLO(BLO) naming below
|
| 2192 |
|
|
brm 6
|
| 2193 |
|
|
d=000010 -- ! mem(6330) 1 PS: tst -1: N=1
|
| 2194 |
|
|
d=053244 -- ! mem(6332) 1 BNE,BLT,BLE,BMI,BHI,BVC,BHIS
|
| 2195 |
|
|
d=000004 -- ! mem(6334) 2 PS: tst 0: Z=1
|
| 2196 |
|
|
d=054630 -- ! mem(6336) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
|
| 2197 |
|
|
d=000000 -- ! mem(6340) 3 PS: tst 1: all 0
|
| 2198 |
|
|
d=052524 -- ! mem(6342) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
|
| 2199 |
|
|
#
|
| 2200 |
|
|
C Exec test 23.3 (cmp testing)
|
| 2201 |
|
|
#
|
| 2202 |
|
|
wr0 006230 -- r0=6230 (input data)
|
| 2203 |
|
|
wr1 000007 -- r1=7
|
| 2204 |
|
|
wr2 177776 -- r2=177776 (PS address)
|
| 2205 |
|
|
wr5 006344 -- sp=6344 (output data)
|
| 2206 |
|
|
wsp 001400 -- sp=1400
|
| 2207 |
30 |
wfjm |
cres
|
| 2208 |
2 |
wfjm |
stapc 005740 -- start @ 5740
|
| 2209 |
|
|
wtgo
|
| 2210 |
|
|
rr0 d=006264 -- ! r0
|
| 2211 |
|
|
rr1 d=000000 -- ! r1
|
| 2212 |
|
|
rr5 d=006400 -- ! r5
|
| 2213 |
|
|
rsp d=001400 -- ! sp
|
| 2214 |
|
|
rpc d=005754 -- ! pc
|
| 2215 |
|
|
wal 006344 -- cmp= S-D !
|
| 2216 |
|
|
brm 14
|
| 2217 |
|
|
d=000011 -- ! mem(6344) 1 PS: cmp 1,2: N=1,C=1 ok
|
| 2218 |
|
|
d=115244 -- ! mem(6346) 1 BNE,BLT,BLE,BMI,BLOS,BVC,BLO
|
| 2219 |
|
|
d=000004 -- ! mem(6350) 2 PS: cmp 1,1: Z=1 ok
|
| 2220 |
|
|
d=054630 -- ! mem(6352) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
|
| 2221 |
|
|
d=000000 -- ! mem(6354) 3 PS: cmp 2,1: none ok
|
| 2222 |
|
|
d=052524 -- ! mem(6356) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
|
| 2223 |
|
|
d=000010 -- ! mem(6360) 4 PS: cmp -1,2: N=1
|
| 2224 |
|
|
d=053244 -- ! mem(6362) 4 BNE,BLT,BLE,BMI,BHI,BVC,BHIS ok
|
| 2225 |
|
|
d=000001 -- ! mem(6364) 5 PS: cmp 2,-1: C=1
|
| 2226 |
|
|
d=114524 -- ! mem(6366) 5 BNE,BGE,BGT,BPL,BLOS,BVC,BLO ok
|
| 2227 |
|
|
d=000002 -- ! mem(6370) 6 PS: cmp 10..,07..: V=1
|
| 2228 |
|
|
d=062644 -- ! mem(6372) 6 BNE,BLT,BLE,BPL,BHI,BVS,BHIS ok
|
| 2229 |
|
|
d=000013 -- ! mem(6374) 7 PS: cmp 07..,10..: N=1,V=1,C=1
|
| 2230 |
|
|
d=125124 -- ! mem(6376) 7 BNE,BGE,BGT,BMI,BLOS,BVS,BLO ok
|
| 2231 |
|
|
#
|
| 2232 |
|
|
#-----------------------------------------------------------------------------
|
| 2233 |
|
|
C Setup code 24 [base 6400] (test MARK instruction)
|
| 2234 |
|
|
#
|
| 2235 |
|
|
wal 006400 -- code (main):
|
| 2236 |
|
|
bwm 13
|
| 2237 |
|
|
010546 -- mov r5,-(sp) ; push old r5 on stack
|
| 2238 |
|
|
012746 -- mov #101,-(sp) ; push 1st parameter
|
| 2239 |
|
|
000101
|
| 2240 |
|
|
012746 -- mov #102,-(sp) ; push 2nd parameter
|
| 2241 |
|
|
000102
|
| 2242 |
|
|
012746 -- mov #103,-(sp) ; push 3rd parameter
|
| 2243 |
|
|
000103
|
| 2244 |
|
|
012746 -- mov #mark3,-(sp) ; push MARK 3
|
| 2245 |
|
|
#6420
|
| 2246 |
|
|
006403
|
| 2247 |
|
|
010605 -- mov sp,r5 ; address of MARK N
|
| 2248 |
|
|
004737 -- jsr pc,@#6440 ; call procedure
|
| 2249 |
|
|
006440
|
| 2250 |
|
|
000000 -- halt
|
| 2251 |
|
|
#
|
| 2252 |
|
|
# stack of procedure when called:
|
| 2253 |
|
|
# addr content
|
| 2254 |
|
|
# 576 12(sp) 10(r5) old r5
|
| 2255 |
|
|
# 574 10(sp) 6(r5) param1
|
| 2256 |
|
|
# 572 6(sp) 4(r5) param2
|
| 2257 |
|
|
# 570 4(sp) 2(r5) param3
|
| 2258 |
|
|
# 566 2(sp) (r5) mark 3
|
| 2259 |
|
|
# 564 (sp) return pc
|
| 2260 |
|
|
#
|
| 2261 |
|
|
wal 006440 -- code (procedure):
|
| 2262 |
|
|
bwm 7
|
| 2263 |
|
|
016520 -- mov 6(r5),(r0)+ ; get 1st param
|
| 2264 |
|
|
000006
|
| 2265 |
|
|
016520 -- mov 4(r5),(r0)+ ; get 2nd param
|
| 2266 |
|
|
000004
|
| 2267 |
|
|
016520 -- mov 2(r5),(r0)+ ; get 3rd param
|
| 2268 |
|
|
000002
|
| 2269 |
|
|
000205 -- rts r5
|
| 2270 |
|
|
#
|
| 2271 |
|
|
C Exec code 24 (test MARK instruction)
|
| 2272 |
|
|
#
|
| 2273 |
|
|
wr0 006470 -- r0=6470
|
| 2274 |
|
|
wr5 123456 -- r5=123456
|
| 2275 |
|
|
wsp 001400 -- sp=1400
|
| 2276 |
30 |
wfjm |
cres
|
| 2277 |
2 |
wfjm |
stapc 006400 -- start @ 6400
|
| 2278 |
|
|
wtgo
|
| 2279 |
|
|
rr0 d=006476 -- ! r0=6476 (3 words written)
|
| 2280 |
|
|
rr5 d=123456 -- ! r5 (restored)
|
| 2281 |
|
|
rsp d=001400 -- ! sp
|
| 2282 |
|
|
rpc d=006432 -- ! pc
|
| 2283 |
|
|
wal 001364 -- check stack
|
| 2284 |
|
|
brm 6
|
| 2285 |
|
|
d=006430 -- ! mem(1364)
|
| 2286 |
|
|
d=006403 -- ! mem(1366)
|
| 2287 |
|
|
d=000103 -- ! mem(1370)
|
| 2288 |
|
|
d=000102 -- ! mem(1372)
|
| 2289 |
|
|
d=000101 -- ! mem(1374)
|
| 2290 |
|
|
d=123456 -- ! mem(1376)
|
| 2291 |
|
|
wal 006470 -- check stored values
|
| 2292 |
|
|
brm 3
|
| 2293 |
|
|
d=000101 -- ! mem(6470) (1st param)
|
| 2294 |
|
|
d=000102 -- ! mem(6472) (2nd param)
|
| 2295 |
|
|
d=000103 -- ! mem(6474) (3rd param)
|
| 2296 |
|
|
#
|
| 2297 |
|
|
# probably first and last time MARK is used. It's a bastard anyway.
|
| 2298 |
|
|
#
|
| 2299 |
|
|
#-----------------------------------------------------------------------------
|
| 2300 |
|
|
C Setup code 25 [base 6500; use 65-66] (basic byte instruction and cc test)
|
| 2301 |
|
|
#
|
| 2302 |
|
|
wal 006500 -- code:
|
| 2303 |
|
|
bwm 22
|
| 2304 |
|
|
110124 -- movb r1,(r4)+ (#123, #333)
|
| 2305 |
|
|
120124 -- cmpb r1,(r4)+ (#123, #333)
|
| 2306 |
|
|
120224 -- cmpb r2,(r4)+ (#321, #111)
|
| 2307 |
|
|
120124 -- cmpb r1,(r4)+ (#123, #123)
|
| 2308 |
|
|
105024 -- clrb (r4)+ (#333)
|
| 2309 |
|
|
130124 -- bitb r1,(r4)+ (#123, #11)
|
| 2310 |
|
|
130124 -- bitb r1,(r4)+ (#123, #44)
|
| 2311 |
|
|
140124 -- bicb r1,(r4)+ (#123, #333)
|
| 2312 |
|
|
#6520
|
| 2313 |
|
|
150124 -- bisb r1,(r4)+ (#123, #111)
|
| 2314 |
|
|
105124 -- comb (r4)+ (#321)
|
| 2315 |
|
|
105224 -- incb (r4)+ (#321)
|
| 2316 |
|
|
105324 -- decb (r4)+ (#321)
|
| 2317 |
|
|
105424 -- negb (r4)+ (#321)
|
| 2318 |
|
|
105724 -- tstb (r4)+ (#321)
|
| 2319 |
|
|
106024 -- rorb (r4)+ (#201) Cin=0; Cout=1
|
| 2320 |
|
|
106024 -- rorb (r4)+ (#021) Cin=1; Cout=1
|
| 2321 |
|
|
#6540
|
| 2322 |
|
|
106124 -- rolb (r4)+ (#210) Cin=1; Cout=1
|
| 2323 |
|
|
106224 -- asrb (r4)+ (#020)
|
| 2324 |
|
|
106224 -- asrb (r4)+ (#220)
|
| 2325 |
|
|
106324 -- aslb (r4)+ (#020)
|
| 2326 |
|
|
106324 -- aslb (r4)+ (#220)
|
| 2327 |
|
|
000000 -- halt
|
| 2328 |
|
|
#
|
| 2329 |
|
|
wal 000014 -- vector: 14
|
| 2330 |
|
|
bwm 2
|
| 2331 |
|
|
006560 -- PC:6560
|
| 2332 |
|
|
000000 -- PS:0
|
| 2333 |
|
|
#
|
| 2334 |
|
|
wal 006560 -- code: (trap 14):
|
| 2335 |
|
|
bwm 3
|
| 2336 |
|
|
016625 -- mov 2(sp),(r5)+
|
| 2337 |
|
|
000002
|
| 2338 |
|
|
000006 -- rtt
|
| 2339 |
|
|
#
|
| 2340 |
|
|
wal 006600 -- data 1:
|
| 2341 |
|
|
bwm 11
|
| 2342 |
|
|
155733 -- (#333,#333)
|
| 2343 |
|
|
051511 -- (#123,#111)
|
| 2344 |
|
|
044333 -- (#11 ,#333)
|
| 2345 |
|
|
155444 -- (#333,#44)
|
| 2346 |
|
|
150511 -- (#321,#111)
|
| 2347 |
|
|
150721 -- (#321,#321)
|
| 2348 |
|
|
150721 -- (#321,#321)
|
| 2349 |
|
|
010601 -- (#021,#201)
|
| 2350 |
|
|
#6620
|
| 2351 |
|
|
010210 -- (#020,#210)
|
| 2352 |
|
|
010220 -- (#020,#220)
|
| 2353 |
|
|
000220 -- (....,#220)
|
| 2354 |
|
|
#
|
| 2355 |
|
|
C Exec code 25 (basic byte instruction and cc test)
|
| 2356 |
|
|
#
|
| 2357 |
|
|
wr1 000123 -- r1=123
|
| 2358 |
|
|
wr2 000321 -- r2=321
|
| 2359 |
|
|
wr4 006600 -- r4=6600
|
| 2360 |
|
|
wr5 006626 -- r5=6626
|
| 2361 |
|
|
wsp 001374 -- sp=1374
|
| 2362 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
| 2363 |
|
|
bwm 2
|
| 2364 |
|
|
006500 -- start address (code 25 @ 6500)
|
| 2365 |
|
|
000020 -- set T flag in PSW
|
| 2366 |
30 |
wfjm |
cres
|
| 2367 |
2 |
wfjm |
stapc 006564 -- start @ 6564 -> rtt -> 6500 from stack
|
| 2368 |
|
|
wtgo
|
| 2369 |
|
|
rr1 d=000123 -- ! r1=123
|
| 2370 |
|
|
rr2 d=000321 -- ! r2=321
|
| 2371 |
|
|
rr4 d=006625 -- ! r4=6625
|
| 2372 |
|
|
rr5 d=006700 -- ! r5=6700
|
| 2373 |
|
|
rsp d=001400 -- ! sp=1400
|
| 2374 |
|
|
rpc d=006554 -- ! pc=6554
|
| 2375 |
|
|
wal 006600
|
| 2376 |
|
|
brm 11
|
| 2377 |
|
|
d=155523 -- ! mem(6600)=123; movb r1,(r4)+ (#123, #333)
|
| 2378 |
|
|
# ! mem(6601)=333; cmpb r1,(r4)+ (#123, #333)
|
| 2379 |
|
|
d=051511 -- ! mem(6602)=111; cmpb r1,(r4)+ (#321, #111)
|
| 2380 |
|
|
# ! mem(6603)=123; cmpb r1,(r4)+ (#123, #123)
|
| 2381 |
|
|
d=044000 -- ! mem(6604)=000; clrb (r4)+ (#333)
|
| 2382 |
|
|
# ! mem(6605)=011; bitb r1,(r4)+ (#123, #11)
|
| 2383 |
|
|
d=104044 -- ! mem(6606)=044; bitb r1,(r4)+ (#123, #44)
|
| 2384 |
|
|
# ! mem(6607)=210; bicb r1,(r4)+ (#123, #333)
|
| 2385 |
|
|
d=027133 -- ! mem(6610)=133; bisb r1,(r4)+ (#123, #111)
|
| 2386 |
|
|
# ! mem(6611)=056; comb (r4)+ (#321)
|
| 2387 |
|
|
d=150322 -- ! mem(6612)=322; incb (r4)+ (#321)
|
| 2388 |
|
|
# ! mem(6613)=320; decb (r4)+ (#321)
|
| 2389 |
|
|
d=150457 -- ! mem(6614)=057; negb (r4)+ (#321)
|
| 2390 |
|
|
# ! mem(6615)=321; tstb (r4)+ (#321)
|
| 2391 |
|
|
d=104100 -- ! mem(6616)=100; rorb (r4)+ (#201) Cout=1
|
| 2392 |
|
|
# ! mem(6617)=210; rorb (r4)+ (#021) Cout=1
|
| 2393 |
|
|
d=004021 -- ! mem(6620)=021; rolb (r4)+ (#210) Cout=1
|
| 2394 |
|
|
# ! mem(6621)=010; asrb (r4)+ (#020)
|
| 2395 |
|
|
d=020310 -- ! mem(6622)=310; asrb (r4)+ (#220)
|
| 2396 |
|
|
# ! mem(6623)=040; aslb (r4)+ (#020)
|
| 2397 |
|
|
d=000040 -- ! mem(6624)=040; aslb (r4)+ (#220)
|
| 2398 |
|
|
#
|
| 2399 |
|
|
wal 006626 -- NZVC
|
| 2400 |
|
|
brm 21
|
| 2401 |
|
|
d=000020 -- ! mem(6626)=0000; movb r1,(r4)+ (#123, #333)
|
| 2402 |
|
|
d=000021 -- ! mem(6630)=000C; cmpb r1,(r4)+ (#123, #333)
|
| 2403 |
|
|
d=000030 -- ! mem(6632)=N000; cmpb r1,(r4)+ (#321, #111)
|
| 2404 |
|
|
d=000024 -- ! mem(6634)=0Z00; cmpb r1,(r4)+ (#123, #123)
|
| 2405 |
|
|
d=000024 -- ! mem(6636)=0Z00; clrb (r4)+ (#333)
|
| 2406 |
|
|
d=000020 -- ! mem(6640)=0000; bitb r1,(r4)+ (#123, #11)
|
| 2407 |
|
|
d=000024 -- ! mem(6642)=0Z00; bitb r1,(r4)+ (#123, #44)
|
| 2408 |
|
|
d=000030 -- ! mem(6644)=N000; bicb r1,(r4)+ (#123, #333)
|
| 2409 |
|
|
d=000020 -- ! mem(6646)=0000; bisb r1,(r4)+ (#123, #111)
|
| 2410 |
|
|
d=000021 -- ! mem(6650)=000C; comb (r4)+ (#321)
|
| 2411 |
|
|
d=000031 -- ! mem(6652)=N00C; incb (r4)+ (#321) keep C!
|
| 2412 |
|
|
d=000031 -- ! mem(6654)=N00C; decb (r4)+ (#321) keep C!
|
| 2413 |
|
|
d=000021 -- ! mem(6656)=000C; negb (r4)+ (#321)
|
| 2414 |
|
|
d=000030 -- ! mem(6660)=N000; tstb (r4)+ (#321)
|
| 2415 |
|
|
d=000023 -- ! mem(6662)=00VC; rorb (r4)+ (#201)
|
| 2416 |
|
|
d=000031 -- ! mem(6664)=N00C; rorb (r4)+ (#021)
|
| 2417 |
|
|
d=000023 -- ! mem(6666)=00VC; rolb (r4)+ (#210)
|
| 2418 |
|
|
d=000020 -- ! mem(6670)=0000; asrb (r4)+ (#020)
|
| 2419 |
|
|
d=000032 -- ! mem(6672)=N0V0; asrb (r4)+ (#220)
|
| 2420 |
|
|
d=000020 -- ! mem(6674)=0000; aslb (r4)+ (#020)
|
| 2421 |
|
|
d=000023 -- ! mem(6676)=00VC; aslb (r4)+ (#220)
|
| 2422 |
|
|
#
|
| 2423 |
30 |
wfjm |
cres -- console reset (to clear T flag)
|
| 2424 |
2 |
wfjm |
wal 000014 -- vector: 14 -> trap catcher again
|
| 2425 |
|
|
bwm 2
|
| 2426 |
|
|
000016 -- PC:16
|
| 2427 |
|
|
000000 -- PS:0
|
| 2428 |
|
|
#-----------------------------------------------------------------------------
|
| 2429 |
|
|
C Setup code 26 [base 6700; use 67-70] (address modes torture tests)
|
| 2430 |
|
|
#
|
| 2431 |
|
|
wal 006700 -- code test 1:
|
| 2432 |
|
|
bwm 5
|
| 2433 |
|
|
012020 -- mov (r0)+,(r0)+
|
| 2434 |
|
|
062020 -- add (r0)+,(r0)+
|
| 2435 |
|
|
014141 -- mov -(r1),-(r1)
|
| 2436 |
|
|
064141 -- add -(r1),-(r1)
|
| 2437 |
|
|
#6710
|
| 2438 |
|
|
000000 -- halt
|
| 2439 |
|
|
#-----
|
| 2440 |
|
|
wal 006720 -- code test 2:
|
| 2441 |
|
|
bwm 8
|
| 2442 |
|
|
016767 -- mov a(pc),b(pc)
|
| 2443 |
|
|
000014 -- here pc=6724, target@6740 --> index=14
|
| 2444 |
|
|
000014 -- here pc=6726, target@6742 --> index=14
|
| 2445 |
|
|
066767 -- add c(pc),d(pc)
|
| 2446 |
|
|
#6730
|
| 2447 |
|
|
000012 -- here pc=6732, target@6744 --> index=12
|
| 2448 |
|
|
000012 -- here pc=6734, target@6746 --> index=12
|
| 2449 |
|
|
000000 -- halt
|
| 2450 |
|
|
000000 -- halt
|
| 2451 |
|
|
#
|
| 2452 |
|
|
wal 006740 -- data (pc relative) for test 2:
|
| 2453 |
|
|
bwm 4
|
| 2454 |
|
|
006740 -- target for mov a(pc)
|
| 2455 |
|
|
006742 -- target for ,b(pc)
|
| 2456 |
|
|
000011 -- target for add c(pc)
|
| 2457 |
|
|
006746 -- target for ,d(pc)
|
| 2458 |
|
|
#-----
|
| 2459 |
|
|
wal 006750 -- code test 3:
|
| 2460 |
|
|
bwm 12
|
| 2461 |
|
|
012727 -- mov #1,#0
|
| 2462 |
|
|
000001
|
| 2463 |
|
|
000000
|
| 2464 |
|
|
062727 -- add #1,#2
|
| 2465 |
|
|
#6760
|
| 2466 |
|
|
000001
|
| 2467 |
|
|
000002
|
| 2468 |
|
|
016767 -- mov -14(pc),2(pc)
|
| 2469 |
|
|
177764 -- pc here: 6770: read dst of mov #1,#0 (@6754)
|
| 2470 |
|
|
000002 -- pc here: 6772: write src of add #0,r0 (@6774)
|
| 2471 |
|
|
062700 -- add #0,r0
|
| 2472 |
|
|
000000
|
| 2473 |
|
|
000000 -- halt
|
| 2474 |
|
|
#-----
|
| 2475 |
|
|
wal 007000 -- code test 4:
|
| 2476 |
|
|
bwm 8
|
| 2477 |
|
|
005200 -- inc r0
|
| 2478 |
|
|
010001 -- mov r0,r1
|
| 2479 |
|
|
010702 -- mov pc,r2
|
| 2480 |
|
|
005007 -- clr pc
|
| 2481 |
|
|
000000 -- halt
|
| 2482 |
|
|
000000 -- halt
|
| 2483 |
|
|
005203 -- L1: inc r3
|
| 2484 |
|
|
000000 -- halt
|
| 2485 |
|
|
#-----
|
| 2486 |
|
|
wal 000000 -- code test 4 (handler at address=0):
|
| 2487 |
|
|
bwm 2
|
| 2488 |
|
|
000137 -- jmp @#L1
|
| 2489 |
|
|
007014
|
| 2490 |
|
|
#-----
|
| 2491 |
|
|
wal 007020 -- code test 5:
|
| 2492 |
|
|
bwm 11
|
| 2493 |
|
|
012707 -- mov #L2,pc
|
| 2494 |
|
|
007032
|
| 2495 |
|
|
000000 -- halt
|
| 2496 |
|
|
000000 -- halt
|
| 2497 |
|
|
000000 -- halt
|
| 2498 |
|
|
062707 -- L2: add #2,pc
|
| 2499 |
|
|
000002
|
| 2500 |
|
|
005201 -- inc r1
|
| 2501 |
|
|
#7040
|
| 2502 |
|
|
005201 -- inc r1
|
| 2503 |
|
|
005201 -- inc r1
|
| 2504 |
|
|
000000 -- halt
|
| 2505 |
|
|
#-----
|
| 2506 |
|
|
wal 007060 -- data for test 1 (r0)+ part:
|
| 2507 |
|
|
bwm 4
|
| 2508 |
|
|
000111
|
| 2509 |
|
|
000222
|
| 2510 |
|
|
000333
|
| 2511 |
|
|
000444
|
| 2512 |
|
|
wal 007070 -- data for test 1 -(r1) part:
|
| 2513 |
|
|
bwm 4
|
| 2514 |
|
|
000111
|
| 2515 |
|
|
000222
|
| 2516 |
|
|
000333
|
| 2517 |
|
|
000444
|
| 2518 |
|
|
C Exec code 26 (address modes torture tests)
|
| 2519 |
|
|
C Exec test 26.1 (test src-dst update hazards with (r0)+,(r0)+ ect):
|
| 2520 |
|
|
#
|
| 2521 |
|
|
wr0 007060 -- r0=7060 (input data for (r0)+...)
|
| 2522 |
|
|
wr1 007100 -- r1=7100 (input data for -(r1)...)
|
| 2523 |
|
|
wsp 001400 -- sp=1400
|
| 2524 |
30 |
wfjm |
cres
|
| 2525 |
2 |
wfjm |
stapc 006700 -- start @ 6700
|
| 2526 |
|
|
wtgo
|
| 2527 |
|
|
rr0 d=007070 -- ! r0
|
| 2528 |
|
|
rr1 d=007070 -- ! r1
|
| 2529 |
|
|
rpc d=006712 -- ! pc
|
| 2530 |
|
|
wal 007060 --
|
| 2531 |
|
|
brm 4
|
| 2532 |
|
|
d=000111 -- ! mem(7060)
|
| 2533 |
|
|
d=000111 -- ! mem(7062)
|
| 2534 |
|
|
d=000333 -- ! mem(7064)
|
| 2535 |
|
|
d=000777 -- ! mem(7066)
|
| 2536 |
|
|
wal 007070 --
|
| 2537 |
|
|
brm 4
|
| 2538 |
|
|
d=000333 -- ! mem(7070)
|
| 2539 |
|
|
d=000222 -- ! mem(7072)
|
| 2540 |
|
|
d=000444 -- ! mem(7074)
|
| 2541 |
|
|
d=000444 -- ! mem(7076)
|
| 2542 |
|
|
C Exec test 26.2 (test indexed mode with pc (mode 67)):
|
| 2543 |
|
|
#
|
| 2544 |
|
|
wsp 001400 -- sp=1400
|
| 2545 |
30 |
wfjm |
cres
|
| 2546 |
2 |
wfjm |
stapc 006720 -- start @ 6720
|
| 2547 |
|
|
wtgo
|
| 2548 |
|
|
rpc d=006736 -- ! pc
|
| 2549 |
|
|
wal 006740 --
|
| 2550 |
|
|
brm 4
|
| 2551 |
|
|
d=006740 -- ! mem(6740)
|
| 2552 |
|
|
d=006740 -- ! mem(6742)
|
| 2553 |
|
|
d=000011 -- ! mem(6744)
|
| 2554 |
|
|
d=006757 -- ! mem(6746)
|
| 2555 |
|
|
C Exec test 26.3 (test (pc)+ as dst):
|
| 2556 |
|
|
#
|
| 2557 |
|
|
wr0 000111 -- r0=0111
|
| 2558 |
|
|
wsp 001400 -- sp=1400
|
| 2559 |
30 |
wfjm |
cres
|
| 2560 |
2 |
wfjm |
stapc 006750 -- start @ 6750
|
| 2561 |
|
|
wtgo
|
| 2562 |
|
|
rr0 d=000112 -- ! r0
|
| 2563 |
|
|
rpc d=007000 -- ! pc
|
| 2564 |
|
|
wal 006752 --
|
| 2565 |
|
|
brm 2
|
| 2566 |
|
|
d=000001 -- ! mem(6752) src mov #1,#0
|
| 2567 |
|
|
d=000001 -- ! mem(6754) dst mov #1,#0
|
| 2568 |
|
|
wal 006760 --
|
| 2569 |
|
|
brm 2
|
| 2570 |
|
|
d=000001 -- ! mem(6760) src add #1,#2
|
| 2571 |
|
|
d=000003 -- ! mem(6762) dst add #1,#2
|
| 2572 |
|
|
wal 006774 -- !
|
| 2573 |
|
|
rmi d=000001 -- ! mem(6774) dst mov -12(pc),2(pc)
|
| 2574 |
|
|
C Exec test 26.4 (test pc as dst in clr):
|
| 2575 |
|
|
#
|
| 2576 |
|
|
wr0 000100 -- r0=0100
|
| 2577 |
|
|
wr1 000110 -- r1=0110
|
| 2578 |
|
|
wr2 000120 -- r2=0120
|
| 2579 |
|
|
wr3 000130 -- r3=0130
|
| 2580 |
|
|
wsp 001400 -- sp=1400
|
| 2581 |
30 |
wfjm |
cres
|
| 2582 |
2 |
wfjm |
stapc 007000 -- start @ 7000
|
| 2583 |
|
|
wtgo
|
| 2584 |
|
|
rr0 d=000101 -- ! r0
|
| 2585 |
|
|
rr1 d=000101 -- ! r1
|
| 2586 |
|
|
rr2 d=007006 -- ! r2 (pc after mov pc,r2)
|
| 2587 |
|
|
rr3 d=000131 -- ! r3
|
| 2588 |
|
|
rpc d=007020 -- ! pc
|
| 2589 |
|
|
# cleanup 'vector 0':
|
| 2590 |
|
|
wal 000000
|
| 2591 |
|
|
bwm 2
|
| 2592 |
|
|
000000
|
| 2593 |
|
|
000000
|
| 2594 |
|
|
C Exec test 26.5 (test pc as dst in mov and add):
|
| 2595 |
|
|
#
|
| 2596 |
|
|
wr1 000000 -- r1=0
|
| 2597 |
|
|
wsp 001400 -- sp=1400
|
| 2598 |
30 |
wfjm |
cres
|
| 2599 |
2 |
wfjm |
stapc 007020 -- start @ 7020
|
| 2600 |
|
|
wtgo
|
| 2601 |
|
|
rr1 d=000002 -- ! r1
|
| 2602 |
|
|
rpc d=007046 -- ! pc
|
| 2603 |
|
|
#-----------------------------------------------------------------------------
|
| 2604 |
|
|
C Setup code 27 [base 7100; use 71-101] (test ASH/ASHC instruction)
|
| 2605 |
|
|
#
|
| 2606 |
|
|
wal 007100 -- code test 1 (ash)
|
| 2607 |
|
|
bwm 7
|
| 2608 |
|
|
000230 -- spl 0
|
| 2609 |
|
|
012004 -- L1: mov (r0)+,r4 -- load low
|
| 2610 |
|
|
072420 -- ash (r0)+,r4 -- shift
|
| 2611 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
| 2612 |
|
|
010421 -- mov r4,(r1)+ -- store low
|
| 2613 |
|
|
077205 -- sob r2,L1 (.-5)
|
| 2614 |
|
|
000000 -- halt
|
| 2615 |
|
|
#-----
|
| 2616 |
|
|
wal 007120 -- code test 2 (ashc even)
|
| 2617 |
|
|
bwm 9
|
| 2618 |
|
|
000230 -- spl 0
|
| 2619 |
|
|
012004 -- L1: mov (r0)+,r4 -- load high
|
| 2620 |
|
|
012005 -- mov (r0)+,r5 -- load low
|
| 2621 |
|
|
073420 -- ashc (r0)+,r4 -- shift
|
| 2622 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
| 2623 |
|
|
010421 -- mov r4,(r1)+ -- store high
|
| 2624 |
|
|
010521 -- mov r5,(r1)+ -- store low
|
| 2625 |
|
|
077207 -- sob r2,L1 (.-7)
|
| 2626 |
|
|
#7140
|
| 2627 |
|
|
000000 -- halt
|
| 2628 |
|
|
#-----
|
| 2629 |
|
|
wal 007150 -- code test 3 (ashc odd)
|
| 2630 |
|
|
bwm 7
|
| 2631 |
|
|
000230 -- spl 0
|
| 2632 |
|
|
012005 -- L1: mov (r0)+,r5 -- load low
|
| 2633 |
|
|
073520 -- ashc (r0)+,r5 -- shift
|
| 2634 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
| 2635 |
|
|
#7160
|
| 2636 |
|
|
010521 -- mov r5,(r1)+ -- store low
|
| 2637 |
|
|
077205 -- sob r2,L1 (.-5)
|
| 2638 |
|
|
000000 -- halt
|
| 2639 |
|
|
#-----
|
| 2640 |
|
|
wal 007200 -- data 1:
|
| 2641 |
|
|
bwm 24
|
| 2642 |
|
|
000200 -- (000200, +1)
|
| 2643 |
|
|
000001 --
|
| 2644 |
|
|
000200 -- (000200, -1)
|
| 2645 |
|
|
177777 --
|
| 2646 |
|
|
000200 -- (000200, +7)
|
| 2647 |
|
|
000007 --
|
| 2648 |
|
|
000200 -- (000200, +8)
|
| 2649 |
|
|
000010 --
|
| 2650 |
|
|
#7220
|
| 2651 |
|
|
000200 -- (000200, +9)
|
| 2652 |
|
|
000011 --
|
| 2653 |
|
|
000200 -- (000200, -7)
|
| 2654 |
|
|
177771 --
|
| 2655 |
|
|
100000 -- (100000, 0)
|
| 2656 |
|
|
000000 --
|
| 2657 |
|
|
000000 -- (000000, 0)
|
| 2658 |
|
|
000000 --
|
| 2659 |
|
|
#7240
|
| 2660 |
|
|
000200 -- (000200, -8)
|
| 2661 |
|
|
177770 --
|
| 2662 |
|
|
000200 -- (000200, 0)
|
| 2663 |
|
|
000000 --
|
| 2664 |
|
|
100000 -- (100000, -6)
|
| 2665 |
|
|
177772 --
|
| 2666 |
|
|
040000 -- (040000, +1)
|
| 2667 |
|
|
000001 --
|
| 2668 |
|
|
#-----
|
| 2669 |
|
|
wal 007300 -- data 2:
|
| 2670 |
|
|
bwm 30
|
| 2671 |
|
|
000020 -- (000020,000200, +1)
|
| 2672 |
|
|
000200 --
|
| 2673 |
|
|
000001 --
|
| 2674 |
|
|
000020 -- (000020,000200, -1)
|
| 2675 |
|
|
000200 --
|
| 2676 |
|
|
177777 --
|
| 2677 |
|
|
000020 -- (000020,000200, +7)
|
| 2678 |
|
|
000200 --
|
| 2679 |
|
|
#7320
|
| 2680 |
|
|
000007 --
|
| 2681 |
|
|
000020 -- (000020,000200, +8)
|
| 2682 |
|
|
000200 --
|
| 2683 |
|
|
000010 --
|
| 2684 |
|
|
000020 -- (000020,000200, +9)
|
| 2685 |
|
|
000200 --
|
| 2686 |
|
|
000011 --
|
| 2687 |
|
|
000000 -- (000000,000200, +23)
|
| 2688 |
|
|
#7340
|
| 2689 |
|
|
000200 --
|
| 2690 |
|
|
000027 --
|
| 2691 |
|
|
000000 -- (000000,000200, +24)
|
| 2692 |
|
|
000200 --
|
| 2693 |
|
|
000030 --
|
| 2694 |
|
|
000000 -- (000000,000200, +25)
|
| 2695 |
|
|
000200 --
|
| 2696 |
|
|
000031 --
|
| 2697 |
|
|
#7360
|
| 2698 |
|
|
000020 -- (000020,000200, -5)
|
| 2699 |
|
|
000200 --
|
| 2700 |
|
|
177773 --
|
| 2701 |
|
|
000020 -- (000020,000200, -8)
|
| 2702 |
|
|
000200 --
|
| 2703 |
|
|
177770 --
|
| 2704 |
|
|
#-----
|
| 2705 |
|
|
wal 007440 -- data 3:
|
| 2706 |
|
|
bwm 6
|
| 2707 |
|
|
000200 -- (000200, +1)
|
| 2708 |
|
|
000001 --
|
| 2709 |
|
|
000200 -- (000200, -1)
|
| 2710 |
|
|
177777 --
|
| 2711 |
|
|
000201 -- (000201, -1)
|
| 2712 |
|
|
177777 --
|
| 2713 |
|
|
#
|
| 2714 |
|
|
C Exec code 27 (test ASH/ASHC instruction)
|
| 2715 |
|
|
C Exec test 27.1 (test ash)
|
| 2716 |
|
|
#
|
| 2717 |
|
|
wr0 007200 -- r0=7200 (input data)
|
| 2718 |
|
|
wr1 007500 -- r1=7500 (output data)
|
| 2719 |
|
|
wr2 000014 -- r2=14 (test count)
|
| 2720 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
| 2721 |
|
|
wsp 001400 -- sp=1400
|
| 2722 |
30 |
wfjm |
cres
|
| 2723 |
2 |
wfjm |
stapc 007100 -- start @ 7100
|
| 2724 |
|
|
wtgo
|
| 2725 |
|
|
rr0 d=007260 -- ! r0
|
| 2726 |
|
|
rr1 d=007560 -- ! r1
|
| 2727 |
|
|
rpc d=007116 -- ! pc
|
| 2728 |
|
|
wal 007500 --
|
| 2729 |
|
|
brm 24
|
| 2730 |
|
|
d=000000 -- ! mem(7500) ash +1, 000200 -> nzvc=0
|
| 2731 |
|
|
d=000400 -- ! mem(7502)
|
| 2732 |
|
|
d=000000 -- ! mem(7504) ash -1, 000200 -> nzvc=0
|
| 2733 |
|
|
d=000100 -- ! mem(7506)
|
| 2734 |
|
|
d=000000 -- ! mem(7510) ash +7, 000200 -> nzvc=0
|
| 2735 |
|
|
d=040000 -- ! mem(7512)
|
| 2736 |
|
|
d=000012 -- ! mem(7514) ash +8, 000200 -> n1,z0,v1,c0
|
| 2737 |
|
|
d=100000 -- ! mem(7516)
|
| 2738 |
|
|
d=000007 -- ! mem(7520) ash +9, 000200 -> n0,z1,v1,c1
|
| 2739 |
|
|
d=000000 -- ! mem(7522)
|
| 2740 |
|
|
d=000000 -- ! mem(7524) ash -7, 000200 -> nzvc=0
|
| 2741 |
|
|
d=000001 -- ! mem(7526)
|
| 2742 |
|
|
d=000010 -- ! mem(7530) ash 0, 100000 -> n1,z0,v0,c0
|
| 2743 |
|
|
d=100000 -- ! mem(7532)
|
| 2744 |
|
|
d=000004 -- ! mem(7534) ash 0, 000000 -> n0,z1,v0,c0
|
| 2745 |
|
|
d=000000 -- ! mem(7536)
|
| 2746 |
|
|
d=000005 -- ! mem(7540) ash -8, 000200 -> n1,z1,v0,c1
|
| 2747 |
|
|
d=000000 -- ! mem(7542)
|
| 2748 |
|
|
d=000000 -- ! mem(7544) ash 0, 000200 -> n0,z0,v0,c0
|
| 2749 |
|
|
d=000200 -- ! mem(7546)
|
| 2750 |
|
|
d=000010 -- ! mem(7550) ash -6, 100000 -> n1,z0,v0,c0
|
| 2751 |
|
|
d=177000 -- ! mem(7552)
|
| 2752 |
|
|
d=000012 -- ! mem(7554) ash +1, 040000 -> n1,z0,v1,c0
|
| 2753 |
|
|
d=100000 -- ! mem(7556)
|
| 2754 |
|
|
#----
|
| 2755 |
|
|
C Exec test 27.2 (test ashc even)
|
| 2756 |
|
|
#
|
| 2757 |
|
|
wr0 007300 -- r0=7300 (input data)
|
| 2758 |
|
|
wr1 007600 -- r1=7600 (output data)
|
| 2759 |
|
|
wr2 000012 -- r2=12 (test count)
|
| 2760 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
| 2761 |
|
|
wsp 001400 -- sp=1400
|
| 2762 |
30 |
wfjm |
cres
|
| 2763 |
2 |
wfjm |
stapc 007120 -- start @ 7120
|
| 2764 |
|
|
wtgo
|
| 2765 |
|
|
rr0 d=007374 -- ! r0
|
| 2766 |
|
|
rr1 d=007674 -- ! r1
|
| 2767 |
|
|
rpc d=007142 -- ! pc
|
| 2768 |
|
|
wal 007600 --
|
| 2769 |
|
|
brm 30
|
| 2770 |
|
|
d=000000 -- ! mem(7600) ashc +1, 000020,000200 -> nzvc=0
|
| 2771 |
|
|
d=000040 -- ! mem(7602)
|
| 2772 |
|
|
d=000400 -- ! mem(7604)
|
| 2773 |
|
|
d=000000 -- ! mem(7606) ashc -1, 000020,000200 -> nzvc=0
|
| 2774 |
|
|
d=000010 -- ! mem(7610)
|
| 2775 |
|
|
d=000100 -- ! mem(7612)
|
| 2776 |
|
|
d=000000 -- ! mem(7614) ashc +7, 000020,000200 -> nzvc=0
|
| 2777 |
|
|
d=004000 -- ! mem(7616)
|
| 2778 |
|
|
d=040000 -- ! mem(7620)
|
| 2779 |
|
|
d=000000 -- ! mem(7622) ashc +8, 000020,000200 -> nzvc=0
|
| 2780 |
|
|
d=010000 -- ! mem(7624)
|
| 2781 |
|
|
d=100000 -- ! mem(7626)
|
| 2782 |
|
|
d=000000 -- ! mem(7630) ashc +9, 000020,000200 -> nzvc=0
|
| 2783 |
|
|
d=020001 -- ! mem(7632)
|
| 2784 |
|
|
d=000000 -- ! mem(7634)
|
| 2785 |
|
|
d=000000 -- ! mem(7636) ashc +23, 000000,000200 -> nzvc=0
|
| 2786 |
|
|
d=040000 -- ! mem(7640)
|
| 2787 |
|
|
d=000000 -- ! mem(7642)
|
| 2788 |
|
|
d=000012 -- ! mem(7644) ashc +24, 000000,000200 -> n1z0v1c0
|
| 2789 |
|
|
d=100000 -- ! mem(7646)
|
| 2790 |
|
|
d=000000 -- ! mem(7650)
|
| 2791 |
|
|
d=000007 -- ! mem(7652) ashc +25, 000000,000200 -> n0z1v1c1
|
| 2792 |
|
|
d=000000 -- ! mem(7654)
|
| 2793 |
|
|
d=000000 -- ! mem(7656)
|
| 2794 |
|
|
d=000000 -- ! mem(7660) ashc -5, 000020,000200 -> nzvc=0
|
| 2795 |
|
|
d=000000 -- ! mem(7662)
|
| 2796 |
|
|
d=100004 -- ! mem(7664)
|
| 2797 |
|
|
d=000001 -- ! mem(7666) ashc -8, 000020,000200 -> n0z0v0c1
|
| 2798 |
|
|
d=000000 -- ! mem(7670)
|
| 2799 |
|
|
d=010000 -- ! mem(7672)
|
| 2800 |
|
|
#----
|
| 2801 |
|
|
C Exec test 27.3 (test ashc odd)
|
| 2802 |
|
|
#
|
| 2803 |
|
|
wr0 007440 -- r0=7440 (input data)
|
| 2804 |
|
|
wr1 007740 -- r1=7740 (output data)
|
| 2805 |
|
|
wr2 000003 -- r2=3 (test count)
|
| 2806 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
| 2807 |
|
|
wsp 001400 -- sp=1400
|
| 2808 |
30 |
wfjm |
cres
|
| 2809 |
2 |
wfjm |
stapc 007150 -- start @ 7150
|
| 2810 |
|
|
wtgo
|
| 2811 |
|
|
rr0 d=007454 -- ! r0
|
| 2812 |
|
|
rr1 d=007754 -- ! r1
|
| 2813 |
|
|
rpc d=007166 -- ! pc
|
| 2814 |
|
|
wal 007740 --
|
| 2815 |
|
|
brm 6
|
| 2816 |
|
|
d=000000 -- ! mem(7740) ashc +1, 000200 -> nzvc=0
|
| 2817 |
|
|
d=000400 -- ! mem(7742)
|
| 2818 |
|
|
d=000000 -- ! mem(7744) ashc -1, 000200 -> nzvc=0
|
| 2819 |
|
|
d=000100 -- ! mem(7746)
|
| 2820 |
|
|
d=000001 -- ! mem(7750) ashc -1, 000201 -> n0z0v0c1
|
| 2821 |
|
|
d=100100 -- ! mem(7752)
|
| 2822 |
|
|
#-----------------------------------------------------------------------------
|
| 2823 |
|
|
C Setup code 30 [base 10200; use 102-103] (test MUL instruction)
|
| 2824 |
|
|
#
|
| 2825 |
|
|
wal 010200 -- code test 1 (mul even)
|
| 2826 |
|
|
bwm 8
|
| 2827 |
|
|
000230 -- spl 0
|
| 2828 |
|
|
012004 -- L1: mov (r0)+,r4 -- load p1
|
| 2829 |
|
|
070420 -- mul (r0)+,r4 -- mul
|
| 2830 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
| 2831 |
|
|
010421 -- mov r4,(r1)+ -- store p_high
|
| 2832 |
|
|
010521 -- mov r5,(r1)+ -- store p_low
|
| 2833 |
|
|
077206 -- sob r2,L1 (.-6)
|
| 2834 |
|
|
000000 -- halt
|
| 2835 |
|
|
#-----
|
| 2836 |
|
|
wal 010220 -- code test 2 (mul odd)
|
| 2837 |
|
|
bwm 7
|
| 2838 |
|
|
000230 -- spl 0
|
| 2839 |
|
|
012005 -- L1: mov (r0)+,r5 -- load p1
|
| 2840 |
|
|
070520 -- mul (r0)+,r5 -- mul
|
| 2841 |
|
|
010521 -- mov r5,(r1)+ -- store p_low
|
| 2842 |
|
|
060403 -- add r4,r3 -- check r4
|
| 2843 |
|
|
077205 -- sob r2,L1 (.-5)
|
| 2844 |
|
|
000000 -- halt
|
| 2845 |
|
|
#
|
| 2846 |
|
|
# 31022 074456 * 9562 022532 -> 296632364 010656,040054
|
| 2847 |
|
|
# 18494 044076 * -24041 121027 -> -444614254 162577,134622
|
| 2848 |
|
|
# -12549 147373 * 2397 004535 -> -30079953 177065,002057
|
| 2849 |
|
|
# -20493 127763 * -23858 121316 -> 488921994 016444,055612
|
| 2850 |
|
|
#
|
| 2851 |
|
|
# 105 000151 * 198 000306 -> 20790 000000,050466
|
| 2852 |
|
|
# 233 000351 * -94 177642 -> -21902 177777,125162
|
| 2853 |
|
|
# 186 000272 * -205 177463 -> -38130 177777,065416
|
| 2854 |
|
|
#
|
| 2855 |
|
|
wal 010240 -- data 1:
|
| 2856 |
|
|
bwm 16
|
| 2857 |
|
|
074456 --
|
| 2858 |
|
|
022532 --
|
| 2859 |
|
|
044076 --
|
| 2860 |
|
|
121027 --
|
| 2861 |
|
|
147373 --
|
| 2862 |
|
|
004535 --
|
| 2863 |
|
|
127763 --
|
| 2864 |
|
|
121316 --
|
| 2865 |
|
|
#10260
|
| 2866 |
|
|
000151 --
|
| 2867 |
|
|
000306 --
|
| 2868 |
|
|
000351 --
|
| 2869 |
|
|
177642 --
|
| 2870 |
|
|
000272 --
|
| 2871 |
|
|
177463 --
|
| 2872 |
|
|
000000 --
|
| 2873 |
|
|
000272 --
|
| 2874 |
|
|
#
|
| 2875 |
|
|
C Exec code 30 (test MUL instruction)
|
| 2876 |
|
|
C Exec test 30.1 (test mul even)
|
| 2877 |
|
|
#
|
| 2878 |
|
|
wr0 010240 -- r0=10240 (input data)
|
| 2879 |
|
|
wr1 010300 -- r1=10300 (output data)
|
| 2880 |
|
|
wr2 000010 -- r2=10 (test count)
|
| 2881 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
| 2882 |
|
|
wsp 001400 -- sp=1400
|
| 2883 |
30 |
wfjm |
cres
|
| 2884 |
2 |
wfjm |
stapc 010200 -- start @ 10200
|
| 2885 |
|
|
wtgo
|
| 2886 |
|
|
rr0 d=010300 -- ! r0
|
| 2887 |
|
|
rr1 d=010360 -- ! r1
|
| 2888 |
|
|
rpc d=010220 -- ! pc
|
| 2889 |
|
|
wal 010300 --
|
| 2890 |
|
|
brm 24
|
| 2891 |
|
|
d=000001 -- ! mem(10300) mul 074456,022532 -> n0z0v0c1
|
| 2892 |
|
|
d=010656 -- ! mem(10302)
|
| 2893 |
|
|
d=040054 -- ! mem(10304)
|
| 2894 |
|
|
d=000011 -- ! mem(10306) mul 044076,121027 -> n1z0v0c1
|
| 2895 |
|
|
d=162577 -- ! mem(10310)
|
| 2896 |
|
|
d=134622 -- ! mem(10312)
|
| 2897 |
|
|
d=000011 -- ! mem(10314) mul 147373,004535 -> n1z0v0c1
|
| 2898 |
|
|
d=177065 -- ! mem(10316)
|
| 2899 |
|
|
d=002057 -- ! mem(10320)
|
| 2900 |
|
|
d=000001 -- ! mem(10322) mul 127763,121316 -> n0z0v0c1
|
| 2901 |
|
|
d=016444 -- ! mem(10324)
|
| 2902 |
|
|
d=055612 -- ! mem(10326)
|
| 2903 |
|
|
d=000000 -- ! mem(10330) mul 000151,000306 -> n0z0v0c0
|
| 2904 |
|
|
d=000000 -- ! mem(10332)
|
| 2905 |
|
|
d=050466 -- ! mem(10334)
|
| 2906 |
|
|
d=000010 -- ! mem(10336) mul 000351,177642 -> n1z0v0c0
|
| 2907 |
|
|
d=177777 -- ! mem(10340)
|
| 2908 |
|
|
d=125162 -- ! mem(10342)
|
| 2909 |
|
|
d=000011 -- ! mem(10344) mul 000272,177463 -> n1z0v0c1
|
| 2910 |
|
|
d=177777 -- ! mem(10346)
|
| 2911 |
|
|
d=065416 -- ! mem(10350)
|
| 2912 |
|
|
d=000004 -- ! mem(10352) mul 000000,000272 -> n0z1v0c0
|
| 2913 |
|
|
d=000000 -- ! mem(10354)
|
| 2914 |
|
|
d=000000 -- ! mem(10356)
|
| 2915 |
|
|
#----
|
| 2916 |
|
|
C Exec test 30.2 (test mul odd)
|
| 2917 |
|
|
#
|
| 2918 |
|
|
wr0 010240 -- r0=10240 (input data)
|
| 2919 |
|
|
wr1 010360 -- r1=10300 (output data)
|
| 2920 |
|
|
wr2 000010 -- r2=10 (test count)
|
| 2921 |
|
|
wr3 000000 -- r3=0
|
| 2922 |
|
|
wr4 000000 -- r4=0
|
| 2923 |
|
|
wsp 001400 -- sp=1400
|
| 2924 |
30 |
wfjm |
cres
|
| 2925 |
2 |
wfjm |
stapc 010220 -- start @ 10220
|
| 2926 |
|
|
wtgo
|
| 2927 |
|
|
rr0 d=010300 -- ! r0
|
| 2928 |
|
|
rr1 d=010400 -- ! r1
|
| 2929 |
|
|
rr3 d=000000 -- ! r3
|
| 2930 |
|
|
rpc d=010236 -- ! pc
|
| 2931 |
|
|
wal 010360 --
|
| 2932 |
|
|
brm 8
|
| 2933 |
|
|
d=040054 -- ! mem(10360)
|
| 2934 |
|
|
d=134622 -- ! mem(10362)
|
| 2935 |
|
|
d=002057 -- ! mem(10364)
|
| 2936 |
|
|
d=055612 -- ! mem(10366)
|
| 2937 |
|
|
d=050466 -- ! mem(10370)
|
| 2938 |
|
|
d=125162 -- ! mem(10372)
|
| 2939 |
|
|
d=065416 -- ! mem(10374)
|
| 2940 |
|
|
d=000000 -- ! mem(10376)
|
| 2941 |
|
|
#
|
| 2942 |
|
|
#-----------------------------------------------------------------------------
|
| 2943 |
|
|
C Setup code 31 [base 10400; use 104-110] (test DIV instruction, also ADC,SXT)
|
| 2944 |
|
|
# Note: test 2 uses sbc too, but if div/div work correctly we have always
|
| 2945 |
|
|
# C=0 for sbc, so sbc isn't tested. adc has C=0 or C=1 though.
|
| 2946 |
|
|
#
|
| 2947 |
|
|
wal 010400 -- code test 1
|
| 2948 |
|
|
bwm 8
|
| 2949 |
|
|
012004 -- L1: mov (r0)+,r4 -- load dd high
|
| 2950 |
|
|
012005 -- mov (r0)+,r5 -- load dd low
|
| 2951 |
|
|
071420 -- div (r0)+,r4 -- div
|
| 2952 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
| 2953 |
|
|
010421 -- mov r4,(r1)+ -- store q
|
| 2954 |
|
|
010521 -- mov r5,(r1)+ -- store r
|
| 2955 |
|
|
077207 -- sob r2,L1 (.-7)
|
| 2956 |
|
|
000000 -- halt
|
| 2957 |
|
|
#-----
|
| 2958 |
|
|
wal 010420 -- code test 2
|
| 2959 |
|
|
bwm 24
|
| 2960 |
|
|
012146 -- L1: mov (r1)+,-(sp) -- save psw on stack
|
| 2961 |
|
|
016002 -- mov 4(r0),r2 -- load divisor
|
| 2962 |
|
|
000004
|
| 2963 |
|
|
070221 -- mul (r1)+,r2 -- multiply with quotient
|
| 2964 |
|
|
061103 -- add (r1),r3 -- add reminder
|
| 2965 |
|
|
005502 -- adc r2
|
| 2966 |
|
|
005721 -- tst (r1)+
|
| 2967 |
|
|
006704 -- sxt r4
|
| 2968 |
|
|
#10440
|
| 2969 |
|
|
060402 -- add r4,r2
|
| 2970 |
|
|
166003 -- sub 2(r0),r3 -- subtract divident
|
| 2971 |
|
|
000002
|
| 2972 |
|
|
005602 -- sbc r2
|
| 2973 |
|
|
161002 -- sub (r0),r2
|
| 2974 |
|
|
001002 -- bne L2 (.+2) -- error if !=0
|
| 2975 |
|
|
005703 -- tst r3
|
| 2976 |
|
|
001404 -- beq L3 (.+4) -- error if !=0
|
| 2977 |
|
|
#10460
|
| 2978 |
|
|
032726 -- L2: bit #3,(sp)+ -- check V,C bits
|
| 2979 |
|
|
000003
|
| 2980 |
|
|
001001 -- bne L3 (.+1) -- if V or C =1, ignore
|
| 2981 |
|
|
000000 -- halt
|
| 2982 |
|
|
062700 -- L3: add #6,r0 --
|
| 2983 |
|
|
000006 --
|
| 2984 |
|
|
077527 -- sob r5,L1 (.-23)
|
| 2985 |
|
|
000000 -- halt
|
| 2986 |
|
|
# r q
|
| 2987 |
|
|
# 6249 014151 * 9158 021706 + 4989 011575 -> 57233331 001551,047663 y n
|
| 2988 |
|
|
# 5194 012112 * -23807 121401 + -3990 170152 -> -123657548 174241,021264 n y
|
| 2989 |
|
|
# -19943 131031 * 27112 064750 + -16037 140533 -> -540710653 157705,064403 y n
|
| 2990 |
|
|
# -20493 127763 * -23858 121316 + 10744 024770 -> 488932738 016444,102602 y y
|
| 2991 |
|
|
#
|
| 2992 |
|
|
# -12549 147373 * 2397 004535 + -11187 152115 -> -30091140 177064,154174 n n
|
| 2993 |
|
|
# 22620 054134 * -9272 155710 + -19907 131075 -> -209752547 171577,067035 y y
|
| 2994 |
|
|
# 10723 024743 * 7931 017373 + 9824 023140 -> 85053937 002421,150761 n n
|
| 2995 |
|
|
# -3548 171044 * -15677 141303 + 3019 005713 -> 55625015 001520,142467 n y
|
| 2996 |
|
|
#
|
| 2997 |
|
|
## 1 000001 * -32767 100001 + 0 000000 -> -32767 177777,100001 V=0
|
| 2998 |
|
|
## -1 177777 * 32767 077777 + 0 000000 -> -32767 177777,100001 V=0
|
| 2999 |
|
|
# 1 000001 * -32768 100000 + 0 000000 -> -32768 177777,100000 V=1
|
| 3000 |
|
|
# -1 177777 * ...... ...... + 0 000000 -> -32768 177777,100000 V=1
|
| 3001 |
|
|
#
|
| 3002 |
|
|
# 32767 077777 * 32767 077777 + 32766 077776 -> 1073709055 037777,077777 V=0
|
| 3003 |
|
|
# 32767 077777 * ............ + ............ -> 1073709056 037777,100000 V=1
|
| 3004 |
|
|
# 32767 077777 * -32767 100001 + -32766 100002 ->-1073709055 140000,100001 V=0
|
| 3005 |
|
|
# 32767 077777 * ............ + ............ ->-1073709056 140000,100000 V=1
|
| 3006 |
|
|
#
|
| 3007 |
|
|
# 32767 077777 * ............ + ............ -> 1073741824 040000,000000 V=1
|
| 3008 |
|
|
##32767 077777 * ............ + ............ ->-2147483648 100000,000000 V=1
|
| 3009 |
|
|
#
|
| 3010 |
|
|
#
|
| 3011 |
|
|
wal 010500 -- data 1:
|
| 3012 |
|
|
bwm 63
|
| 3013 |
|
|
000000 -- (000000,000042, 000005) 34/ 5 -> q: 6 r: 4
|
| 3014 |
|
|
000042 --
|
| 3015 |
|
|
000005 --
|
| 3016 |
|
|
000000 -- (000000,000042, 177773) 34/-5 -> q:-6 r: 4
|
| 3017 |
|
|
000042 --
|
| 3018 |
|
|
177773 --
|
| 3019 |
|
|
177777 -- (177777,177736, 000005) -34/ 5 -> q:-6 r:-4
|
| 3020 |
|
|
177736 --
|
| 3021 |
|
|
#010520
|
| 3022 |
|
|
000005 --
|
| 3023 |
|
|
177777 -- (177777,177736, 177773) -34/-5 -> q: 6 r:-4
|
| 3024 |
|
|
177736 --
|
| 3025 |
|
|
177773 --
|
| 3026 |
|
|
001551 -- (001551,047663, 014151) 57233331 / 6249
|
| 3027 |
|
|
047663 -- -> q: 9158 r: 4989
|
| 3028 |
|
|
014151 --
|
| 3029 |
|
|
174241 -- (174241,021264, 012112) -123657548 / 5194
|
| 3030 |
|
|
#010540
|
| 3031 |
|
|
021264 -- -> q: -23807 r: -3990
|
| 3032 |
|
|
012112 --
|
| 3033 |
|
|
157705 -- (157705,064403, 131031) -540710653 / -19943
|
| 3034 |
|
|
064403 -- -> q: 27112 r: -16037
|
| 3035 |
|
|
131031 --
|
| 3036 |
|
|
016444 -- (016444,102602, 127763) 488932738 / -20493
|
| 3037 |
|
|
102602 -- -> q: -23858 r: 10744
|
| 3038 |
|
|
127763 --
|
| 3039 |
|
|
#010560
|
| 3040 |
|
|
177064 -- (177064,154174, 147373) -30091140 / -12549
|
| 3041 |
|
|
154174 -- -> q: 2397 r: -11187
|
| 3042 |
|
|
147373 --
|
| 3043 |
|
|
171577 -- (171577,067035, 054134) -209752547 / 22620
|
| 3044 |
|
|
067035 -- -> q: -9272 r: -19907
|
| 3045 |
|
|
054134 --
|
| 3046 |
|
|
002421 -- (002421,150761, 024743) 85053937 / 10723
|
| 3047 |
|
|
150761 -- -> q: 7931 r: 9824
|
| 3048 |
|
|
#010600
|
| 3049 |
|
|
024743 --
|
| 3050 |
|
|
001520 -- (001520,142467, 171044) 55625015 / -3548
|
| 3051 |
|
|
142467 -- -> q: -15677 r: 3019
|
| 3052 |
|
|
171044 --
|
| 3053 |
|
|
001520 -- (001520,142467,000000) 55625015 / 0
|
| 3054 |
|
|
142467 --
|
| 3055 |
|
|
000000 --
|
| 3056 |
|
|
000000 -- (000000,000000,021706) 0 / 9158
|
| 3057 |
|
|
#010620
|
| 3058 |
|
|
000000 --
|
| 3059 |
|
|
021706 --
|
| 3060 |
|
|
177777 -- (177777,100000,000001) -32768 / 1
|
| 3061 |
|
|
100000 --
|
| 3062 |
|
|
000001 --
|
| 3063 |
|
|
177777 -- (177777,100000,177777) -32768 / -1
|
| 3064 |
|
|
100000 --
|
| 3065 |
|
|
177777 --
|
| 3066 |
|
|
#010640
|
| 3067 |
|
|
037777 -- (037777,077777,077777) 1073709055 / 32767
|
| 3068 |
|
|
077777 --
|
| 3069 |
|
|
077777 --
|
| 3070 |
|
|
037777 -- (037777,100000,077777) 1073709056 / 32767
|
| 3071 |
|
|
100000 --
|
| 3072 |
|
|
077777 --
|
| 3073 |
|
|
140000 -- (140000,100001,077777) -1073709055 / 32767
|
| 3074 |
|
|
100001 --
|
| 3075 |
|
|
#010660
|
| 3076 |
|
|
077777 --
|
| 3077 |
|
|
140000 -- (140000,100000,077777) -1073709056 / 32767
|
| 3078 |
|
|
100000 --
|
| 3079 |
|
|
077777 --
|
| 3080 |
|
|
040000 -- (040000,000000,077777) 1073741824 / 32767
|
| 3081 |
|
|
000000 --
|
| 3082 |
|
|
077777 --
|
| 3083 |
|
|
#
|
| 3084 |
|
|
C Exec code 31 (test DIV instruction, also ADC,SXT)
|
| 3085 |
|
|
C Exec test 31.1 (test div)
|
| 3086 |
|
|
#
|
| 3087 |
|
|
wr0 010500 -- r0=10500 (input data)
|
| 3088 |
|
|
wr1 010700 -- r1=10700 (output data)
|
| 3089 |
|
|
wr2 000025 -- r2=25 (test count)
|
| 3090 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
| 3091 |
|
|
wsp 001400 -- sp=1400
|
| 3092 |
30 |
wfjm |
cres -- console reset ; do reset; cont to start with
|
| 3093 |
2 |
wfjm |
wps 000000 -- clear psw ; psw cc code dump below
|
| 3094 |
|
|
wpc 010400 -- pc=10400
|
| 3095 |
30 |
wfjm |
sta -- start @ 10400
|
| 3096 |
2 |
wfjm |
wtgo
|
| 3097 |
|
|
rr0 d=010676 -- ! r0
|
| 3098 |
|
|
rr1 d=011076 -- ! r1
|
| 3099 |
|
|
rpc d=010420 -- ! pc
|
| 3100 |
|
|
wal 010700 --
|
| 3101 |
|
|
brm 63
|
| 3102 |
|
|
d=000000 -- ! mem(10700) div 000000, 000042,000005 -> n0z0v0c0
|
| 3103 |
|
|
d=000006 -- ! mem(10702) 34/ 5 -> 6,4
|
| 3104 |
|
|
d=000004 -- ! mem(10704)
|
| 3105 |
|
|
d=000010 -- ! mem(10706) div 000000,000042, 177773 -> n1z0v0c0
|
| 3106 |
|
|
d=177772 -- ! mem(10710) 34/-5 -> -6,4
|
| 3107 |
|
|
d=000004 -- ! mem(10712)
|
| 3108 |
|
|
d=000010 -- ! mem(10714) div 177777,177736, 000005 -> n1z0v0c0
|
| 3109 |
|
|
d=177772 -- ! mem(10716) -34/ 5 -> -6,-4
|
| 3110 |
|
|
d=177774 -- ! mem(10720)
|
| 3111 |
|
|
d=000000 -- ! mem(10722) div 177777,177736, 177773 -> n0z0v0c0
|
| 3112 |
|
|
d=000006 -- ! mem(10724) -34/-5 -> 6,-4
|
| 3113 |
|
|
d=177774 -- ! mem(10726)
|
| 3114 |
|
|
d=000000 -- ! mem(10730) div 001551,047663, 014151 -> n0z0v0c0
|
| 3115 |
|
|
d=021706 -- ! mem(10732) 57233331/6249 -> 9158,4989
|
| 3116 |
|
|
d=011575 -- ! mem(10734)
|
| 3117 |
|
|
d=000010 -- ! mem(10736) div 174241,021264, 012112 -> n1z0v0c0
|
| 3118 |
|
|
d=121401 -- ! mem(10740) -123657548/5194 -> -23807,-3990
|
| 3119 |
|
|
d=170152 -- ! mem(10742)
|
| 3120 |
|
|
d=000000 -- ! mem(10744) div 157705,064403, 131031 -> n0z0v0c0
|
| 3121 |
|
|
d=064750 -- ! mem(10746) -540710653/-19943 -> 27112,-16037
|
| 3122 |
|
|
d=140533 -- ! mem(10750)
|
| 3123 |
|
|
d=000010 -- ! mem(10752) div 016444,102602, 127763 -> n1z0v0c0
|
| 3124 |
|
|
d=121316 -- ! mem(10754) 488932738/-20493 -> -23858, 10744
|
| 3125 |
|
|
d=024770 -- ! mem(10756)
|
| 3126 |
|
|
d=000000 -- ! mem(10760) div 177064,154174, 147373 -> n0z0v0c0
|
| 3127 |
|
|
d=004535 -- ! mem(10762) -30091140/-12549 -> 2397,-11187
|
| 3128 |
|
|
d=152115 -- ! mem(10764)
|
| 3129 |
|
|
d=000010 -- ! mem(10766) div 171577,067035, 054134 -> n1z0v0c0
|
| 3130 |
|
|
d=155710 -- ! mem(10770) -209752547/22620 -> -9272,-19907
|
| 3131 |
|
|
d=131075 -- ! mem(10772)
|
| 3132 |
|
|
d=000000 -- ! mem(10774) div 002421,150761, 024743 -> n0z0v0c0
|
| 3133 |
|
|
d=017373 -- ! mem(10776) 85053937/10723 -> 7931,9824
|
| 3134 |
|
|
d=023140 -- ! mem(11000)
|
| 3135 |
|
|
d=000010 -- ! mem(11002) div 001520,142467, 171044 -> n1z0v0c0
|
| 3136 |
|
|
d=141303 -- ! mem(11004) 55625015/-3548 -> -15677,3019
|
| 3137 |
|
|
d=005713 -- ! mem(11006)
|
| 3138 |
|
|
d=000007 -- ! mem(11010) div 001520,142467,000000 -> n0z1v1c1
|
| 3139 |
|
|
d=001520 -- ! mem(11012) 55625015/0 -> V=1, keep regs
|
| 3140 |
|
|
d=142467 -- ! mem(11014)
|
| 3141 |
|
|
d=000004 -- ! mem(11016) div 000000,000000,021706 -> n0z1v1c0
|
| 3142 |
|
|
d=000000 -- ! mem(11020) 0/9158 -> 0,0
|
| 3143 |
|
|
d=000000 -- ! mem(11022)
|
| 3144 |
25 |
wfjm |
d=000010 -- ! mem(11024) div 177777,100000,000001->n1z0v1c0
|
| 3145 |
|
|
d=100000 -- ! mem(11026) -32768/1 -> -32768,0
|
| 3146 |
|
|
d=000000 -- ! mem(11030)
|
| 3147 |
2 |
wfjm |
d=000002 -- ! mem(11032) div 177777,100000,177777 -> n0z0v1c0 ?? 2
|
| 3148 |
|
|
d=177777 -- ! mem(11034) -32768/-1 -> overflow
|
| 3149 |
|
|
d=100000 -- ! mem(11036)
|
| 3150 |
|
|
d=000000 -- ! mem(11040) div 037777,077777,077777 -> n0z0v0c0
|
| 3151 |
|
|
d=077777 -- ! mem(11042) 1073709055/32767 -> 32767,32766
|
| 3152 |
|
|
d=077776 -- ! mem(11044)
|
| 3153 |
|
|
d=000002 -- ! mem(11046) div 037777,100000,077777 -> n0z0v1c0
|
| 3154 |
|
|
d=037777 -- ! mem(11050) 1073709056/32767 -> overflow
|
| 3155 |
|
|
d=100000 -- ! mem(11052)
|
| 3156 |
|
|
d=000010 -- ! mem(11054) div 140000,100001,077777 -> n1z0v0c0
|
| 3157 |
|
|
d=100001 -- ! mem(11056) -1073709055/32767 -> -32767,-32766
|
| 3158 |
|
|
d=100002 -- ! mem(11060)
|
| 3159 |
25 |
wfjm |
d=000010 -- ! mem(11062) div 140000,100000,077777->n1z0v1c0
|
| 3160 |
|
|
d=100000 -- ! mem(11064) -1073709056/32767 -> -32768,0
|
| 3161 |
|
|
d=000000 -- ! mem(11066)
|
| 3162 |
2 |
wfjm |
d=000002 -- ! mem(11070) div 040000,000000,077777 -> n0z0v1c0
|
| 3163 |
|
|
d=040000 -- ! mem(11072) 1073741824/32767 -> overflow
|
| 3164 |
|
|
d=000000 -- ! mem(11074)
|
| 3165 |
|
|
#
|
| 3166 |
|
|
# simh notes:
|
| 3167 |
|
|
# 1. a quotient of 100000 leads to an overflow (V=1) on the W11
|
| 3168 |
|
|
# simh will not indicate overflow and returns q=100000
|
| 3169 |
|
|
#
|
| 3170 |
|
|
#----
|
| 3171 |
|
|
C Exec test 31.2 (test mul after div)
|
| 3172 |
|
|
#
|
| 3173 |
|
|
wr0 010500 -- r0=10500 (input data from DIV)
|
| 3174 |
|
|
wr1 010700 -- r1=10700 (output data from DIV)
|
| 3175 |
|
|
wr5 000016 -- r5=16 (test count)
|
| 3176 |
|
|
wsp 001400 -- sp=1400
|
| 3177 |
30 |
wfjm |
cres
|
| 3178 |
2 |
wfjm |
stapc 010420 -- start @ 10420
|
| 3179 |
|
|
wtgo
|
| 3180 |
|
|
rr0 d=010624 -- ! r0
|
| 3181 |
|
|
rr1 d=011024 -- ! r1
|
| 3182 |
|
|
rr2 d=000000 -- ! r2
|
| 3183 |
|
|
rr3 d=000000 -- ! r3
|
| 3184 |
|
|
rr5 d=000000 -- ! r5
|
| 3185 |
|
|
rpc d=010500 -- ! pc
|
| 3186 |
|
|
#-----------------------------------------------------------------------------
|
| 3187 |
|
|
C Setup code 32 [base 11100; use 111-112] (PIRQ test)
|
| 3188 |
|
|
# The code will exercise all 7 pirq interrupt levels:
|
| 3189 |
|
|
# set 1+3 -> handle 3, set 7 -> handle 7, set 6+4 -> handle 6
|
| 3190 |
|
|
# -> handle 4, set 5+2 -> handle 5 -> handle 2 > handle 1
|
| 3191 |
|
|
#
|
| 3192 |
|
|
wal 011100 -- code:
|
| 3193 |
|
|
bwm 14
|
| 3194 |
|
|
000237 -- spl 7
|
| 3195 |
|
|
011425 -- mov (r4),(r5)+ ; save PSW
|
| 3196 |
|
|
012713 -- mov #1000,(r3) ; set PIRQ 1
|
| 3197 |
|
|
001000
|
| 3198 |
|
|
011325 -- mov (r3),(r5)+ ; save PIRQ
|
| 3199 |
|
|
112763 -- movb #12,1(r3) ; set PIRQ 1+3
|
| 3200 |
|
|
000012
|
| 3201 |
|
|
000001
|
| 3202 |
|
|
#11120
|
| 3203 |
|
|
011325 -- mov (r3),(r5)+ ; save PIRQ
|
| 3204 |
|
|
000232 -- spl 2 ; now pri=2
|
| 3205 |
|
|
000240 -- nop ; allow interrupt to happen
|
| 3206 |
|
|
000230 -- spl 0 ; now pri=0
|
| 3207 |
|
|
#11130
|
| 3208 |
|
|
000240 -- nop ; allow interrupt to happen
|
| 3209 |
|
|
000000 -- halt
|
| 3210 |
|
|
#-----
|
| 3211 |
|
|
wal 000240 -- vector: 240
|
| 3212 |
|
|
bwm 2
|
| 3213 |
|
|
011134 -- PC:11134
|
| 3214 |
|
|
000340 -- PS:pri=7
|
| 3215 |
|
|
#-----
|
| 3216 |
|
|
wal 011134 -- code: (vector 240)
|
| 3217 |
|
|
bwm 18
|
| 3218 |
|
|
011300 -- mov (r3),r0 ; get pirq
|
| 3219 |
|
|
010625 -- mov sp,(r5)+ ; save sp
|
| 3220 |
|
|
#11140
|
| 3221 |
|
|
010025 -- mov r0,(r5)+ ; save pirq
|
| 3222 |
|
|
110014 -- movb r0,(r4) ; PSW=PIRQ (sets priority)
|
| 3223 |
|
|
042700 -- bic #177761,r0 ; mask out index bits
|
| 3224 |
|
|
177761
|
| 3225 |
|
|
010001 -- mov r0,r1 ; r0 is word index (pri*2)
|
| 3226 |
|
|
006201 -- asr r1 ; r1 is byte index (pri*1)
|
| 3227 |
|
|
012702 -- mov #400,r2
|
| 3228 |
|
|
000400
|
| 3229 |
|
|
#11160
|
| 3230 |
|
|
072201 -- ash r1,r2 ; r2 = 1<<(pri)
|
| 3231 |
|
|
040213 -- bic r2,(r3) ; clear current level in pirq
|
| 3232 |
|
|
010246 -- mov r2,-(sp) ; save pirq level mask
|
| 3233 |
|
|
056013 -- bis 11200(r0),(r3) ; trigger new pirq's
|
| 3234 |
|
|
011200
|
| 3235 |
|
|
000240 -- noop
|
| 3236 |
|
|
012625 -- mov (sp)+,(r5)+ ; save pirq level mask
|
| 3237 |
|
|
000002 -- rti
|
| 3238 |
|
|
#11200
|
| 3239 |
|
|
#-----
|
| 3240 |
|
|
wal 011200 -- data:
|
| 3241 |
|
|
bwm 8
|
| 3242 |
|
|
000000 -- mem(11200)=0 ; new pirq @ level 0
|
| 3243 |
|
|
000000 -- mem(11202)=0 ; new pirq @ level 1
|
| 3244 |
|
|
000000 -- mem(11204)=0 ; new pirq @ level 2
|
| 3245 |
|
|
100000 -- mem(11206)=100000 ; new pirq @ level 3 -> 7
|
| 3246 |
|
|
022000 -- mem(11210)=022000 ; new pirq @ level 4 -> 5+2
|
| 3247 |
|
|
000000 -- mem(11212)=0 ; new pirq @ level 5
|
| 3248 |
|
|
000000 -- mem(11214)=0 ; new pirq @ level 6
|
| 3249 |
|
|
050000 -- mem(11216)=050000 ; new pirq @ level 7 -> 6+4
|
| 3250 |
|
|
#
|
| 3251 |
|
|
C Exec code 32 (PIRQ test)
|
| 3252 |
|
|
#
|
| 3253 |
|
|
wr3 177772 -- r3=177772 (#PIRQ)
|
| 3254 |
|
|
wr4 177776 -- r4=177776 (#PSW)
|
| 3255 |
|
|
wr5 011220 -- r1=11220 (output data)
|
| 3256 |
|
|
wsp 001400 -- sp=1400
|
| 3257 |
30 |
wfjm |
cres
|
| 3258 |
2 |
wfjm |
stapc 011100 -- start @ 11100
|
| 3259 |
|
|
wtgo
|
| 3260 |
|
|
rr5 d=011300 -- ! r5
|
| 3261 |
|
|
rsp d=001400 -- ! sp
|
| 3262 |
|
|
rpc d=011134 -- ! pc
|
| 3263 |
|
|
rps d=000000 -- ! PSW
|
| 3264 |
|
|
wal 177772 --
|
| 3265 |
|
|
rmi d=000000 -- ! PIRQ
|
| 3266 |
|
|
wal 011220 --
|
| 3267 |
|
|
brm 24
|
| 3268 |
|
|
d=000340 -- ! mem(11220) PSW after SPL 7
|
| 3269 |
|
|
d=001042 -- ! mem(11222) PIRQ when 1 set
|
| 3270 |
|
|
d=005146 -- ! mem(11224) PIRQ when 1+3 set
|
| 3271 |
|
|
d=001374 -- ! mem(11226) -> PI:3 SP
|
| 3272 |
|
|
d=005146 -- ! mem(11230) PIRQ (3+1 pending)
|
| 3273 |
|
|
d=001366 -- ! mem(11232) -> PI:7 SP
|
| 3274 |
|
|
d=101356 -- ! mem(11234) PIRQ (7+1 pending)
|
| 3275 |
|
|
d=100000 -- ! mem(11236) <- PI:7 mask
|
| 3276 |
|
|
d=001366 -- ! mem(11240) -> PI:6 SP
|
| 3277 |
|
|
d=051314 -- ! mem(11242) PIRQ (6+4+1 pending)
|
| 3278 |
|
|
d=040000 -- ! mem(11244) <- PI:6 mask
|
| 3279 |
|
|
d=001366 -- ! mem(11246) -> PI:4 SP
|
| 3280 |
|
|
d=011210 -- ! mem(11250) PIRQ (4+1 pending)
|
| 3281 |
|
|
d=001360 -- ! mem(11252) -> PI:5 SP
|
| 3282 |
|
|
d=023252 -- ! mem(11254) PIRQ (5+2+1 pending)
|
| 3283 |
|
|
d=020000 -- ! mem(11256) <- PI:5 mask
|
| 3284 |
|
|
d=010000 -- ! mem(11260) <- PI:4 mask
|
| 3285 |
|
|
d=004000 -- ! mem(11262) <- PI:3 mask
|
| 3286 |
|
|
d=001374 -- ! mem(11264) -> PI:2 SP
|
| 3287 |
|
|
d=003104 -- ! mem(11266) PIRQ
|
| 3288 |
|
|
d=002000 -- ! mem(11270) <- PI:2 mask
|
| 3289 |
|
|
d=001374 -- ! mem(11272) -> PI:1 SP
|
| 3290 |
|
|
d=001042 -- ! mem(11274) PIRQ
|
| 3291 |
|
|
d=001000 -- ! mem(11276) <- PI:1 mask
|
| 3292 |
|
|
#
|
| 3293 |
|
|
wal 000240 -- vector: 240 -> trap catcher again
|
| 3294 |
|
|
bwm 2
|
| 3295 |
|
|
000242 -- PC:242
|
| 3296 |
|
|
000000 -- PS:0
|
| 3297 |
|
|
#-----------------------------------------------------------------------------
|
| 3298 |
|
|
C Setup code 33 [base 11200; use 112-113] (adc(b) and sbc(b) test)
|
| 3299 |
|
|
#
|
| 3300 |
|
|
wal 011200 -- code test 1: (adc)
|
| 3301 |
|
|
bwm 5
|
| 3302 |
|
|
006020 -- L1: ror (r0)+
|
| 3303 |
|
|
005520 -- adc (r0)+
|
| 3304 |
|
|
006120 -- rol (r0)+
|
| 3305 |
|
|
077104 -- sob r1,L1 (.-4)
|
| 3306 |
|
|
000000 -- halt
|
| 3307 |
|
|
#-----
|
| 3308 |
|
|
wal 011220 -- code test 2: (sbc)
|
| 3309 |
|
|
bwm 5
|
| 3310 |
|
|
006020 -- L1: ror (r0)+
|
| 3311 |
|
|
005620 -- sbc (r0)+
|
| 3312 |
|
|
006120 -- rol (r0)+
|
| 3313 |
|
|
077104 -- sob r1,L1 (.-4)
|
| 3314 |
|
|
000000 -- halt
|
| 3315 |
|
|
#-----
|
| 3316 |
|
|
wal 011240 -- code test 3: (adcb)
|
| 3317 |
|
|
bwm 5
|
| 3318 |
|
|
006020 -- L1: ror (r0)+
|
| 3319 |
|
|
105520 -- adcb (r0)+
|
| 3320 |
|
|
106120 -- rolb (r0)+
|
| 3321 |
|
|
077104 -- sob r1,L1 (.-4)
|
| 3322 |
|
|
000000 -- halt
|
| 3323 |
|
|
#-----
|
| 3324 |
|
|
wal 011260 -- code test 4: (sbcb)
|
| 3325 |
|
|
bwm 5
|
| 3326 |
|
|
006020 -- L1: ror (r0)+
|
| 3327 |
|
|
105620 -- sbcb (r0)+
|
| 3328 |
|
|
106120 -- rolb (r0)+
|
| 3329 |
|
|
077104 -- sob r1,L1 (.-4)
|
| 3330 |
|
|
000000 -- halt
|
| 3331 |
|
|
#-----
|
| 3332 |
|
|
wal 011300 -- data test 1: (adc)
|
| 3333 |
|
|
bwm 9
|
| 3334 |
|
|
000000 -- 177776 + 0 -> 177776 + 0
|
| 3335 |
|
|
177776
|
| 3336 |
|
|
000000
|
| 3337 |
|
|
000001 -- 177776 + 1 -> 177777 + 0
|
| 3338 |
|
|
177776
|
| 3339 |
|
|
000000
|
| 3340 |
|
|
000001 -- 177777 + 1 -> 000000 + 1
|
| 3341 |
|
|
177777
|
| 3342 |
|
|
000000
|
| 3343 |
|
|
#-----
|
| 3344 |
|
|
wal 011324 -- data test 2: (sbc)
|
| 3345 |
|
|
bwm 9
|
| 3346 |
|
|
000000 -- 000002 - 0 -> 000002 - 0
|
| 3347 |
|
|
000002
|
| 3348 |
|
|
000000
|
| 3349 |
|
|
000001 -- 000002 - 1 -> 000001 - 0
|
| 3350 |
|
|
000002
|
| 3351 |
|
|
000000
|
| 3352 |
|
|
000001 -- 000000 - 1 -> 177777 - 1
|
| 3353 |
|
|
000000
|
| 3354 |
|
|
000000
|
| 3355 |
|
|
#-----
|
| 3356 |
|
|
wal 011350 -- data test 3: (adcb)
|
| 3357 |
|
|
bwm 6
|
| 3358 |
|
|
000000 -- 376 + 0 -> 376 + 0
|
| 3359 |
|
|
000376
|
| 3360 |
|
|
000001 -- 376 + 1 -> 377 + 0
|
| 3361 |
|
|
000376
|
| 3362 |
|
|
000001 -- 377 + 1 -> 000 + 1
|
| 3363 |
|
|
000377
|
| 3364 |
|
|
#-----
|
| 3365 |
|
|
wal 011364 -- data test 4: (sbcb)
|
| 3366 |
|
|
bwm 6
|
| 3367 |
|
|
000000 -- 002 - 0 -> 002 - 0
|
| 3368 |
|
|
000002
|
| 3369 |
|
|
000001 -- 002 - 1 -> 001 - 0
|
| 3370 |
|
|
000002
|
| 3371 |
|
|
000001 -- 000 - 1 -> 337 - 1
|
| 3372 |
|
|
000000
|
| 3373 |
|
|
#
|
| 3374 |
|
|
C Exec code 33 (adc and sbc test)
|
| 3375 |
|
|
C Exec test 33.1 (adc)
|
| 3376 |
|
|
#
|
| 3377 |
|
|
wr0 011300 -- r0=11300
|
| 3378 |
|
|
wr1 000003 -- r1=3
|
| 3379 |
|
|
wsp 001400 -- sp=1400
|
| 3380 |
30 |
wfjm |
cres
|
| 3381 |
2 |
wfjm |
stapc 011200 -- start @ 11200
|
| 3382 |
|
|
wtgo
|
| 3383 |
|
|
rr0 d=011322 -- ! r0=11322
|
| 3384 |
|
|
rpc d=011212 -- ! pc
|
| 3385 |
|
|
wal 011300
|
| 3386 |
|
|
brm 9
|
| 3387 |
|
|
d=000000 -- ! mem(11300)=000000 -- 177776 + 0 -> 177776 + 0
|
| 3388 |
|
|
d=177776 -- ! mem(11302)=000000
|
| 3389 |
|
|
d=000000 -- ! mem(11304)=000000
|
| 3390 |
|
|
d=000000 -- ! mem(11306)=000000 -- 177776 + 1 -> 177777 + 0
|
| 3391 |
|
|
d=177777 -- ! mem(11310)=000000
|
| 3392 |
|
|
d=000000 -- ! mem(11312)=000000
|
| 3393 |
|
|
d=000000 -- ! mem(11314)=000000 -- 177777 + 1 -> 000000 + 1
|
| 3394 |
|
|
d=000000 -- ! mem(11316)=000000
|
| 3395 |
|
|
d=000001 -- ! mem(11320)=000000
|
| 3396 |
|
|
#----
|
| 3397 |
|
|
C Exec test 33.2 (sbc)
|
| 3398 |
|
|
#
|
| 3399 |
|
|
wr0 011324 -- r0=11324
|
| 3400 |
|
|
wr1 000003 -- r1=3
|
| 3401 |
|
|
wsp 001400 -- sp=1400
|
| 3402 |
30 |
wfjm |
cres
|
| 3403 |
2 |
wfjm |
stapc 011220 -- start @ 11220
|
| 3404 |
|
|
wtgo
|
| 3405 |
|
|
rr0 d=011346 -- ! r0=11346
|
| 3406 |
|
|
rpc d=011232 -- ! pc
|
| 3407 |
|
|
wal 011324
|
| 3408 |
|
|
brm 9
|
| 3409 |
|
|
d=000000 -- ! mem(11324)=000000 -- 000002 - 0 -> 000002 - 0
|
| 3410 |
|
|
d=000002 -- ! mem(11326)=000000
|
| 3411 |
|
|
d=000000 -- ! mem(11330)=000000
|
| 3412 |
|
|
d=000000 -- ! mem(11332)=000000 -- 000002 - 1 -> 000001 - 0
|
| 3413 |
|
|
d=000001 -- ! mem(11334)=000000
|
| 3414 |
|
|
d=000000 -- ! mem(11336)=000000
|
| 3415 |
|
|
d=000000 -- ! mem(11340)=000000 -- 000000 - 1 -> 177777 - 1
|
| 3416 |
|
|
d=177777 -- ! mem(11342)=000000
|
| 3417 |
|
|
d=000001 -- ! mem(11344)=000000
|
| 3418 |
|
|
#----
|
| 3419 |
|
|
C Exec test 33.3 (adcb)
|
| 3420 |
|
|
#
|
| 3421 |
|
|
wr0 011350 -- r0=11350
|
| 3422 |
|
|
wr1 000003 -- r1=3
|
| 3423 |
|
|
wsp 001400 -- sp=1400
|
| 3424 |
30 |
wfjm |
cres
|
| 3425 |
2 |
wfjm |
stapc 011240 -- start @ 11240
|
| 3426 |
|
|
wtgo
|
| 3427 |
|
|
rr0 d=011364 -- ! r0=11364
|
| 3428 |
|
|
rpc d=011252 -- ! pc
|
| 3429 |
|
|
wal 011350
|
| 3430 |
|
|
brm 6
|
| 3431 |
|
|
d=000000 -- ! mem(11350)=000000 -- 376 + 0 -> 376 + 0
|
| 3432 |
|
|
d=000376 -- ! mem(11352)=000000
|
| 3433 |
|
|
d=000000 -- ! mem(11354)=000000 -- 376 + 1 -> 377 + 0
|
| 3434 |
|
|
d=000377 -- ! mem(11356)=000000
|
| 3435 |
|
|
d=000000 -- ! mem(11360)=000000 -- 377 + 1 -> 000 + 1
|
| 3436 |
|
|
d=000400 -- ! mem(11362)=000000
|
| 3437 |
|
|
#----
|
| 3438 |
|
|
C Exec test 33.4 (sbcb)
|
| 3439 |
|
|
#
|
| 3440 |
|
|
wr0 011364 -- r0=11364
|
| 3441 |
|
|
wr1 000003 -- r1=3
|
| 3442 |
|
|
wsp 001400 -- sp=1400
|
| 3443 |
30 |
wfjm |
cres
|
| 3444 |
2 |
wfjm |
stapc 011260 -- start @ 11260
|
| 3445 |
|
|
wtgo
|
| 3446 |
|
|
rr0 d=011400 -- ! r0=11400
|
| 3447 |
|
|
rpc d=011272 -- ! pc
|
| 3448 |
|
|
wal 011364
|
| 3449 |
|
|
brm 6
|
| 3450 |
|
|
d=000000 -- ! mem(11364)=000000 -- 002 - 0 -> 002 - 0
|
| 3451 |
|
|
d=000002 -- ! mem(11366)=000000
|
| 3452 |
|
|
d=000000 -- ! mem(11370)=000000 -- 002 - 1 -> 001 - 0
|
| 3453 |
|
|
d=000001 -- ! mem(11372)=000000
|
| 3454 |
|
|
d=000000 -- ! mem(11374)=000000 -- 000 - 1 -> 337 - 1
|
| 3455 |
|
|
d=000777 -- ! mem(11377)=000000
|
| 3456 |
|
|
#-----------------------------------------------------------------------------
|
| 3457 |
|
|
C Setup code 34 [base 11400; use 114-115] (11/34 self test code)
|
| 3458 |
|
|
# code adapted from M9312 23-248F1 console PROM, the 11/04-34 Diagnostic PROM
|
| 3459 |
|
|
#
|
| 3460 |
|
|
wal 011400 -- code:
|
| 3461 |
|
|
bwm 51
|
| 3462 |
|
|
005000 -- clr r0 ; r0=000000 c=0
|
| 3463 |
|
|
005200 -- inc r0 ; r0=000001 c=0
|
| 3464 |
|
|
005100 -- com r0 ; r0=177776 c=1
|
| 3465 |
|
|
006200 -- asr r0 ; r0=177777 c=0
|
| 3466 |
|
|
006300 -- asl r0 ; r0=177776 c=1
|
| 3467 |
|
|
006000 -- ror r0 ; r0=177777 c=0
|
| 3468 |
|
|
005700 -- tst r0 ; r0=177777 c=0 ?impact unclear?
|
| 3469 |
|
|
005400 -- neg r0 ; r0=000001 c=1
|
| 3470 |
|
|
#11420
|
| 3471 |
|
|
005300 -- dec r0 ; r0=000000 c=1
|
| 3472 |
|
|
005600 -- sbc r0 ; r0=177777 c=1
|
| 3473 |
|
|
006100 -- rol r0 ; r0=177777 c=1
|
| 3474 |
|
|
005500 -- adc r0 ; r0=000000 c=1
|
| 3475 |
|
|
000300 -- swab r0 ; r0=000000 c=0
|
| 3476 |
|
|
001401 -- beq .+1 ;
|
| 3477 |
|
|
000000 -- halt ;
|
| 3478 |
|
|
012702 -- mov #data0,r2 ; r2=011560
|
| 3479 |
|
|
#11440
|
| 3480 |
|
|
011560
|
| 3481 |
|
|
011203 -- mov (r2),r3 ; r2=011560 r3=011560
|
| 3482 |
|
|
022203 -- cmp (r2)+,r3 ; r2=011562 r3=011560
|
| 3483 |
|
|
001401 -- beq .+1 ;
|
| 3484 |
|
|
000000 -- halt ;
|
| 3485 |
|
|
063203 -- add @(r2)+,r3 ; r2=011564 r3=<2*11560>
|
| 3486 |
|
|
165203 -- sub @-(r2),r3 ; r2=011562 r3=011560
|
| 3487 |
|
|
044203 -- bic -(r2),r3 ; r2=011560 r3=000000
|
| 3488 |
|
|
#11460
|
| 3489 |
|
|
056203 -- bis 12(r2),r3 ; r2=011560 r3=011566
|
| 3490 |
|
|
000012
|
| 3491 |
|
|
037203 -- bis @12(r2),r3 ; r2=011560 r3=011566
|
| 3492 |
|
|
000012
|
| 3493 |
|
|
001001 -- bne .+1 ;
|
| 3494 |
|
|
000000 -- halt ;
|
| 3495 |
|
|
010701 -- mov pc,r1 ; r1=011476
|
| 3496 |
|
|
000121 -- jmp (r1)+ ; jump 1.self 2. next; r1=011500
|
| 3497 |
|
|
#11500
|
| 3498 |
|
|
012701 -- mov #L2,r1 ; r1=011510
|
| 3499 |
|
|
011510
|
| 3500 |
|
|
000131 -- jmp @(r1)+ ; r1=011512 pc=011506
|
| 3501 |
|
|
000111 -- L1:jmp (r1) ; r1=011512 pc=011512
|
| 3502 |
|
|
011506 -- L2:.word L1
|
| 3503 |
|
|
105737 -- tstb data1 ;
|
| 3504 |
|
|
011564
|
| 3505 |
|
|
001401 -- beq .+1 ;
|
| 3506 |
|
|
#11520
|
| 3507 |
|
|
000000 -- halt ;
|
| 3508 |
|
|
010204 -- mov r2,r4 ; keep r2 for later check
|
| 3509 |
|
|
022424 -- cmp (r4)+,(r4)+ ; r4=011564
|
| 3510 |
|
|
105724 -- tstb (r4)+ ; r4=011565 (r4)+=000
|
| 3511 |
|
|
001401 -- beq .+1 ;
|
| 3512 |
|
|
000000 -- halt ;
|
| 3513 |
|
|
105714 -- tstb (r4) ; r4=011565 (r4)=200
|
| 3514 |
|
|
100402 -- bmi .+2 ;
|
| 3515 |
|
|
#11540
|
| 3516 |
|
|
000000 -- halt ;
|
| 3517 |
|
|
000000 -- halt ;
|
| 3518 |
|
|
000000 -- halt ;
|
| 3519 |
|
|
#-----
|
| 3520 |
|
|
wal 011560 -- data:
|
| 3521 |
|
|
bwm 8
|
| 3522 |
|
|
011560 -- data0: .word data0
|
| 3523 |
|
|
011560 -- .word data0
|
| 3524 |
|
|
100000 -- data1: .byte 000,200
|
| 3525 |
|
|
177777 -- data2: .word 177777
|
| 3526 |
|
|
011566 -- .word data2
|
| 3527 |
|
|
011566 -- .word data2
|
| 3528 |
|
|
000700 -- .word mem+0
|
| 3529 |
|
|
000701 -- .word mem+1
|
| 3530 |
|
|
#
|
| 3531 |
|
|
C Exec code 34 (11/34 self test code)
|
| 3532 |
|
|
# D RE RQ FU DAT
|
| 3533 |
30 |
wfjm |
cres
|
| 3534 |
2 |
wfjm |
stapc 011400 -- start @ 11400
|
| 3535 |
|
|
wtgo
|
| 3536 |
|
|
rr0 d=000000 -- ! r0
|
| 3537 |
|
|
rr1 d=011512 -- ! r1
|
| 3538 |
|
|
rr2 d=011560 -- ! r2
|
| 3539 |
|
|
rr3 d=011566 -- ! r3
|
| 3540 |
|
|
rr4 d=011565 -- ! r4
|
| 3541 |
|
|
rpc d=011546 -- ! pc
|
| 3542 |
|
|
#-----------------------------------------------------------------------------
|
| 3543 |
|
|
C Setup code 35 [base 11600; use 116-121] (11/70 self test code)
|
| 3544 |
|
|
# code adapted from M9312 23-616F1 console PROM, the 11/60-70 Diagnostic PROM
|
| 3545 |
|
|
#
|
| 3546 |
|
|
wal 011600 -- code:
|
| 3547 |
|
|
bwm 117
|
| 3548 |
|
|
005006 -- clr sp ; sp=000000
|
| 3549 |
|
|
100404 -- bmi L3 ;
|
| 3550 |
|
|
102403 -- bvs L3 ;
|
| 3551 |
|
|
101002 -- bhi L3 ;
|
| 3552 |
|
|
002401 -- blt L3 ;
|
| 3553 |
|
|
101401 -- blos L4 ;
|
| 3554 |
|
|
000000 -- L3: halt ;
|
| 3555 |
|
|
005306 -- L3: dec sp ; sp=177777
|
| 3556 |
|
|
#11620
|
| 3557 |
|
|
100003 -- bpl L5 ;
|
| 3558 |
|
|
001402 -- beq L5 ;
|
| 3559 |
|
|
002001 -- bge L5 ;
|
| 3560 |
|
|
003401 -- ble L6 ;
|
| 3561 |
|
|
000000 -- L5: halt ;
|
| 3562 |
|
|
006006 -- L6: ror sp ; sp=077777
|
| 3563 |
|
|
102002 -- bvc L7 ;
|
| 3564 |
|
|
103001 -- bcc L7 ;
|
| 3565 |
|
|
#11640
|
| 3566 |
|
|
001001 -- bne L8 ;
|
| 3567 |
|
|
000000 -- L7: halt ;
|
| 3568 |
|
|
012706 -- L8: mov #125252,sp ; sp=125252
|
| 3569 |
|
|
125252
|
| 3570 |
|
|
010600 -- mov sp,r0 ;
|
| 3571 |
|
|
010001 -- mov r0,r1 ;
|
| 3572 |
|
|
010102 -- mov r1,r2 ;
|
| 3573 |
|
|
010203 -- mov r2,r3 ;
|
| 3574 |
|
|
#11660
|
| 3575 |
|
|
010304 -- mov r3,r4 ;
|
| 3576 |
|
|
010405 -- mov r4,r5 ;
|
| 3577 |
|
|
160501 -- sub r5,r1 ; r1=00000
|
| 3578 |
|
|
002401 -- blt L9a ;
|
| 3579 |
|
|
001401 -- beq L9 ;
|
| 3580 |
|
|
000000 -- L9a: halt ;
|
| 3581 |
|
|
006102 -- L9: rol r2 ; r2=052524 c=1
|
| 3582 |
|
|
103001 -- bcc L10 ;
|
| 3583 |
|
|
#11700
|
| 3584 |
|
|
002401 -- blt L11 ;
|
| 3585 |
|
|
000000 -- L10: halt ;
|
| 3586 |
|
|
060203 -- L11: add r2,r3 ; r3=177776 (125252+052524)
|
| 3587 |
|
|
005203 -- inc r3 ; r3=177777
|
| 3588 |
|
|
005103 -- com r3 ; r3=000000
|
| 3589 |
|
|
060301 -- add r3,r1 ; r1=000000 c=0
|
| 3590 |
|
|
103401 -- bcs L12 ;
|
| 3591 |
|
|
003401 -- ble L13 ;
|
| 3592 |
|
|
#11720
|
| 3593 |
|
|
000000 -- L12: halt ;
|
| 3594 |
|
|
006004 -- L13: ror r4 ; r4=052525
|
| 3595 |
|
|
050403 -- bis r4,r3 ; r3=052525 (r3 was 0)
|
| 3596 |
|
|
060503 -- add r5,r3 ; r3=177777 c=0 (125252+052525)
|
| 3597 |
|
|
005203 -- inc r3 ; r3=000000 c=0 (kept)
|
| 3598 |
|
|
103402 -- bcs L14 ;
|
| 3599 |
|
|
005301 -- dec r1 ; r1=177777
|
| 3600 |
|
|
002401 -- blt L15 ;
|
| 3601 |
|
|
#11740
|
| 3602 |
|
|
000000 -- L14: halt ;
|
| 3603 |
|
|
005100 -- L15: com r0 ; r0=052525
|
| 3604 |
|
|
101401 -- blos L16 ;
|
| 3605 |
|
|
000000 -- halt ;
|
| 3606 |
|
|
040001 -- L16: bic r0,r1 ; r1=125252
|
| 3607 |
|
|
060101 -- L16: add r1,r1 ; r1=052524 c=1
|
| 3608 |
|
|
003001 -- bgt L17 ;
|
| 3609 |
|
|
003401 -- ble L18 ;
|
| 3610 |
|
|
#11760
|
| 3611 |
|
|
000000 -- L17: halt ;
|
| 3612 |
|
|
000301 -- L18: swab r1 ; r1=052125
|
| 3613 |
|
|
020127 -- cmp r1,#052125 ;
|
| 3614 |
|
|
052125
|
| 3615 |
|
|
001004 -- bne L19 ;
|
| 3616 |
|
|
030405 -- bit r4,r5 ;
|
| 3617 |
|
|
003002 -- bgt L19 ;
|
| 3618 |
|
|
005105 -- com r5 ; r5=052525
|
| 3619 |
|
|
#12000
|
| 3620 |
|
|
001001 -- bne L20 ;
|
| 3621 |
|
|
000000 -- L19: halt ;
|
| 3622 |
|
|
112700 -- L20: movb #177401,r0 ;
|
| 3623 |
|
|
177401
|
| 3624 |
|
|
100001 -- bpl L21 ;
|
| 3625 |
|
|
000000 -- L22: halt ;
|
| 3626 |
|
|
077002 -- L21: sob r0,L22 ;
|
| 3627 |
|
|
000261 -- sec ; c=1
|
| 3628 |
|
|
#12020
|
| 3629 |
|
|
006100 -- rol r0 ; r0=000001
|
| 3630 |
|
|
006100 -- rol r0 ; r0=000002
|
| 3631 |
|
|
006100 -- rol r0 ; r0=000004
|
| 3632 |
|
|
010001 -- mov r0,r1 ; r1=000004
|
| 3633 |
|
|
005401 -- neg r1 ; r1=177774
|
| 3634 |
|
|
005201 -- L23: inc r1 ;
|
| 3635 |
|
|
077002 -- sob r0,L23 ;
|
| 3636 |
|
|
005700 -- tst r0 ; here r0=r1=0
|
| 3637 |
|
|
#12040
|
| 3638 |
|
|
001002 -- bne L24 ;
|
| 3639 |
|
|
005701 -- tst r1 ;
|
| 3640 |
|
|
001401 -- beq L25 ;
|
| 3641 |
|
|
000000 -- L24: halt ;
|
| 3642 |
|
|
012706 -- L25: mov #776,sp ;
|
| 3643 |
|
|
000776 --
|
| 3644 |
|
|
004767 -- jsr pc,L26 ;
|
| 3645 |
|
|
000002
|
| 3646 |
|
|
#12060
|
| 3647 |
|
|
000000 -- N2: halt ;
|
| 3648 |
|
|
022716 -- L26: cmp #N2,(sp) ;
|
| 3649 |
|
|
012060
|
| 3650 |
|
|
001401 -- beq L27 ;
|
| 3651 |
|
|
000000 -- halt ;
|
| 3652 |
|
|
012716 -- L27: mov #N3,(sp) ;
|
| 3653 |
|
|
012102
|
| 3654 |
|
|
000207 -- rts pc ;
|
| 3655 |
|
|
#12100
|
| 3656 |
|
|
000000 -- halt ;
|
| 3657 |
|
|
005046 -- N3: clr -(sp) ;
|
| 3658 |
|
|
012746 -- mov #N4,-(sp) ;
|
| 3659 |
|
|
012114
|
| 3660 |
|
|
000002 -- rti ;
|
| 3661 |
|
|
000000 -- halt ;
|
| 3662 |
|
|
000137 -- N4: jmp @#N5 ;
|
| 3663 |
|
|
012122
|
| 3664 |
|
|
#12120
|
| 3665 |
|
|
000000 -- halt ;
|
| 3666 |
|
|
012705 -- N5: mov #160000,r5 ; r5=160000
|
| 3667 |
|
|
160000
|
| 3668 |
|
|
005037 -- clr @#6 ;
|
| 3669 |
|
|
000006
|
| 3670 |
|
|
012737 -- mov #N6,@#4 ;
|
| 3671 |
|
|
012150
|
| 3672 |
|
|
000004
|
| 3673 |
|
|
#12140
|
| 3674 |
|
|
012706 -- mov #776,sp ; sp=776
|
| 3675 |
|
|
000776
|
| 3676 |
|
|
005715 -- tst (r5) ; will fail, first word of I/O page
|
| 3677 |
|
|
000000 -- halt ;
|
| 3678 |
|
|
000000 -- N6: halt ;
|
| 3679 |
|
|
#
|
| 3680 |
|
|
C Exec code 35 (11/70 self test code)
|
| 3681 |
|
|
# D RE RQ FU DAT
|
| 3682 |
30 |
wfjm |
cres
|
| 3683 |
2 |
wfjm |
stapc 011600 -- start @ 11600
|
| 3684 |
|
|
wtgo
|
| 3685 |
|
|
rpc d=012152 -- ! pc
|
| 3686 |
|
|
wal 000004 -- vector: 4 -> trap catcher again
|
| 3687 |
|
|
bwm 2
|
| 3688 |
|
|
000006 -- PC:6
|
| 3689 |
|
|
000000 -- PS:0
|
| 3690 |
|
|
#-----------------------------------------------------------------------------
|
| 3691 |
|
|
# Up to here code and data (both input and result) occupied 'fresh' memory.
|
| 3692 |
|
|
# Easy to debug, but inconvenient when test should be extended later.
|
| 3693 |
|
|
# From here on, only code will always occupy fresh memory.
|
| 3694 |
|
|
# Data will be put into the upper part of the 16 kbyte memory:
|
| 3695 |
|
|
# test vector: 036000 (512 byte area)
|
| 3696 |
|
|
# result data: 037000 (512 byte area)
|
| 3697 |
|
|
#-----------------------------------------------------------------------------
|
| 3698 |
|
|
C Setup code 36 [base 12200] (systematic CMP test)
|
| 3699 |
|
|
#
|
| 3700 |
|
|
wal 012200 -- code:
|
| 3701 |
|
|
bwm 7
|
| 3702 |
|
|
000230 -- spl 0
|
| 3703 |
|
|
012400 -- L1: mov (r4)+,r0
|
| 3704 |
|
|
012401 -- mov (r4)+,r1
|
| 3705 |
|
|
020001 -- cmp r0,r1
|
| 3706 |
|
|
011225 -- mov (r2),(r5)+
|
| 3707 |
|
|
077305 -- sob r3,L1
|
| 3708 |
|
|
000000 -- halt
|
| 3709 |
|
|
#
|
| 3710 |
|
|
C Exec code 36 (systematic CMP test)
|
| 3711 |
|
|
C Exec test 36.1: data adapted from cmp.s11 code of Begemot p11-2.10c
|
| 3712 |
|
|
#
|
| 3713 |
|
|
wal 036000 -- setup test vector:
|
| 3714 |
|
|
bwm 22
|
| 3715 |
|
|
000000 -- 000000, 000000 --> nzvc=0100
|
| 3716 |
|
|
000000 --
|
| 3717 |
|
|
000001 -- 000001, 000001 --> nzvc=0100
|
| 3718 |
|
|
000001 --
|
| 3719 |
|
|
177777 -- 177777, 177777 --> nzvc=0100
|
| 3720 |
|
|
177777 --
|
| 3721 |
|
|
000000 -- 000000, 000001 --> nzvc=1001
|
| 3722 |
|
|
000001 --
|
| 3723 |
|
|
000000 -- 000000, 177777 --> nzvc=0001
|
| 3724 |
|
|
177777 --
|
| 3725 |
|
|
000001 -- 000001, 000000 --> nzvc=0000
|
| 3726 |
|
|
000000 --
|
| 3727 |
|
|
177777 -- 177777, 000000 --> nzvc=1000
|
| 3728 |
|
|
000000 --
|
| 3729 |
|
|
000001 -- 000001, 177777 --> nzvc=0001
|
| 3730 |
|
|
177777 --
|
| 3731 |
|
|
177777 -- 177777, 000001 --> nzvc=1000
|
| 3732 |
|
|
000001 --
|
| 3733 |
|
|
077777 -- 077777, 100000 --> nzvc=1011
|
| 3734 |
|
|
100000 --
|
| 3735 |
|
|
100000 -- 100000, 077777 --> nzvc=0010
|
| 3736 |
|
|
077777 --
|
| 3737 |
|
|
#----
|
| 3738 |
|
|
wr2 177776 -- r2=177776 -> psw
|
| 3739 |
|
|
wr3 000013 -- r3=13 -> test count
|
| 3740 |
|
|
wr4 036000 -- r4=36000 -> input area
|
| 3741 |
|
|
wr5 037000 -- r5=37000 -> output area
|
| 3742 |
|
|
wsp 001400 -- sp=1400
|
| 3743 |
30 |
wfjm |
cres
|
| 3744 |
2 |
wfjm |
stapc 012200 -- start @ 12200
|
| 3745 |
|
|
wtgo
|
| 3746 |
|
|
rpc d=012216 -- ! pc
|
| 3747 |
|
|
rr3 d=000000 -- ! r3=0
|
| 3748 |
|
|
rr4 d=036054 -- ! r4=12354
|
| 3749 |
|
|
rr5 d=037026 -- ! r5=12426
|
| 3750 |
|
|
wal 037000 --
|
| 3751 |
|
|
brm 11
|
| 3752 |
|
|
d=000004 -- 000000, 000000 --> nzvc=0100
|
| 3753 |
|
|
d=000004 -- 000001, 000001 --> nzvc=0100
|
| 3754 |
|
|
d=000004 -- 177777, 177777 --> nzvc=0100
|
| 3755 |
|
|
d=000011 -- 000000, 000001 --> nzvc=1001
|
| 3756 |
|
|
d=000001 -- 000000, 177777 --> nzvc=0001
|
| 3757 |
|
|
d=000000 -- 000001, 000000 --> nzvc=0000
|
| 3758 |
|
|
d=000010 -- 177777, 000000 --> nzvc=1000
|
| 3759 |
|
|
d=000001 -- 000001, 177777 --> nzvc=0001
|
| 3760 |
|
|
d=000010 -- 177777, 000001 --> nzvc=1000
|
| 3761 |
|
|
d=000013 -- 077777, 100000 --> nzvc=1011
|
| 3762 |
|
|
d=000002 -- 100000, 077777 --> nzvc=0010
|
| 3763 |
|
|
#-----------------------------------------------------------------------------
|
| 3764 |
|
|
C Setup code 37 [base 12300] (systematic DIV test)
|
| 3765 |
|
|
#
|
| 3766 |
|
|
wal 012300 -- code:
|
| 3767 |
|
|
bwm 9
|
| 3768 |
|
|
000230 -- spl 0
|
| 3769 |
|
|
012400 -- L1: mov (r4)+,r0
|
| 3770 |
|
|
012401 -- mov (r4)+,r1
|
| 3771 |
|
|
071024 -- div (r4)+,r0
|
| 3772 |
|
|
011225 -- mov (r2),(r5)+
|
| 3773 |
|
|
010025 -- mov r0,(r5)+
|
| 3774 |
|
|
010125 -- mov r1,(r5)+
|
| 3775 |
|
|
077307 -- sob r3,L1
|
| 3776 |
|
|
#12520
|
| 3777 |
|
|
000000 -- halt
|
| 3778 |
|
|
#
|
| 3779 |
|
|
C Exec code 37 (systematic DIV test)
|
| 3780 |
|
|
C Exec test 37.1: data adapted from div.s11 code of Begemot p11-2.10c
|
| 3781 |
|
|
#
|
| 3782 |
|
|
wal 036000 -- setup test vector:
|
| 3783 |
|
|
bwm 57
|
| 3784 |
|
|
000000 -- 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
|
| 3785 |
|
|
000004 --
|
| 3786 |
|
|
000000 --
|
| 3787 |
|
|
000000 -- 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
|
| 3788 |
|
|
000004 --
|
| 3789 |
|
|
000002 --
|
| 3790 |
|
|
000000 -- 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
|
| 3791 |
|
|
000006 --
|
| 3792 |
|
|
000002 --
|
| 3793 |
|
|
000000 -- 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
|
| 3794 |
|
|
000004 --
|
| 3795 |
|
|
177776 --
|
| 3796 |
|
|
#36030
|
| 3797 |
|
|
000002 -- 2, 0, 1, 2, 2, 0# 0x20000 / 1
|
| 3798 |
|
|
000000 --
|
| 3799 |
|
|
000001 --
|
| 3800 |
|
|
000002 -- 2, 0, -2, 12, 2, 0# 0x20000 / -2
|
| 3801 |
|
|
000000 --
|
| 3802 |
|
|
177776 --
|
| 3803 |
|
|
100000 -- 100000, 0, 1, 12,100000, 0# 0x80000000 / 1
|
| 3804 |
|
|
000000 --
|
| 3805 |
|
|
000001 --
|
| 3806 |
|
|
177776 -- 177776,177777, -1, 2,177776,177777# -0x10001 / -1
|
| 3807 |
|
|
177777 --
|
| 3808 |
|
|
177777 --
|
| 3809 |
|
|
#36060
|
| 3810 |
|
|
177777 -- 177777,177773, 2, 10, -2, -1# -5 / 2
|
| 3811 |
|
|
177773 --
|
| 3812 |
|
|
000002 --
|
| 3813 |
|
|
177777 -- 177777,177773, -2, 0, 2, -1# -5 / -2
|
| 3814 |
|
|
177773 --
|
| 3815 |
|
|
177776 --
|
| 3816 |
|
|
177776 -- 177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
|
| 3817 |
|
|
000000 --
|
| 3818 |
|
|
040000 --
|
| 3819 |
|
|
000100 -- 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
|
| 3820 |
|
|
000200 --
|
| 3821 |
|
|
177601 --
|
| 3822 |
|
|
#36110
|
| 3823 |
|
|
000000 -- 0, 1, 0, 7, 0, 1 # zero divide
|
| 3824 |
|
|
000001 --
|
| 3825 |
|
|
000000 --
|
| 3826 |
|
|
177777 -- -1, -1, 0, 7, -1, -1 # zero divide
|
| 3827 |
|
|
177777 --
|
| 3828 |
|
|
000000 --
|
| 3829 |
|
|
000000 -- 0, 0, 0, 7, 0, 0 # zero divide
|
| 3830 |
|
|
000000 --
|
| 3831 |
|
|
000000 --
|
| 3832 |
|
|
000001 -- 1, 1, 1, 2, 1, 1 # overflow
|
| 3833 |
|
|
000001 --
|
| 3834 |
|
|
000001 --
|
| 3835 |
|
|
#36140
|
| 3836 |
|
|
000001 -- 1, 1, -1, 012, 1, 1 # overflow
|
| 3837 |
|
|
000001 --
|
| 3838 |
|
|
177777 --
|
| 3839 |
|
|
177777 -- -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
|
| 3840 |
|
|
177777 --
|
| 3841 |
|
|
000001 --
|
| 3842 |
|
|
177777 -- -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
|
| 3843 |
|
|
177777 --
|
| 3844 |
|
|
177777 --
|
| 3845 |
|
|
#----
|
| 3846 |
|
|
wr2 177776 -- r2=177776 -> psw
|
| 3847 |
|
|
wr3 000023 -- r3=23 -> test count
|
| 3848 |
|
|
wr4 036000 -- r4=36000 -> input area
|
| 3849 |
|
|
wr5 037000 -- r5=37000 -> output area
|
| 3850 |
|
|
wsp 001400 -- sp=1400
|
| 3851 |
30 |
wfjm |
cres
|
| 3852 |
2 |
wfjm |
stapc 012300 -- start @ 12300
|
| 3853 |
|
|
wtgo
|
| 3854 |
|
|
rpc d=012322 -- ! pc
|
| 3855 |
|
|
rr3 d=000000 -- ! r3=0
|
| 3856 |
|
|
rr4 d=036162 -- ! r4=36162
|
| 3857 |
|
|
rr5 d=037162 -- ! r5=37162
|
| 3858 |
|
|
wal 037000 --
|
| 3859 |
|
|
brm 57
|
| 3860 |
|
|
d=000007 --! 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
|
| 3861 |
|
|
d=000000 --!
|
| 3862 |
|
|
d=000004 --!
|
| 3863 |
|
|
d=000000 --! 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
|
| 3864 |
|
|
d=000002 --!
|
| 3865 |
|
|
d=000000 --!
|
| 3866 |
|
|
d=000000 --! 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
|
| 3867 |
|
|
d=000003 --!
|
| 3868 |
|
|
d=000000 --!
|
| 3869 |
|
|
d=000010 --! 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
|
| 3870 |
|
|
d=177776 --!
|
| 3871 |
|
|
d=000000 --!
|
| 3872 |
|
|
#37030
|
| 3873 |
|
|
d=000002 --! 2, 0, 1, 2, 2, 0# 0x20000 / 1
|
| 3874 |
|
|
d=000002 --!
|
| 3875 |
|
|
d=000000 --!
|
| 3876 |
|
|
d=000012 --! 2, 0, -2, 12, 2, 0# 0x20000 / -2
|
| 3877 |
|
|
d=000002 --!
|
| 3878 |
|
|
d=000000 --!
|
| 3879 |
|
|
d=000012 --!100000, 0, 1, 12,100000, 0# 0x80000000 / 1
|
| 3880 |
|
|
d=100000 --!
|
| 3881 |
|
|
d=000000 --!
|
| 3882 |
|
|
d=000002 --!177776,177777, -1, 2,177776,177777# -0x10001 / -1
|
| 3883 |
|
|
d=177776 --!
|
| 3884 |
|
|
d=177777 --!
|
| 3885 |
|
|
#37060
|
| 3886 |
|
|
d=000010 --!177777,177773, 2, 10, -2, -1# -5 / 2
|
| 3887 |
|
|
d=177776 --!
|
| 3888 |
|
|
d=177777 --!
|
| 3889 |
|
|
d=000000 --!177777,177773, -2, 0, 2, -1# -5 / -2
|
| 3890 |
|
|
d=000002 --!
|
| 3891 |
|
|
d=177777 --!
|
| 3892 |
|
|
d=000010 --!177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
|
| 3893 |
|
|
d=177770 --!
|
| 3894 |
|
|
d=000000 --!
|
| 3895 |
|
|
d=000012 --! 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
|
| 3896 |
|
|
d=000100 --!
|
| 3897 |
|
|
d=000200 --!
|
| 3898 |
|
|
#37110
|
| 3899 |
|
|
d=000007 --! 0, 1, 0, 7, 0, 1 # zero divide
|
| 3900 |
|
|
d=000000 --!
|
| 3901 |
|
|
d=000001 --!
|
| 3902 |
|
|
d=000007 --! -1, -1, 0, 7, -1, -1 # zero divide
|
| 3903 |
|
|
d=177777 --!
|
| 3904 |
|
|
d=177777 --!
|
| 3905 |
|
|
d=000007 --! 0, 0, 0, 7, 0, 0 # zero divide
|
| 3906 |
|
|
d=000000 --!
|
| 3907 |
|
|
d=000000 --!
|
| 3908 |
|
|
d=000002 --! 1, 1, 1, 2, 1, 1 # overflow
|
| 3909 |
|
|
d=000001 --!
|
| 3910 |
|
|
d=000001 --!
|
| 3911 |
|
|
#13740
|
| 3912 |
|
|
d=000012 --! 1, 1, -1, 012, 1, 1 # overflow
|
| 3913 |
|
|
d=000001 --!
|
| 3914 |
|
|
d=000001 --!
|
| 3915 |
|
|
d=000010 --! -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
|
| 3916 |
|
|
d=177777 --!
|
| 3917 |
|
|
d=000000 --!
|
| 3918 |
|
|
d=000000 --! -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
|
| 3919 |
|
|
d=000001 --!
|
| 3920 |
|
|
d=000000 --!
|
| 3921 |
|
|
#--------
|
| 3922 |
|
|
C Exec test 37.2: data adapted from KDJ11.MAC, test 213, p. 139-141
|
| 3923 |
|
|
# D RE RQ FU DAT
|
| 3924 |
|
|
wal 036000 -- setup test vector:
|
| 3925 |
|
|
bwm 51
|
| 3926 |
|
|
177777 -- 177777,177777,177777, 0, 1, 0#
|
| 3927 |
|
|
177777 --
|
| 3928 |
|
|
177777 --
|
| 3929 |
25 |
wfjm |
000000 -- 0,177777,177777,12, 0,177777# w11a:12,000001,000000
|
| 3930 |
2 |
wfjm |
177777 --
|
| 3931 |
|
|
177777 --
|
| 3932 |
|
|
177777 -- 177777, 0,177777, 2,177777, 0#
|
| 3933 |
|
|
000000 --
|
| 3934 |
|
|
177777 --
|
| 3935 |
|
|
000000 -- 0, 7642, 7643, 4, 0, 7642#
|
| 3936 |
|
|
007642 --
|
| 3937 |
|
|
007643 --
|
| 3938 |
|
|
000000 -- 0, 137,177543, 4, 0, 137#
|
| 3939 |
|
|
000137 --
|
| 3940 |
|
|
177543 --
|
| 3941 |
|
|
000000 -- 0, 7643, 7643, 0, 1, 0#
|
| 3942 |
|
|
007643 --
|
| 3943 |
|
|
007643 --
|
| 3944 |
|
|
100000 -- 100000, 4376, 10021,12,100000, 4376#
|
| 3945 |
|
|
004376 --
|
| 3946 |
|
|
010021 --
|
| 3947 |
|
|
177700 -- 177700,170033, 10021,10,176024,171307#
|
| 3948 |
|
|
170033 --
|
| 3949 |
|
|
010021 --
|
| 3950 |
|
|
177700 -- 177700,170033,167757, 0, 1754,171307#
|
| 3951 |
|
|
170033 --
|
| 3952 |
|
|
167757 --
|
| 3953 |
|
|
000000 -- 0,177777, 1, 2, 0,177777#
|
| 3954 |
|
|
177777 --
|
| 3955 |
|
|
000001 --
|
| 3956 |
25 |
wfjm |
177777 -- 177777, 45716, 1,12,177777, 45716# w11a:12,045716,000000
|
| 3957 |
2 |
wfjm |
045716 --
|
| 3958 |
|
|
000001 --
|
| 3959 |
|
|
000000 -- 0, 2,177770, 4, 0, 2#
|
| 3960 |
|
|
000002 --
|
| 3961 |
|
|
177770 --
|
| 3962 |
|
|
177777 -- 177777,177776, 10, 4, 0,177776#
|
| 3963 |
|
|
177776 --
|
| 3964 |
|
|
000010 --
|
| 3965 |
|
|
000001 -- 1,177777, 1, 2, 1,177777#
|
| 3966 |
|
|
177777 --
|
| 3967 |
|
|
000001 --
|
| 3968 |
|
|
000001 -- 1, 0, 2, 2, 1, 0#
|
| 3969 |
|
|
000000 --
|
| 3970 |
|
|
000002 --
|
| 3971 |
|
|
000001 -- 1, 0, 3, 0, 52525, 1#
|
| 3972 |
|
|
000000 --
|
| 3973 |
|
|
000003 --
|
| 3974 |
|
|
000023 -- 23, 16054, 16537, 0, 246, 10222#
|
| 3975 |
|
|
016054 --
|
| 3976 |
|
|
016537 --
|
| 3977 |
|
|
#----
|
| 3978 |
|
|
wr2 177776 -- r2=177776 -> psw
|
| 3979 |
|
|
wr3 000021 -- r3=21 (17.) -> test count
|
| 3980 |
|
|
wr4 036000 -- r4=36000 -> input area
|
| 3981 |
|
|
wr5 037000 -- r5=37000 -> output area
|
| 3982 |
|
|
wsp 001400 -- sp=1400
|
| 3983 |
30 |
wfjm |
cres
|
| 3984 |
2 |
wfjm |
stapc 012300 -- start @ 12300
|
| 3985 |
|
|
wtgo
|
| 3986 |
|
|
rpc d=012322 -- ! pc
|
| 3987 |
|
|
rr3 d=000000 -- ! r3=0
|
| 3988 |
|
|
rr4 d=036146 -- ! r4=36146
|
| 3989 |
|
|
rr5 d=037146 -- ! r5=37146
|
| 3990 |
|
|
wal 037000 --
|
| 3991 |
|
|
brm 51
|
| 3992 |
|
|
d=000000 --!177777,177777,177777, 0, 1, 0#
|
| 3993 |
|
|
d=000001 --!
|
| 3994 |
|
|
d=000000 --!
|
| 3995 |
25 |
wfjm |
d=000012 --! 0,177777,177777,12, 0,177777# w11a:12,000001,000000
|
| 3996 |
|
|
d=000001 --!
|
| 3997 |
2 |
wfjm |
d=000000 --!
|
| 3998 |
|
|
d=000002 --!177777, 0,177777, 2,177777, 0#
|
| 3999 |
|
|
d=177777 --!
|
| 4000 |
|
|
d=000000 --!
|
| 4001 |
|
|
d=000004 --! 0, 7642, 7643, 4, 0, 7642#
|
| 4002 |
|
|
d=000000 --!
|
| 4003 |
|
|
d=007642 --!
|
| 4004 |
|
|
d=000004 --! 0, 137,177543, 4, 0, 137#
|
| 4005 |
|
|
d=000000 --!
|
| 4006 |
|
|
d=000137 --!
|
| 4007 |
|
|
d=000000 --! 0, 7643, 7643, 0, 1, 0#
|
| 4008 |
|
|
d=000001 --!
|
| 4009 |
|
|
d=000000 --!
|
| 4010 |
|
|
d=000012 --!100000, 4376, 10021,12,100000, 4376#
|
| 4011 |
|
|
d=100000 --!
|
| 4012 |
|
|
d=004376 --!
|
| 4013 |
|
|
d=000010 --!177700,170033, 10021,10,176024,171307#
|
| 4014 |
|
|
d=176024 --!
|
| 4015 |
|
|
d=171307 --!
|
| 4016 |
|
|
d=000000 --!177700,170033,167757, 0, 1754,171307#
|
| 4017 |
|
|
d=001754 --!
|
| 4018 |
|
|
d=171307 --!
|
| 4019 |
|
|
d=000002 --! 0,177777, 1, 2, 0,177777#
|
| 4020 |
|
|
d=000000 --!
|
| 4021 |
|
|
d=177777 --!
|
| 4022 |
25 |
wfjm |
d=000012 --!177777, 45716, 1,12,177777, 45716# w11a:12,045716,000000
|
| 4023 |
2 |
wfjm |
d=045716 --!
|
| 4024 |
25 |
wfjm |
d=000000 --!
|
| 4025 |
2 |
wfjm |
d=000004 --! 0, 2,177770, 4, 0, 2#
|
| 4026 |
|
|
d=000000 --!
|
| 4027 |
|
|
d=000002 --!
|
| 4028 |
|
|
d=000004 --!177777,177776, 10, 4, 0,177776#
|
| 4029 |
|
|
d=000000 --!
|
| 4030 |
|
|
d=177776 --!
|
| 4031 |
|
|
d=000002 --! 1,177777, 1, 2, 1,177777#
|
| 4032 |
|
|
d=000001 --!
|
| 4033 |
|
|
d=177777 --!
|
| 4034 |
|
|
d=000002 --! 1, 0, 2, 2, 1, 0#
|
| 4035 |
|
|
d=000001 --!
|
| 4036 |
|
|
d=000000 --!
|
| 4037 |
|
|
d=000000 --! 1, 0, 3, 0, 52525, 1#
|
| 4038 |
|
|
d=052525 --!
|
| 4039 |
|
|
d=000001 --!
|
| 4040 |
|
|
d=000000 --! 23, 16054, 16537, 0, 246, 10222#
|
| 4041 |
|
|
d=000246 --!
|
| 4042 |
|
|
d=010222 --!
|
| 4043 |
|
|
#-----------------------------------------------------------------------------
|
| 4044 |
|
|
C Setup code 40 [base 12400] (systematic ASH test)
|
| 4045 |
|
|
#
|
| 4046 |
|
|
wal 012400 -- code:
|
| 4047 |
|
|
bwm 15
|
| 4048 |
|
|
000230 -- spl 0
|
| 4049 |
|
|
016400 -- L1: mov 2(r4),r0
|
| 4050 |
|
|
000002
|
| 4051 |
|
|
011412 -- mov (r4),(r2)
|
| 4052 |
|
|
072064 -- ash 4(r4),r0
|
| 4053 |
|
|
000004
|
| 4054 |
|
|
011265 -- mov (r2),2(r5)
|
| 4055 |
|
|
000002
|
| 4056 |
|
|
#12420
|
| 4057 |
|
|
010015 -- mov r0,(r5)
|
| 4058 |
|
|
062704 -- add #6,r4
|
| 4059 |
|
|
000006
|
| 4060 |
|
|
062705 -- add #4,r5
|
| 4061 |
|
|
000004
|
| 4062 |
|
|
077315 -- sob r3,L1
|
| 4063 |
|
|
000000 -- halt
|
| 4064 |
|
|
#
|
| 4065 |
|
|
C Exec code 40 (systematic ASH test)
|
| 4066 |
|
|
C Exec test 40.1: data adapted from ash.s11 code of Begemot p11-2.10c
|
| 4067 |
|
|
#
|
| 4068 |
|
|
# The {} comments are original comments from Harti Brandt
|
| 4069 |
|
|
# Annotations starting with !! indicated mods for W11
|
| 4070 |
|
|
# Note, that the W11 does not have the microcode bugs of the J11 !
|
| 4071 |
|
|
#
|
| 4072 |
|
|
wal 036000 -- setup test vector:
|
| 4073 |
|
|
# test shift amount 0
|
| 4074 |
|
|
bwm 150
|
| 4075 |
|
|
000000 -- 00, 000000, 000000, 000000, 04
|
| 4076 |
|
|
000000 --
|
| 4077 |
|
|
000000 --
|
| 4078 |
|
|
000017 -- 17, 000000, 000000, 000000, 04
|
| 4079 |
|
|
000000 --
|
| 4080 |
|
|
000000 --
|
| 4081 |
|
|
000017 -- 17, 100001, 000000, 100001, 10
|
| 4082 |
|
|
100001 --
|
| 4083 |
|
|
000000 --
|
| 4084 |
|
|
000017 -- 17, 040001, 000000, 040001, 00
|
| 4085 |
|
|
040001 --
|
| 4086 |
|
|
000000 --
|
| 4087 |
|
|
000017 -- 17, 040001, 177700, 040001, 00
|
| 4088 |
|
|
040001 --
|
| 4089 |
|
|
177700 --
|
| 4090 |
|
|
# right shift positive values
|
| 4091 |
|
|
000000 -- 00, 000000, 000077, 000000, 04
|
| 4092 |
|
|
000000 --
|
| 4093 |
|
|
000077 --
|
| 4094 |
|
|
000017 -- 17, 000000, 000077, 000000, 04
|
| 4095 |
|
|
000000 --
|
| 4096 |
|
|
000077 --
|
| 4097 |
|
|
000000 -- 00, 000002, 000077, 000001, 00
|
| 4098 |
|
|
000002 --
|
| 4099 |
|
|
000077 --
|
| 4100 |
|
|
000000 -- 00, 000001, 000077, 000000, 05
|
| 4101 |
|
|
000001 --
|
| 4102 |
|
|
000077 --
|
| 4103 |
|
|
000000 -- 00, 000003, 000076, 000000, 05
|
| 4104 |
|
|
000003 --
|
| 4105 |
|
|
000076 --
|
| 4106 |
|
|
000000 -- 00, 000001, 000076, 000000, 04
|
| 4107 |
|
|
000001 --
|
| 4108 |
|
|
000076 --
|
| 4109 |
|
|
000000 -- 00, 040000, 000062, 000001, 00
|
| 4110 |
|
|
040000 --
|
| 4111 |
|
|
000062 --
|
| 4112 |
|
|
000000 -- 00, 040000, 000061, 000000, 05
|
| 4113 |
|
|
040000 --
|
| 4114 |
|
|
000061 --
|
| 4115 |
|
|
000000 -- 00, 040000, 000060, 000000, 04
|
| 4116 |
|
|
040000 --
|
| 4117 |
|
|
000060 --
|
| 4118 |
|
|
000000 -- 00, 040000, 000042, 000000, 04
|
| 4119 |
|
|
040000 --
|
| 4120 |
|
|
000042 --
|
| 4121 |
|
|
000000 -- 00, 040000, 000041, 000000, 04
|
| 4122 |
|
|
040000 --
|
| 4123 |
|
|
000041 --
|
| 4124 |
|
|
000000 -- 00, 040000, 000040, 000000, 04
|
| 4125 |
|
|
040000 --
|
| 4126 |
|
|
000040 --
|
| 4127 |
|
|
000000 -- 00, 040000, 100037, 000000, 04
|
| 4128 |
|
|
040000 --
|
| 4129 |
|
|
100037 --
|
| 4130 |
|
|
# right shift negative numbers
|
| 4131 |
|
|
000000 -- 00, 100002, 000077, 140001, 10
|
| 4132 |
|
|
100002 --
|
| 4133 |
|
|
000077 --
|
| 4134 |
|
|
000000 -- 00, 100002, 000076, 160000, 11
|
| 4135 |
|
|
100002 --
|
| 4136 |
|
|
000076 --
|
| 4137 |
|
|
000000 -- 00, 100002, 000075, 170000, 10
|
| 4138 |
|
|
100002 --
|
| 4139 |
|
|
000075 --
|
| 4140 |
|
|
000000 -- 00, 100002, 000062, 177776, 10
|
| 4141 |
|
|
100002 --
|
| 4142 |
|
|
000062 --
|
| 4143 |
|
|
000000 -- 00, 100002, 000061, 177777, 10
|
| 4144 |
|
|
100002 --
|
| 4145 |
|
|
000061 --
|
| 4146 |
|
|
000000 -- 00, 100002, 000060, 177777, 11
|
| 4147 |
|
|
100002 --
|
| 4148 |
|
|
000060 --
|
| 4149 |
|
|
000000 -- 00, 100002, 000057, 177777, 11
|
| 4150 |
|
|
100002 --
|
| 4151 |
|
|
000057 --
|
| 4152 |
|
|
000000 -- 00, 100002, 000056, 177777, 11
|
| 4153 |
|
|
100002 --
|
| 4154 |
|
|
000056 --
|
| 4155 |
|
|
000000 -- 00, 100002, 000041, 177777, 11
|
| 4156 |
|
|
100002 --
|
| 4157 |
|
|
000041 --
|
| 4158 |
|
|
000000 -- 00, 100002, 000040, 177777, 11
|
| 4159 |
|
|
100002 --
|
| 4160 |
|
|
000040 --
|
| 4161 |
|
|
000000 -- 00, 100002, 040037, 177777, 11
|
| 4162 |
|
|
100002 --
|
| 4163 |
|
|
040037 --
|
| 4164 |
|
|
# left shift positive numbers
|
| 4165 |
|
|
000000 -- 00, 000000, 000001, 000000, 04
|
| 4166 |
|
|
000000 --
|
| 4167 |
|
|
000001 --
|
| 4168 |
|
|
000017 -- 17, 000000, 000001, 000000, 04
|
| 4169 |
|
|
000000 --
|
| 4170 |
|
|
000001 --
|
| 4171 |
|
|
000000 -- 00, 000001, 000007, 000200, 00
|
| 4172 |
|
|
000001 --
|
| 4173 |
|
|
000007 --
|
| 4174 |
|
|
000000 -- 00, 000001, 000016, 040000, 00
|
| 4175 |
|
|
000001 --
|
| 4176 |
|
|
000016 --
|
| 4177 |
|
|
000000 -- 00, 000001, 000017, 100000, 12
|
| 4178 |
|
|
000001 --
|
| 4179 |
|
|
000017 --
|
| 4180 |
|
|
000000 -- 00, 000001, 000020, 000000, 07
|
| 4181 |
|
|
000001 --
|
| 4182 |
|
|
000020 --
|
| 4183 |
|
|
000000 -- 00, 000001, 000021, 000000, 06
|
| 4184 |
|
|
000001 --
|
| 4185 |
|
|
000021 --
|
| 4186 |
|
|
000000 -- 00, 000001, 000036, 000000, 06
|
| 4187 |
|
|
000001 --
|
| 4188 |
|
|
000036 --
|
| 4189 |
|
|
000000 -- 00, 000001, 000037, 000000, 04 {????}
|
| 4190 |
|
|
000001 --
|
| 4191 |
|
|
000037 --
|
| 4192 |
|
|
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
|
| 4193 |
|
|
000001 --
|
| 4194 |
|
|
000040 --
|
| 4195 |
|
|
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
|
| 4196 |
|
|
000001 --
|
| 4197 |
|
|
010037 --
|
| 4198 |
|
|
# left shift negative numbers
|
| 4199 |
|
|
000000 -- 00, 100001, 000001, 000002, 03
|
| 4200 |
|
|
100001 --
|
| 4201 |
|
|
000001 --
|
| 4202 |
|
|
000000 -- 00, 140001, 000001, 100002, 11
|
| 4203 |
|
|
140001 --
|
| 4204 |
|
|
000001 --
|
| 4205 |
|
|
000000 -- 00, 140001, 000002, 000004, 03
|
| 4206 |
|
|
140001 --
|
| 4207 |
|
|
000002 --
|
| 4208 |
|
|
000000 -- 00, 140001, 000016, 040000, 02
|
| 4209 |
|
|
140001 --
|
| 4210 |
|
|
000016 --
|
| 4211 |
|
|
000000 -- 00, 140001, 000017, 100000, 12
|
| 4212 |
|
|
140001 --
|
| 4213 |
|
|
000017 --
|
| 4214 |
|
|
000000 -- 00, 140001, 000020, 000000, 07
|
| 4215 |
|
|
140001 --
|
| 4216 |
|
|
000020 --
|
| 4217 |
|
|
000000 -- 00, 140001, 000021, 000000, 06
|
| 4218 |
|
|
140001 --
|
| 4219 |
|
|
000021 --
|
| 4220 |
|
|
000000 -- 00, 140002, 000035, 000000, 06
|
| 4221 |
|
|
140002 --
|
| 4222 |
|
|
000035 --
|
| 4223 |
|
|
000000 -- 00, 140002, 000036, 000000, 06
|
| 4224 |
|
|
140002 --
|
| 4225 |
|
|
000036 --
|
| 4226 |
|
|
000000 -- 00, 140002, 000037, 177777, 11 {????}
|
| 4227 |
|
|
140002 --
|
| 4228 |
|
|
000037 --
|
| 4229 |
|
|
#----
|
| 4230 |
|
|
wr2 177776 -- r2=177776 -> psw
|
| 4231 |
|
|
wr3 000062 -- r3=62 -> test count
|
| 4232 |
|
|
wr4 036000 -- r4=36000 -> input area
|
| 4233 |
|
|
wr5 037000 -- r5=37000 -> output area
|
| 4234 |
|
|
wsp 001400 -- sp=1400
|
| 4235 |
30 |
wfjm |
cres
|
| 4236 |
2 |
wfjm |
stapc 012400 -- start @ 12400
|
| 4237 |
|
|
wtgo
|
| 4238 |
|
|
rpc d=012436 -- ! pc
|
| 4239 |
|
|
rr3 d=000000 -- ! r3=0
|
| 4240 |
|
|
rr4 d=036454 -- ! r4=36454
|
| 4241 |
|
|
rr5 d=037310 -- ! r5=37310
|
| 4242 |
|
|
wal 037000 --
|
| 4243 |
|
|
# test shift amount 0
|
| 4244 |
|
|
brm 100
|
| 4245 |
|
|
d=000000 -- 00, 000000, 000000, 000000, 04
|
| 4246 |
|
|
d=000004 --
|
| 4247 |
|
|
d=000000 -- 17, 000000, 000000, 000000, 04
|
| 4248 |
|
|
d=000004 --
|
| 4249 |
|
|
d=100001 -- 17, 100001, 000000, 100001, 10
|
| 4250 |
|
|
d=000010 --
|
| 4251 |
|
|
d=040001 -- 17, 040001, 000000, 040001, 00
|
| 4252 |
|
|
d=000000 --
|
| 4253 |
|
|
d=040001 -- 17, 040001, 177700, 040001, 00
|
| 4254 |
|
|
d=000000 --
|
| 4255 |
|
|
#37024 # right shift positive values
|
| 4256 |
|
|
d=000000 -- 00, 000000, 000077, 000000, 04
|
| 4257 |
|
|
d=000004 --
|
| 4258 |
|
|
d=000000 -- 17, 000000, 000077, 000000, 04
|
| 4259 |
|
|
d=000004 --
|
| 4260 |
|
|
d=000001 -- 00, 000002, 000077, 000001, 00
|
| 4261 |
|
|
d=000000 --
|
| 4262 |
|
|
#37040
|
| 4263 |
|
|
d=000000 -- 00, 000001, 000077, 000000, 05
|
| 4264 |
|
|
d=000005 --
|
| 4265 |
|
|
d=000000 -- 00, 000003, 000076, 000000, 05
|
| 4266 |
|
|
d=000005 --
|
| 4267 |
|
|
d=000000 -- 00, 000001, 000076, 000000, 04
|
| 4268 |
|
|
d=000004 --
|
| 4269 |
|
|
d=000001 -- 00, 040000, 000062, 000001, 00
|
| 4270 |
|
|
d=000000 --
|
| 4271 |
|
|
#37060
|
| 4272 |
|
|
d=000000 -- 00, 040000, 000061, 000000, 05
|
| 4273 |
|
|
d=000005 --
|
| 4274 |
|
|
d=000000 -- 00, 040000, 000060, 000000, 04
|
| 4275 |
|
|
d=000004 --
|
| 4276 |
|
|
d=000000 -- 00, 040000, 000042, 000000, 04
|
| 4277 |
|
|
d=000004 --
|
| 4278 |
|
|
d=000000 -- 00, 040000, 000041, 000000, 04
|
| 4279 |
|
|
d=000004 --
|
| 4280 |
|
|
#37100
|
| 4281 |
|
|
d=000000 -- 00, 040000, 000040, 000000, 04
|
| 4282 |
|
|
d=000004 --
|
| 4283 |
|
|
d=000000 -- 00, 040000, 100037, 000000, 04
|
| 4284 |
|
|
d=000006 -- !!04->06
|
| 4285 |
|
|
#37110 # right shift negative numbers
|
| 4286 |
|
|
d=140001 -- 00, 100002, 000077, 140001, 10
|
| 4287 |
|
|
d=000010 --
|
| 4288 |
|
|
d=160000 -- 00, 100002, 000076, 160000, 11
|
| 4289 |
|
|
d=000011 --
|
| 4290 |
|
|
#37120
|
| 4291 |
|
|
d=170000 -- 00, 100002, 000075, 170000, 10
|
| 4292 |
|
|
d=000010 --
|
| 4293 |
|
|
d=177776 -- 00, 100002, 000062, 177776, 10
|
| 4294 |
|
|
d=000010 --
|
| 4295 |
|
|
d=177777 -- 00, 100002, 000061, 177777, 10
|
| 4296 |
|
|
d=000010 --
|
| 4297 |
|
|
d=177777 -- 00, 100002, 000060, 177777, 11
|
| 4298 |
|
|
d=000011 --
|
| 4299 |
|
|
#37140
|
| 4300 |
|
|
d=177777 -- 00, 100002, 000057, 177777, 11
|
| 4301 |
|
|
d=000011 --
|
| 4302 |
|
|
d=177777 -- 00, 100002, 000056, 177777, 11
|
| 4303 |
|
|
d=000011 --
|
| 4304 |
|
|
d=177777 -- 00, 100002, 000041, 177777, 11
|
| 4305 |
|
|
d=000011 --
|
| 4306 |
|
|
d=177777 -- 00, 100002, 000040, 177777, 11
|
| 4307 |
|
|
d=000011 -- see Note below [[s:10]]
|
| 4308 |
|
|
d=000000 -- 00, 100002, 040037, 177777, 11 !!-1->0
|
| 4309 |
|
|
d=000006 -- !!11->06
|
| 4310 |
|
|
#37164 # left shift positive numbers
|
| 4311 |
|
|
d=000000 -- 00, 000000, 000001, 000000, 04
|
| 4312 |
|
|
d=000004 --
|
| 4313 |
|
|
d=000000 -- 17, 000000, 000001, 000000, 04
|
| 4314 |
|
|
d=000004 --
|
| 4315 |
|
|
d=000200 -- 00, 000001, 000007, 000200, 00
|
| 4316 |
|
|
d=000000 --
|
| 4317 |
|
|
#37200
|
| 4318 |
|
|
d=040000 -- 00, 000001, 000016, 040000, 00
|
| 4319 |
|
|
d=000000 --
|
| 4320 |
|
|
d=100000 -- 00, 000001, 000017, 100000, 12
|
| 4321 |
|
|
d=000012 --
|
| 4322 |
|
|
d=000000 -- 00, 000001, 000020, 000000, 07
|
| 4323 |
|
|
d=000007 --
|
| 4324 |
|
|
d=000000 -- 00, 000001, 000021, 000000, 06
|
| 4325 |
|
|
d=000006 --
|
| 4326 |
|
|
#37220
|
| 4327 |
|
|
d=000000 -- 00, 000001, 000036, 000000, 06
|
| 4328 |
|
|
d=000006 --
|
| 4329 |
|
|
d=000000 -- 00, 000001, 000037, 000000, 04 {????}
|
| 4330 |
|
|
d=000006 -- !!04->06
|
| 4331 |
|
|
d=000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
|
| 4332 |
|
|
d=000004 --
|
| 4333 |
|
|
d=000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
|
| 4334 |
|
|
d=000006 -- !!04->06
|
| 4335 |
|
|
#37240 # left shift negative numbers
|
| 4336 |
|
|
d=000002 -- 00, 100001, 000001, 000002, 03
|
| 4337 |
|
|
d=000003 --
|
| 4338 |
|
|
d=100002 -- 00, 140001, 000001, 100002, 11
|
| 4339 |
|
|
d=000011 --
|
| 4340 |
|
|
d=000004 -- 00, 140001, 000002, 000004, 03
|
| 4341 |
|
|
d=000003 --
|
| 4342 |
|
|
d=040000 -- 00, 140001, 000016, 040000, 02
|
| 4343 |
|
|
d=000002 --
|
| 4344 |
|
|
#37260
|
| 4345 |
|
|
d=100000 -- 00, 140001, 000017, 100000, 12
|
| 4346 |
|
|
d=000012 --
|
| 4347 |
|
|
d=000000 -- 00, 140001, 000020, 000000, 07
|
| 4348 |
|
|
d=000007 --
|
| 4349 |
|
|
d=000000 -- 00, 140001, 000021, 000000, 06
|
| 4350 |
|
|
d=000006 --
|
| 4351 |
|
|
d=000000 -- 00, 140002, 000035, 000000, 06
|
| 4352 |
|
|
d=000006 --
|
| 4353 |
|
|
#37300
|
| 4354 |
|
|
d=000000 -- 00, 140002, 000036, 000000, 06
|
| 4355 |
|
|
d=000006 --
|
| 4356 |
|
|
d=000000 -- 00, 140002, 000037, 177777, 11 {????} !!-1->0
|
| 4357 |
|
|
d=000006 -- !!11->06
|
| 4358 |
|
|
#
|
| 4359 |
|
|
# simh notes:
|
| 4360 |
|
|
# 1. ash dst=100002,src=040 sets C=0 in simh. PSW is: s:10 b:11 W11:11
|
| 4361 |
|
|
#
|
| 4362 |
|
|
#-----------------------------------------------------------------------------
|
| 4363 |
|
|
C Setup code 41 [base 12500] (systematic ASHC even test)
|
| 4364 |
|
|
#
|
| 4365 |
|
|
wal 012500 -- code:
|
| 4366 |
|
|
bwm 19
|
| 4367 |
|
|
000230 -- spl 0
|
| 4368 |
|
|
016400 -- L1: mov 2(r4),r0
|
| 4369 |
|
|
000002
|
| 4370 |
|
|
016401 -- mov 4(r4),r1
|
| 4371 |
|
|
000004
|
| 4372 |
|
|
011412 -- mov (r4),(r2)
|
| 4373 |
|
|
073064 -- ashc 6(r4),r0
|
| 4374 |
|
|
000006
|
| 4375 |
|
|
#12520
|
| 4376 |
|
|
011265 -- mov (r2),4(r5)
|
| 4377 |
|
|
000004
|
| 4378 |
|
|
010015 -- mov r0,(r5)
|
| 4379 |
|
|
010165 -- mov r1,2(r5)
|
| 4380 |
|
|
000002
|
| 4381 |
|
|
062704 -- add #10,r4
|
| 4382 |
|
|
000010
|
| 4383 |
|
|
062705 -- add #6,r5
|
| 4384 |
|
|
#12540
|
| 4385 |
|
|
000006
|
| 4386 |
|
|
077321 -- sob r3,L1
|
| 4387 |
|
|
000000 -- halt
|
| 4388 |
|
|
#
|
| 4389 |
|
|
C Exec code 41 (systematic ASHC even test)
|
| 4390 |
|
|
C Exec test 41.1: data adapted from ashc.s11 code of Begemot p11-2.10c
|
| 4391 |
|
|
#
|
| 4392 |
|
|
# The {} comments are original comments from Harti Brandt
|
| 4393 |
|
|
# Annotations starting with !! indicated mods for W11
|
| 4394 |
|
|
# Note, that the W11 does not have the microcode bugs of the J11 !
|
| 4395 |
|
|
#
|
| 4396 |
|
|
wal 036000 -- setup test vector:
|
| 4397 |
|
|
# test when no shift at all, cc must be correctly set
|
| 4398 |
|
|
bwm 188
|
| 4399 |
|
|
000000 -- 00, 000000, 000000, 000000, 000000, 000000, 04
|
| 4400 |
|
|
000000 --
|
| 4401 |
|
|
000000 --
|
| 4402 |
|
|
000000 --
|
| 4403 |
|
|
000017 -- 17, 000000, 000000, 000000, 000000, 000000, 04
|
| 4404 |
|
|
000000 --
|
| 4405 |
|
|
000000 --
|
| 4406 |
|
|
000000 --
|
| 4407 |
|
|
000017 -- 17, 040000, 000001, 000000, 040000, 000001, 00
|
| 4408 |
|
|
040000 --
|
| 4409 |
|
|
000001 --
|
| 4410 |
|
|
000000 --
|
| 4411 |
|
|
000017 -- 17, 100000, 000001, 000000, 100000, 000001, 10
|
| 4412 |
|
|
100000 --
|
| 4413 |
|
|
000001 --
|
| 4414 |
|
|
000000 --
|
| 4415 |
|
|
000017 -- 17, 100000, 000001, 177700, 100000, 000001, 10
|
| 4416 |
|
|
100000 --
|
| 4417 |
|
|
000001 --
|
| 4418 |
|
|
177700 --
|
| 4419 |
|
|
# right shifts of positive numbers
|
| 4420 |
|
|
000000 -- 00, 000000, 000000, 000077, 000000, 000000, 04
|
| 4421 |
|
|
000000 --
|
| 4422 |
|
|
000000 --
|
| 4423 |
|
|
000077 --
|
| 4424 |
|
|
000017 -- 17, 000000, 000000, 000077, 000000, 000000, 04
|
| 4425 |
|
|
000000 --
|
| 4426 |
|
|
000000 --
|
| 4427 |
|
|
000077 --
|
| 4428 |
|
|
000000 -- 00, 040000, 000000, 000077, 020000, 000000, 00
|
| 4429 |
|
|
040000 --
|
| 4430 |
|
|
000000 --
|
| 4431 |
|
|
000077 --
|
| 4432 |
|
|
000000 -- 00, 040000, 000000, 177777, 020000, 000000, 00
|
| 4433 |
|
|
040000 --
|
| 4434 |
|
|
000000 --
|
| 4435 |
|
|
000077 --
|
| 4436 |
|
|
000000 -- 00, 040000, 000000, 000060, 000000, 040000, 00
|
| 4437 |
|
|
040000 --
|
| 4438 |
|
|
000000 --
|
| 4439 |
|
|
000060 --
|
| 4440 |
|
|
000000 -- 00, 040000, 000000, 000042, 000000, 000001, 00
|
| 4441 |
|
|
040000 --
|
| 4442 |
|
|
000000 --
|
| 4443 |
|
|
000042 --
|
| 4444 |
|
|
000000 -- 00, 040000, 000000, 000041, 000000, 000000, 05
|
| 4445 |
|
|
040000 --
|
| 4446 |
|
|
000000 --
|
| 4447 |
|
|
000041 --
|
| 4448 |
|
|
000000 -- 00, 040000, 000000, 000040, 000000, 000000, 04
|
| 4449 |
|
|
040000 --
|
| 4450 |
|
|
000000 --
|
| 4451 |
|
|
000040 --
|
| 4452 |
|
|
000000 -- 00, 040000, 000000, 177737, 000000, 000000, 04
|
| 4453 |
|
|
040000 --
|
| 4454 |
|
|
000000 --
|
| 4455 |
|
|
177737 --
|
| 4456 |
|
|
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04
|
| 4457 |
|
|
000000 --
|
| 4458 |
|
|
000001 --
|
| 4459 |
|
|
177737 --
|
| 4460 |
|
|
# right shifts of negative numbers
|
| 4461 |
|
|
000000 -- 00, 100000, 000002, 000077, 140000, 000001, 10
|
| 4462 |
|
|
100000 --
|
| 4463 |
|
|
000002 --
|
| 4464 |
|
|
000077 --
|
| 4465 |
|
|
000000 -- 00, 100020, 000001, 000077, 140010, 000000, 11
|
| 4466 |
|
|
100020 --
|
| 4467 |
|
|
000001 --
|
| 4468 |
|
|
000077 --
|
| 4469 |
|
|
000000 -- 00, 177777, 177776, 000077, 177777, 177777, 10
|
| 4470 |
|
|
177777 --
|
| 4471 |
|
|
177776 --
|
| 4472 |
|
|
000077 --
|
| 4473 |
|
|
000000 -- 00, 177777, 177777, 000077, 177777, 177777, 11
|
| 4474 |
|
|
177777 --
|
| 4475 |
|
|
177777 --
|
| 4476 |
|
|
000077 --
|
| 4477 |
|
|
000000 -- 00, 100000, 100000, 000060, 177777, 100000, 11
|
| 4478 |
|
|
100000 --
|
| 4479 |
|
|
100000 --
|
| 4480 |
|
|
000060 --
|
| 4481 |
|
|
000000 -- 00, 100000, 000000, 000060, 177777, 100000, 10
|
| 4482 |
|
|
100000 --
|
| 4483 |
|
|
000000 --
|
| 4484 |
|
|
000060 --
|
| 4485 |
|
|
000000 -- 00, 100000, 000001, 000042, 177777, 177776, 10
|
| 4486 |
|
|
100000 --
|
| 4487 |
|
|
000001 --
|
| 4488 |
|
|
000042 --
|
| 4489 |
|
|
000000 -- 00, 100000, 000001, 000041, 177777, 177777, 10
|
| 4490 |
|
|
100000 --
|
| 4491 |
|
|
000001 --
|
| 4492 |
|
|
000041 --
|
| 4493 |
|
|
000000 -- 00, 100000, 000001, 000040, 177777, 177777, 11
|
| 4494 |
|
|
100000 --
|
| 4495 |
|
|
000001 --
|
| 4496 |
|
|
000040 --
|
| 4497 |
|
|
000000 -- 00, 100000, 000001, 177737, 177777, 177777, 11
|
| 4498 |
|
|
100000 --
|
| 4499 |
|
|
000001 --
|
| 4500 |
|
|
177737 --
|
| 4501 |
|
|
# left shifts of positive numbers
|
| 4502 |
|
|
000000 -- 00, 000000, 000000, 000001, 000000, 000000, 04
|
| 4503 |
|
|
000000 --
|
| 4504 |
|
|
000000 --
|
| 4505 |
|
|
000001 --
|
| 4506 |
|
|
000017 -- 17, 000000, 000000, 000001, 000000, 000000, 04
|
| 4507 |
|
|
000000 --
|
| 4508 |
|
|
000000 --
|
| 4509 |
|
|
000001 --
|
| 4510 |
|
|
000000 -- 00, 000002, 000001, 000001, 000004, 000002, 00
|
| 4511 |
|
|
000002 --
|
| 4512 |
|
|
000001 --
|
| 4513 |
|
|
000001 --
|
| 4514 |
|
|
000000 -- 00, 000002, 100000, 000001, 000005, 000000, 00
|
| 4515 |
|
|
000002 --
|
| 4516 |
|
|
100000 --
|
| 4517 |
|
|
000001 --
|
| 4518 |
|
|
000000 -- 00, 040000, 000000, 000001, 100000, 000000, 12
|
| 4519 |
|
|
040000 --
|
| 4520 |
|
|
000000 --
|
| 4521 |
|
|
000001 --
|
| 4522 |
|
|
000000 -- 00, 040000, 000000, 000002, 000000, 000000, 07
|
| 4523 |
|
|
040000 --
|
| 4524 |
|
|
000000 --
|
| 4525 |
|
|
000002 --
|
| 4526 |
|
|
000000 -- 00, 040000, 000000, 000003, 000000, 000000, 06
|
| 4527 |
|
|
040000 --
|
| 4528 |
|
|
000000 --
|
| 4529 |
|
|
000003 --
|
| 4530 |
|
|
000000 -- 00, 000000, 000001, 177701, 000000, 000002, 00
|
| 4531 |
|
|
000000 --
|
| 4532 |
|
|
000001 --
|
| 4533 |
|
|
177701 --
|
| 4534 |
|
|
000000 -- 00, 000000, 000001, 177735, 020000, 000000, 00
|
| 4535 |
|
|
000000 --
|
| 4536 |
|
|
000001 --
|
| 4537 |
|
|
177735 --
|
| 4538 |
|
|
000000 -- 00, 000000, 000001, 177736, 040000, 000000, 00
|
| 4539 |
|
|
000000 --
|
| 4540 |
|
|
000001 --
|
| 4541 |
|
|
177736 --
|
| 4542 |
|
|
000000 -- 00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
|
| 4543 |
|
|
000000 --
|
| 4544 |
|
|
000001 --
|
| 4545 |
|
|
000037 --
|
| 4546 |
|
|
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!}
|
| 4547 |
|
|
000000 --
|
| 4548 |
|
|
000001 --
|
| 4549 |
|
|
177737 --
|
| 4550 |
|
|
000000 -- 00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!}
|
| 4551 |
|
|
000000 --
|
| 4552 |
|
|
000001 --
|
| 4553 |
|
|
020037 --
|
| 4554 |
|
|
# left shifts of negative numbers
|
| 4555 |
|
|
000000 -- 00, 177777, 177777, 000001, 177777, 177776, 11
|
| 4556 |
|
|
177777 --
|
| 4557 |
|
|
177777 --
|
| 4558 |
|
|
000001 --
|
| 4559 |
|
|
000000 -- 00, 177777, 177777, 000002, 177777, 177774, 11
|
| 4560 |
|
|
177777 --
|
| 4561 |
|
|
177777 --
|
| 4562 |
|
|
000002 --
|
| 4563 |
|
|
000000 -- 00, 177777, 177777, 000036, 140000, 000000, 11
|
| 4564 |
|
|
177777 --
|
| 4565 |
|
|
177777 --
|
| 4566 |
|
|
000036 --
|
| 4567 |
|
|
000000 -- 00, 177777, 177777, 000037, 100000, 000000, 11
|
| 4568 |
|
|
177777 --
|
| 4569 |
|
|
177777 --
|
| 4570 |
|
|
000037 --
|
| 4571 |
|
|
000000 -- 00, 177777, 177776, 000037, 000000, 000000, 07
|
| 4572 |
|
|
177777 --
|
| 4573 |
|
|
177776 --
|
| 4574 |
|
|
000037 --
|
| 4575 |
|
|
000000 -- 00, 177777, 177774, 000037, 000000, 000000, 06
|
| 4576 |
|
|
177777 --
|
| 4577 |
|
|
177774 --
|
| 4578 |
|
|
000037 --
|
| 4579 |
|
|
000000 -- 00, 177777, 177777, 177701, 177777, 177776, 11
|
| 4580 |
|
|
177777 --
|
| 4581 |
|
|
177777 --
|
| 4582 |
|
|
177701 --
|
| 4583 |
|
|
000000 -- 00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!}
|
| 4584 |
|
|
177777 --
|
| 4585 |
|
|
177777 --
|
| 4586 |
|
|
001037 --
|
| 4587 |
|
|
000000 -- 00, 177777, 177777, 001036, 140000, 000000, 11
|
| 4588 |
|
|
177777 --
|
| 4589 |
|
|
177777 --
|
| 4590 |
|
|
001036 --
|
| 4591 |
|
|
#----
|
| 4592 |
|
|
wr2 177776 -- r2=177776
|
| 4593 |
|
|
wr3 000057 -- r3=57 (47.)
|
| 4594 |
|
|
wr4 036000 -- r4=36000
|
| 4595 |
|
|
wr5 037000 -- r5=37000
|
| 4596 |
|
|
wsp 001400 -- sp=1400
|
| 4597 |
30 |
wfjm |
cres
|
| 4598 |
2 |
wfjm |
stapc 012500 -- start @ 12500
|
| 4599 |
|
|
wtgo
|
| 4600 |
|
|
rpc d=012546 -- ! pc
|
| 4601 |
|
|
rr3 d=000000 -- ! r3=0
|
| 4602 |
|
|
rr4 d=036570 -- ! r4=36570
|
| 4603 |
|
|
rr5 d=037432 -- ! r5=37432
|
| 4604 |
|
|
wal 037000 --
|
| 4605 |
|
|
# test when no shift at all, cc must be correctly set
|
| 4606 |
|
|
brm 141
|
| 4607 |
|
|
d=000000 --!00, 000000, 000000, 000000, 000000, 000000, 04
|
| 4608 |
|
|
d=000000 --!
|
| 4609 |
|
|
d=000004 --!
|
| 4610 |
|
|
d=000000 --!17, 000000, 000000, 000000, 000000, 000000, 04
|
| 4611 |
|
|
d=000000 --!
|
| 4612 |
|
|
d=000004 --!
|
| 4613 |
|
|
d=040000 --!17, 040000, 000001, 000000, 040000, 000001, 00
|
| 4614 |
|
|
d=000001 --!
|
| 4615 |
|
|
d=000000 --!
|
| 4616 |
|
|
d=100000 --!17, 100000, 000001, 000000, 100000, 000001, 10
|
| 4617 |
|
|
d=000001 --!
|
| 4618 |
|
|
d=000010 --!
|
| 4619 |
|
|
#37030
|
| 4620 |
|
|
d=100000 --!17, 100000, 000001, 177700, 100000, 000001, 10
|
| 4621 |
|
|
d=000001 --!
|
| 4622 |
|
|
d=000010 --!
|
| 4623 |
|
|
# right shifts of positive numbers
|
| 4624 |
|
|
d=000000 --!00, 000000, 000000, 000077, 000000, 000000, 04
|
| 4625 |
|
|
d=000000 --!
|
| 4626 |
|
|
d=000004 --!
|
| 4627 |
|
|
d=000000 --!17, 000000, 000000, 000077, 000000, 000000, 04
|
| 4628 |
|
|
d=000000 --!
|
| 4629 |
|
|
d=000004 --!
|
| 4630 |
|
|
d=020000 --!00, 040000, 000000, 000077, 020000, 000000, 00
|
| 4631 |
|
|
d=000000 --!
|
| 4632 |
|
|
d=000000 --!
|
| 4633 |
|
|
#37060
|
| 4634 |
|
|
d=020000 --!00, 040000, 000000, 177777, 020000, 000000, 00
|
| 4635 |
|
|
d=000000 --!
|
| 4636 |
|
|
d=000000 --!
|
| 4637 |
|
|
d=000000 --!00, 040000, 000000, 000060, 000000, 040000, 00
|
| 4638 |
|
|
d=040000 --!
|
| 4639 |
|
|
d=000000 --!
|
| 4640 |
|
|
d=000000 --!00, 040000, 000000, 000042, 000000, 000001, 00
|
| 4641 |
|
|
d=000001 --!
|
| 4642 |
|
|
d=000000 --!
|
| 4643 |
|
|
d=000000 --!00, 040000, 000000, 000041, 000000, 000000, 05
|
| 4644 |
|
|
d=000000 --!
|
| 4645 |
|
|
d=000005 --!
|
| 4646 |
|
|
#37110
|
| 4647 |
|
|
d=000000 --!00, 040000, 000000, 000040, 000000, 000000, 04
|
| 4648 |
|
|
d=000000 --!
|
| 4649 |
|
|
d=000004 --!
|
| 4650 |
|
|
d=000000 --!00, 040000, 000000, 177737, 000000, 000000, 04
|
| 4651 |
|
|
d=000000 --!
|
| 4652 |
|
|
d=000006 --! !!04->06
|
| 4653 |
|
|
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04!!->100000
|
| 4654 |
|
|
d=000000 --!
|
| 4655 |
|
|
d=000012 --! !!04->12
|
| 4656 |
|
|
# right shifts of negative numbers
|
| 4657 |
|
|
d=140000 --!00, 100000, 000002, 000077, 140000, 000001, 10
|
| 4658 |
|
|
d=000001 --!
|
| 4659 |
|
|
d=000010 --!
|
| 4660 |
|
|
#37140
|
| 4661 |
|
|
d=140010 --!00, 100020, 000001, 000077, 140010, 000000, 11
|
| 4662 |
|
|
d=000000 --!
|
| 4663 |
|
|
d=000011 --!
|
| 4664 |
|
|
d=177777 --!00, 177777, 177776, 000077, 177777, 177777, 10
|
| 4665 |
|
|
d=177777 --!
|
| 4666 |
|
|
d=000010 --!
|
| 4667 |
|
|
d=177777 --!00, 177777, 177777, 000077, 177777, 177777, 11
|
| 4668 |
|
|
d=177777 --!
|
| 4669 |
|
|
d=000011 --!
|
| 4670 |
|
|
d=177777 --!00, 100000, 100000, 000060, 177777, 100000, 11
|
| 4671 |
|
|
d=100000 --!
|
| 4672 |
|
|
d=000011 --!
|
| 4673 |
|
|
#37170
|
| 4674 |
|
|
d=177777 --!00, 100000, 000000, 000060, 177777, 100000, 10
|
| 4675 |
|
|
d=100000 --!
|
| 4676 |
|
|
d=000010 --!
|
| 4677 |
|
|
d=177777 --!00, 100000, 000001, 000042, 177777, 177776, 10
|
| 4678 |
|
|
d=177776 --!
|
| 4679 |
|
|
d=000010 --!
|
| 4680 |
|
|
d=177777 --!00, 100000, 000001, 000041, 177777, 177777, 10
|
| 4681 |
|
|
d=177777 --!
|
| 4682 |
|
|
d=000010 --!
|
| 4683 |
|
|
d=177777 --!00, 100000, 000001, 000040, 177777, 177777, 11
|
| 4684 |
|
|
d=177777 --!
|
| 4685 |
|
|
d=000011 --!
|
| 4686 |
|
|
#37220
|
| 4687 |
|
|
d=100000 --!00, 100000, 000001, 177737, 177777, 177777, 11!!->100000
|
| 4688 |
|
|
d=000000 --! !!->000000
|
| 4689 |
|
|
d=000012 --! !!11->12
|
| 4690 |
|
|
# left shifts of positive numbers
|
| 4691 |
|
|
d=000000 --!00, 000000, 000000, 000001, 000000, 000000, 04
|
| 4692 |
|
|
d=000000 --!
|
| 4693 |
|
|
d=000004 --!
|
| 4694 |
|
|
d=000000 --!17, 000000, 000000, 000001, 000000, 000000, 04
|
| 4695 |
|
|
d=000000 --!
|
| 4696 |
|
|
d=000004 --!
|
| 4697 |
|
|
d=000004 --!00, 000002, 000001, 000001, 000004, 000002, 00
|
| 4698 |
|
|
d=000002 --!
|
| 4699 |
|
|
d=000000 --!
|
| 4700 |
|
|
#37250
|
| 4701 |
|
|
d=000005 --!00, 000002, 100000, 000001, 000005, 000000, 00
|
| 4702 |
|
|
d=000000 --!
|
| 4703 |
|
|
d=000000 --!
|
| 4704 |
|
|
d=100000 --!00, 040000, 000000, 000001, 100000, 000000, 12
|
| 4705 |
|
|
d=000000 --!
|
| 4706 |
|
|
d=000012 --!
|
| 4707 |
|
|
d=000000 --!00, 040000, 000000, 000002, 000000, 000000, 07
|
| 4708 |
|
|
d=000000 --!
|
| 4709 |
|
|
d=000007 --!
|
| 4710 |
|
|
d=000000 --!00, 040000, 000000, 000003, 000000, 000000, 06
|
| 4711 |
|
|
d=000000 --!
|
| 4712 |
|
|
d=000006 --!
|
| 4713 |
|
|
#37300
|
| 4714 |
|
|
d=000000 --!00, 000000, 000001, 177701, 000000, 000002, 00
|
| 4715 |
|
|
d=000002 --!
|
| 4716 |
|
|
d=000000 --!
|
| 4717 |
|
|
d=020000 --!00, 000000, 000001, 177735, 020000, 000000, 00
|
| 4718 |
|
|
d=000000 --!
|
| 4719 |
|
|
d=000000 --!
|
| 4720 |
|
|
d=040000 --!00, 000000, 000001, 177736, 040000, 000000, 00
|
| 4721 |
|
|
d=000000 --!
|
| 4722 |
|
|
d=000000 --!
|
| 4723 |
|
|
d=100000 --!00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
|
| 4724 |
|
|
d=000000 --!
|
| 4725 |
|
|
d=000012 --!
|
| 4726 |
|
|
#37330
|
| 4727 |
|
|
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!} !!->100000
|
| 4728 |
|
|
d=000000 --!
|
| 4729 |
|
|
d=000012 --! !!04->12
|
| 4730 |
|
|
d=100000 --!00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!} !!->100000
|
| 4731 |
|
|
d=000000 --!
|
| 4732 |
|
|
d=000012 --! !!04->12
|
| 4733 |
|
|
# left shifts of negative numbers
|
| 4734 |
|
|
d=177777 --!00, 177777, 177777, 000001, 177777, 177776, 11
|
| 4735 |
|
|
d=177776 --!
|
| 4736 |
|
|
d=000011 --!
|
| 4737 |
|
|
d=177777 --!00, 177777, 177777, 000002, 177777, 177774, 11
|
| 4738 |
|
|
d=177774 --!
|
| 4739 |
|
|
d=000011 --!
|
| 4740 |
|
|
#37360
|
| 4741 |
|
|
d=140000 --!00, 177777, 177777, 000036, 140000, 000000, 11
|
| 4742 |
|
|
d=000000 --!
|
| 4743 |
|
|
d=000011 --!
|
| 4744 |
|
|
d=100000 --!00, 177777, 177777, 000037, 100000, 000000, 11
|
| 4745 |
|
|
d=000000 --!
|
| 4746 |
|
|
d=000011 --!
|
| 4747 |
|
|
d=000000 --!00, 177777, 177776, 000037, 000000, 000000, 07
|
| 4748 |
|
|
d=000000 --!
|
| 4749 |
|
|
d=000007 --!
|
| 4750 |
|
|
d=000000 --!00, 177777, 177774, 000037, 000000, 000000, 06
|
| 4751 |
|
|
d=000000 --!
|
| 4752 |
|
|
d=000006 --!
|
| 4753 |
|
|
#37410
|
| 4754 |
|
|
d=177777 --!00, 177777, 177777, 177701, 177777, 177776, 11
|
| 4755 |
|
|
d=177776 --!
|
| 4756 |
|
|
d=000011 --!
|
| 4757 |
|
|
d=100000 --!00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!} !!->100000
|
| 4758 |
|
|
d=000000 --! !!->00000
|
| 4759 |
|
|
d=000011 --!
|
| 4760 |
|
|
d=140000 --!00, 177777, 177777, 001036, 140000, 000000, 11
|
| 4761 |
|
|
d=000000 --!
|
| 4762 |
|
|
d=000011 --!
|
| 4763 |
|
|
#-----------------------------------------------------------------------------
|
| 4764 |
|
|
C Setup code 42 [base 12600] (systematic ASHC odd test)
|
| 4765 |
|
|
#
|
| 4766 |
|
|
wal 012600 -- code:
|
| 4767 |
|
|
bwm 15
|
| 4768 |
|
|
000230 -- spl 0
|
| 4769 |
|
|
016401 -- L1: mov 2(r4),r1
|
| 4770 |
|
|
000002
|
| 4771 |
|
|
011412 -- mov (r4),(r2)
|
| 4772 |
|
|
073164 -- ashc 4(r4),r1
|
| 4773 |
|
|
000004
|
| 4774 |
|
|
011265 -- mov (r2),2(r5)
|
| 4775 |
|
|
000002
|
| 4776 |
|
|
#12620
|
| 4777 |
|
|
010115 -- mov r1,(r5)
|
| 4778 |
|
|
062704 -- add #6,r4
|
| 4779 |
|
|
000006
|
| 4780 |
|
|
062705 -- add #4,r5
|
| 4781 |
|
|
000004
|
| 4782 |
|
|
077315 -- sob r3,L1
|
| 4783 |
|
|
000000 -- halt
|
| 4784 |
|
|
#
|
| 4785 |
|
|
C Exec code 42 (systematic ASHC odd test)
|
| 4786 |
|
|
C Exec test 42.1: data adapted from ashc.s11 code of Begemot p11-2.10c
|
| 4787 |
|
|
#
|
| 4788 |
|
|
# The {} comments are original comments from Harti Brandt
|
| 4789 |
|
|
# Annotations starting with !! indicated mods for W11
|
| 4790 |
|
|
# Note, that the W11 does not have the microcode bugs of the J11 !
|
| 4791 |
|
|
#
|
| 4792 |
|
|
wal 036000 -- setup test vector:
|
| 4793 |
|
|
# test shift amount 0
|
| 4794 |
|
|
bwm 165
|
| 4795 |
|
|
000000 -- 00, 000000, 000000, 000000, 04
|
| 4796 |
|
|
000000 --
|
| 4797 |
|
|
000000 --
|
| 4798 |
|
|
000017 -- 17, 000000, 000000, 000000, 04
|
| 4799 |
|
|
000000 --
|
| 4800 |
|
|
000000 --
|
| 4801 |
|
|
000017 -- 17, 100001, 000000, 100001, 10
|
| 4802 |
|
|
100001 --
|
| 4803 |
|
|
000000 --
|
| 4804 |
|
|
000017 -- 17, 040001, 000000, 040001, 00
|
| 4805 |
|
|
040001 --
|
| 4806 |
|
|
000000 --
|
| 4807 |
|
|
000017 -- 17, 040001, 177700, 040001, 00
|
| 4808 |
|
|
040001 --
|
| 4809 |
|
|
177700 --
|
| 4810 |
|
|
# right rotate positive values
|
| 4811 |
|
|
000000 -- 00, 000000, 000077, 000000, 04
|
| 4812 |
|
|
000000 --
|
| 4813 |
|
|
000077 --
|
| 4814 |
|
|
000017 -- 17, 000000, 000077, 000000, 04
|
| 4815 |
|
|
000000 --
|
| 4816 |
|
|
000077 --
|
| 4817 |
|
|
000000 -- 00, 000002, 000077, 000001, 00
|
| 4818 |
|
|
000002 --
|
| 4819 |
|
|
000077 --
|
| 4820 |
|
|
000000 -- 00, 000001, 000077, 100000, 01 {cc is funny!}
|
| 4821 |
|
|
000001 --
|
| 4822 |
|
|
000077 --
|
| 4823 |
|
|
000000 -- 00, 000003, 000076, 140000, 01
|
| 4824 |
|
|
000003 --
|
| 4825 |
|
|
000076 --
|
| 4826 |
|
|
000000 -- 00, 000001, 000076, 040000, 00
|
| 4827 |
|
|
000001 --
|
| 4828 |
|
|
000076 --
|
| 4829 |
|
|
000000 -- 00, 040000, 000060, 040000, 00
|
| 4830 |
|
|
040000 --
|
| 4831 |
|
|
000060 --
|
| 4832 |
|
|
000000 -- 00, 040000, 000043, 000002, 00
|
| 4833 |
|
|
040000 --
|
| 4834 |
|
|
000043 --
|
| 4835 |
|
|
000000 -- 00, 040000, 000042, 000001, 00
|
| 4836 |
|
|
040000 --
|
| 4837 |
|
|
000042 --
|
| 4838 |
|
|
000000 -- 00, 040000, 000041, 000000, 05
|
| 4839 |
|
|
040000 --
|
| 4840 |
|
|
000041 --
|
| 4841 |
|
|
000000 -- 00, 040000, 000040, 000000, 04
|
| 4842 |
|
|
040000 --
|
| 4843 |
|
|
000040 --
|
| 4844 |
|
|
000000 -- 00, 040000, 100037, 000000, 04
|
| 4845 |
|
|
040000 --
|
| 4846 |
|
|
100037 --
|
| 4847 |
|
|
000000 -- 00, 020000, 000043, 000001, 00
|
| 4848 |
|
|
020000 --
|
| 4849 |
|
|
000043 --
|
| 4850 |
|
|
000000 -- 00, 020000, 000042, 000000, 05
|
| 4851 |
|
|
020000 --
|
| 4852 |
|
|
000042 --
|
| 4853 |
|
|
000000 -- 00, 020000, 000041, 000000, 04
|
| 4854 |
|
|
020000 --
|
| 4855 |
|
|
000041 --
|
| 4856 |
|
|
# right rotate negative numbers
|
| 4857 |
|
|
000000 -- 00, 100002, 000077, 040001, 10
|
| 4858 |
|
|
100002 --
|
| 4859 |
|
|
000077 --
|
| 4860 |
|
|
000000 -- 00, 100002, 000076, 120000, 11
|
| 4861 |
|
|
100002 --
|
| 4862 |
|
|
000076 --
|
| 4863 |
|
|
000000 -- 00, 100002, 000075, 050000, 10
|
| 4864 |
|
|
100002 --
|
| 4865 |
|
|
000075 --
|
| 4866 |
|
|
000000 -- 00, 100002, 000061, 000005, 10
|
| 4867 |
|
|
100002 --
|
| 4868 |
|
|
000061 --
|
| 4869 |
|
|
000000 -- 00, 100002, 000060, 100002, 11
|
| 4870 |
|
|
100002 --
|
| 4871 |
|
|
000060 --
|
| 4872 |
|
|
000000 -- 00, 100002, 000057, 140001, 10
|
| 4873 |
|
|
100002 --
|
| 4874 |
|
|
000057 --
|
| 4875 |
|
|
000000 -- 00, 100002, 000056, 160000, 11
|
| 4876 |
|
|
100002 --
|
| 4877 |
|
|
000056 --
|
| 4878 |
|
|
000000 -- 00, 100002, 000055, 170000, 10
|
| 4879 |
|
|
100002 --
|
| 4880 |
|
|
000055 --
|
| 4881 |
|
|
000000 -- 00, 100002, 000042, 177776, 10
|
| 4882 |
|
|
100002 --
|
| 4883 |
|
|
000042 --
|
| 4884 |
|
|
000000 -- 00, 100002, 000041, 177777, 10
|
| 4885 |
|
|
100002 --
|
| 4886 |
|
|
000041 --
|
| 4887 |
|
|
000000 -- 00, 100002, 000040, 177777, 11
|
| 4888 |
|
|
100002 --
|
| 4889 |
|
|
000040 --
|
| 4890 |
|
|
000000 -- 00, 100002, 040037, 177777, 11
|
| 4891 |
|
|
100002 --
|
| 4892 |
|
|
040037 --
|
| 4893 |
|
|
# left rotate positive numbers
|
| 4894 |
|
|
000000 -- 00, 000000, 000001, 000000, 04
|
| 4895 |
|
|
000000 --
|
| 4896 |
|
|
000001 --
|
| 4897 |
|
|
000000 -- 17, 000000, 000001, 000000, 04
|
| 4898 |
|
|
000000 --
|
| 4899 |
|
|
000001 --
|
| 4900 |
|
|
000000 -- 00, 000001, 000007, 000200, 00
|
| 4901 |
|
|
000001 --
|
| 4902 |
|
|
000007 --
|
| 4903 |
|
|
000000 -- 00, 000001, 000016, 040000, 00
|
| 4904 |
|
|
000001 --
|
| 4905 |
|
|
000016 --
|
| 4906 |
|
|
000000 -- 00, 000001, 000017, 100000, 12
|
| 4907 |
|
|
000001 --
|
| 4908 |
|
|
000017 --
|
| 4909 |
|
|
000000 -- 00, 000001, 000020, 000000, 03
|
| 4910 |
|
|
000001 --
|
| 4911 |
|
|
000020 --
|
| 4912 |
|
|
000000 -- 00, 000001, 000021, 000000, 02
|
| 4913 |
|
|
000001 --
|
| 4914 |
|
|
000021 --
|
| 4915 |
|
|
000000 -- 00, 000001, 000036, 000000, 02
|
| 4916 |
|
|
000001 --
|
| 4917 |
|
|
000036 --
|
| 4918 |
|
|
000000 -- 00, 000001, 000037, 000000, 12
|
| 4919 |
|
|
000001 --
|
| 4920 |
|
|
000037 --
|
| 4921 |
|
|
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
|
| 4922 |
|
|
000001 --
|
| 4923 |
|
|
000040 --
|
| 4924 |
|
|
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
|
| 4925 |
|
|
000001 --
|
| 4926 |
|
|
010037 --
|
| 4927 |
|
|
# left rotate negative numbers
|
| 4928 |
|
|
000000 -- 00, 100001, 000001, 000002, 03
|
| 4929 |
|
|
100001 --
|
| 4930 |
|
|
000001 --
|
| 4931 |
|
|
000000 -- 00, 140001, 000001, 100002, 11
|
| 4932 |
|
|
140001 --
|
| 4933 |
|
|
000001 --
|
| 4934 |
|
|
000000 -- 00, 140001, 000002, 000004, 03
|
| 4935 |
|
|
140001 --
|
| 4936 |
|
|
000002 --
|
| 4937 |
|
|
000000 -- 00, 140001, 000016, 040000, 02
|
| 4938 |
|
|
140001 --
|
| 4939 |
|
|
000016 --
|
| 4940 |
|
|
000000 -- 00, 140001, 000017, 100000, 12
|
| 4941 |
|
|
140001 --
|
| 4942 |
|
|
000017 --
|
| 4943 |
|
|
000000 -- 00, 140001, 000020, 000000, 13
|
| 4944 |
|
|
140001 --
|
| 4945 |
|
|
000020 --
|
| 4946 |
|
|
000000 -- 00, 140001, 000021, 000000, 13
|
| 4947 |
|
|
140001 --
|
| 4948 |
|
|
000021 --
|
| 4949 |
|
|
000000 -- 00, 140001, 000022, 000000, 03
|
| 4950 |
|
|
140001 --
|
| 4951 |
|
|
000022 --
|
| 4952 |
|
|
000000 -- 00, 140001, 000023, 000000, 02
|
| 4953 |
|
|
140001 --
|
| 4954 |
|
|
000023 --
|
| 4955 |
|
|
000000 -- 00, 140002, 000035, 000000, 02
|
| 4956 |
|
|
140002 --
|
| 4957 |
|
|
000035 --
|
| 4958 |
|
|
000000 -- 00, 140002, 000036, 000000, 12
|
| 4959 |
|
|
140002 --
|
| 4960 |
|
|
000036 --
|
| 4961 |
|
|
000000 -- 00, 140002, 000037, 000000, 07
|
| 4962 |
|
|
140002 --
|
| 4963 |
|
|
000037 --
|
| 4964 |
|
|
#----
|
| 4965 |
|
|
wr2 177776 -- r2=177776 -> psw
|
| 4966 |
|
|
wr3 000067 -- r3=67 (55.) -> test count
|
| 4967 |
|
|
wr4 036000 -- r4=36000 -> input area
|
| 4968 |
|
|
wr5 037000 -- r5=37000 -> output area
|
| 4969 |
|
|
wsp 001400 -- sp=1400
|
| 4970 |
30 |
wfjm |
cres
|
| 4971 |
2 |
wfjm |
stapc 012600 -- start @ 12600
|
| 4972 |
|
|
wtgo
|
| 4973 |
|
|
rpc d=012636 -- ! pc
|
| 4974 |
|
|
rr3 d=000000 -- ! r3=0
|
| 4975 |
|
|
rr4 d=036512 -- ! r4=36512
|
| 4976 |
|
|
rr5 d=037334 -- ! r5=37334
|
| 4977 |
|
|
wal 037000 --
|
| 4978 |
|
|
# test shift amount 0
|
| 4979 |
|
|
brm 110
|
| 4980 |
|
|
d=000000 --!00, 000000, 000000, 000000, 04
|
| 4981 |
|
|
d=000004 --!
|
| 4982 |
|
|
d=000000 --!17, 000000, 000000, 000000, 04
|
| 4983 |
|
|
d=000004 --!
|
| 4984 |
|
|
d=100001 --!17, 100001, 000000, 100001, 10
|
| 4985 |
|
|
d=000010 --!
|
| 4986 |
|
|
d=040001 --!17, 040001, 000000, 040001, 00
|
| 4987 |
|
|
d=000000 --!
|
| 4988 |
|
|
#37020
|
| 4989 |
|
|
d=040001 --!17, 040001, 177700, 040001, 00
|
| 4990 |
|
|
d=000000 --!
|
| 4991 |
|
|
# right rotate positive values
|
| 4992 |
|
|
d=000000 --!00, 000000, 000077, 000000, 04
|
| 4993 |
|
|
d=000004 --!
|
| 4994 |
|
|
d=000000 --!17, 000000, 000077, 000000, 04
|
| 4995 |
|
|
d=000004 --!
|
| 4996 |
|
|
d=000001 --!00, 000002, 000077, 000001, 00
|
| 4997 |
|
|
d=000000 --!
|
| 4998 |
|
|
#37040
|
| 4999 |
|
|
d=100000 --!00, 000001, 000077, 100000, 01 {cc is funny!}
|
| 5000 |
|
|
d=000001 --!
|
| 5001 |
|
|
d=140000 --!00, 000003, 000076, 140000, 01
|
| 5002 |
|
|
d=000001 --!
|
| 5003 |
|
|
d=040000 --!00, 000001, 000076, 040000, 00
|
| 5004 |
|
|
d=000000 --!
|
| 5005 |
|
|
d=040000 --!00, 040000, 000060, 040000, 00
|
| 5006 |
|
|
d=000000 --!
|
| 5007 |
|
|
#37060
|
| 5008 |
|
|
d=000002 --!00, 040000, 000043, 000002, 00
|
| 5009 |
|
|
d=000000 --!
|
| 5010 |
|
|
d=000001 --!00, 040000, 000042, 000001, 00
|
| 5011 |
|
|
d=000000 --!
|
| 5012 |
|
|
d=000000 --!00, 040000, 000041, 000000, 05
|
| 5013 |
|
|
d=000005 --!
|
| 5014 |
|
|
d=000000 --!00, 040000, 000040, 000000, 04
|
| 5015 |
|
|
d=000004 --!
|
| 5016 |
|
|
#37100
|
| 5017 |
|
|
d=000000 --!00, 040000, 100037, 000000, 04
|
| 5018 |
|
|
d=000006 --! !!04->06
|
| 5019 |
|
|
d=000001 --!00, 020000, 000043, 000001, 00
|
| 5020 |
|
|
d=000000 --!
|
| 5021 |
|
|
d=000000 --!00, 020000, 000042, 000000, 05
|
| 5022 |
|
|
d=000005 --!
|
| 5023 |
|
|
d=000000 --!00, 020000, 000041, 000000, 04
|
| 5024 |
|
|
d=000004 --!
|
| 5025 |
|
|
#37120 # right rotate negative numbers
|
| 5026 |
|
|
d=040001 --!00, 100002, 000077, 040001, 10
|
| 5027 |
|
|
d=000010 --!
|
| 5028 |
|
|
d=120000 --!00, 100002, 000076, 120000, 11
|
| 5029 |
|
|
d=000011 --!
|
| 5030 |
|
|
d=050000 --!00, 100002, 000075, 050000, 10
|
| 5031 |
|
|
d=000010 --!
|
| 5032 |
|
|
d=000005 --!00, 100002, 000061, 000005, 10
|
| 5033 |
|
|
d=000010 --!
|
| 5034 |
|
|
#37140
|
| 5035 |
|
|
d=100002 --!00, 100002, 000060, 100002, 11
|
| 5036 |
|
|
d=000011 --!
|
| 5037 |
|
|
d=140001 --!00, 100002, 000057, 140001, 10
|
| 5038 |
|
|
d=000010 --!
|
| 5039 |
|
|
d=160000 --!00, 100002, 000056, 160000, 11
|
| 5040 |
|
|
d=000011 --!
|
| 5041 |
|
|
d=170000 --!00, 100002, 000055, 170000, 10
|
| 5042 |
|
|
d=000010 --!
|
| 5043 |
|
|
#37160
|
| 5044 |
|
|
d=177776 --!00, 100002, 000042, 177776, 10
|
| 5045 |
|
|
d=000010 --!
|
| 5046 |
|
|
d=177777 --!00, 100002, 000041, 177777, 10
|
| 5047 |
|
|
d=000010 --!
|
| 5048 |
|
|
d=177777 --!00, 100002, 000040, 177777, 11
|
| 5049 |
|
|
d=000011 --!
|
| 5050 |
|
|
d=000000 --!00, 100002, 040037, 177777, 11 !!->000000
|
| 5051 |
|
|
d=000007 --! !!11->07
|
| 5052 |
|
|
#37200 # left rotate positive numbers
|
| 5053 |
|
|
d=000000 --!00, 000000, 000001, 000000, 04
|
| 5054 |
|
|
d=000004 --!
|
| 5055 |
|
|
d=000000 --!17, 000000, 000001, 000000, 04
|
| 5056 |
|
|
d=000004 --!
|
| 5057 |
|
|
d=000200 --!00, 000001, 000007, 000200, 00
|
| 5058 |
|
|
d=000000 --!
|
| 5059 |
|
|
d=040000 --!00, 000001, 000016, 040000, 00
|
| 5060 |
|
|
d=000000 --!
|
| 5061 |
|
|
#37220
|
| 5062 |
|
|
d=100000 --!00, 000001, 000017, 100000, 12
|
| 5063 |
|
|
d=000012 --!
|
| 5064 |
|
|
d=000000 --!00, 000001, 000020, 000000, 03
|
| 5065 |
|
|
d=000003 --!
|
| 5066 |
|
|
d=000000 --!00, 000001, 000021, 000000, 02
|
| 5067 |
|
|
d=000002 --!
|
| 5068 |
|
|
d=000000 --!00, 000001, 000036, 000000, 02
|
| 5069 |
|
|
d=000002 --!
|
| 5070 |
|
|
#37240
|
| 5071 |
|
|
d=000000 --!00, 000001, 000037, 000000, 12
|
| 5072 |
|
|
d=000012 --!
|
| 5073 |
|
|
d=000000 --!00, 000001, 000040, 000000, 04 {right shift!}
|
| 5074 |
|
|
d=000004 --!
|
| 5075 |
|
|
d=000000 --!00, 000001, 010037, 000000, 04 {right shift!}
|
| 5076 |
|
|
d=000012 --! !!04->12
|
| 5077 |
|
|
# left rotate negative numbers
|
| 5078 |
|
|
d=000002 --!00, 100001, 000001, 000002, 03
|
| 5079 |
|
|
d=000003 --!
|
| 5080 |
|
|
#37260
|
| 5081 |
|
|
d=100002 --!00, 140001, 000001, 100002, 11
|
| 5082 |
|
|
d=000011 --!
|
| 5083 |
|
|
d=000004 --!00, 140001, 000002, 000004, 03
|
| 5084 |
|
|
d=000003 --!
|
| 5085 |
|
|
d=040000 --!00, 140001, 000016, 040000, 02
|
| 5086 |
|
|
d=000002 --!
|
| 5087 |
|
|
d=100000 --!00, 140001, 000017, 100000, 12
|
| 5088 |
|
|
d=000012 --!
|
| 5089 |
|
|
#37300
|
| 5090 |
|
|
d=000000 --!00, 140001, 000020, 000000, 13
|
| 5091 |
|
|
d=000013 --!
|
| 5092 |
|
|
d=000000 --!00, 140001, 000021, 000000, 13
|
| 5093 |
|
|
d=000013 --!
|
| 5094 |
|
|
d=000000 --!00, 140001, 000022, 000000, 03
|
| 5095 |
|
|
d=000003 --!
|
| 5096 |
|
|
d=000000 --!00, 140001, 000023, 000000, 02
|
| 5097 |
|
|
d=000002 --!
|
| 5098 |
|
|
#37320
|
| 5099 |
|
|
d=000000 --!00, 140002, 000035, 000000, 02
|
| 5100 |
|
|
d=000002 --!
|
| 5101 |
|
|
d=000000 --!00, 140002, 000036, 000000, 12
|
| 5102 |
|
|
d=000012 --!
|
| 5103 |
|
|
d=000000 --!00, 140002, 000037, 000000, 07
|
| 5104 |
|
|
d=000007 --!
|
| 5105 |
|
|
#-----------------------------------------------------------------------------
|
| 5106 |
|
|
C Setup code 43 [base 12700] (Begemot MARK instruction test)
|
| 5107 |
|
|
# test data and code adapted from Mark.s11 code of Begemot p11-2.10c
|
| 5108 |
|
|
#
|
| 5109 |
|
|
wal 012700 -- code test 1: (basics)
|
| 5110 |
|
|
bwm 14
|
| 5111 |
|
|
012705 -- mov #77077,r5 ; cookie
|
| 5112 |
|
|
077077
|
| 5113 |
|
|
010546 -- mov r5,-(sp) ; push r5
|
| 5114 |
|
|
012746 -- mov #12,-(sp) ; parameter 1
|
| 5115 |
|
|
000012
|
| 5116 |
|
|
012746 -- mov #23,-(sp) ; parameter 2
|
| 5117 |
|
|
000023
|
| 5118 |
|
|
012746 -- mov #mark+2,-(sp) ; now the mark instruction
|
| 5119 |
|
|
#12720
|
| 5120 |
|
|
006402
|
| 5121 |
|
|
010605 -- mov sp,r5 ; let r5 point to mark instruction
|
| 5122 |
|
|
004737 -- jsr pc,subr ; call subroutine
|
| 5123 |
|
|
012770
|
| 5124 |
|
|
000240 -- noop
|
| 5125 |
|
|
000000 -- halt
|
| 5126 |
|
|
#-----
|
| 5127 |
|
|
wal 012740 -- code test 2: (MARK with max. # of args)
|
| 5128 |
|
|
bwm 10
|
| 5129 |
|
|
010546 -- mov r5, -(sp) ; push r5
|
| 5130 |
|
|
162706 -- sub #2*77, sp ; max number
|
| 5131 |
|
|
000176
|
| 5132 |
|
|
012746 -- mov #mark+77, -(sp) ; the mark instruction
|
| 5133 |
|
|
006477
|
| 5134 |
|
|
010605 -- mov sp, r5 ; let r5 point to mark instruction
|
| 5135 |
|
|
004737 -- jsr pc, subr ; call subroutine
|
| 5136 |
|
|
012770
|
| 5137 |
|
|
#12760
|
| 5138 |
|
|
000240 -- noop
|
| 5139 |
|
|
000000 -- halt
|
| 5140 |
|
|
#-----
|
| 5141 |
|
|
wal 012770 -- code (procedure):
|
| 5142 |
|
|
wmi 000205 -- subr: rts r5
|
| 5143 |
|
|
#-----
|
| 5144 |
|
|
C Exec code 43 (Begemot MARK test)
|
| 5145 |
|
|
C Exec test 43.1 (basics)
|
| 5146 |
|
|
# D RE RQ FU DAT
|
| 5147 |
|
|
wsp 001400 -- sp=1400
|
| 5148 |
30 |
wfjm |
cres
|
| 5149 |
2 |
wfjm |
stapc 012700 -- start @ 12700
|
| 5150 |
|
|
wtgo
|
| 5151 |
|
|
rpc d=012734 -- ! pc
|
| 5152 |
|
|
rr5 d=077077 -- ! r5
|
| 5153 |
|
|
rsp d=001400 -- ! sp
|
| 5154 |
|
|
wal 001366 --
|
| 5155 |
|
|
brm 5
|
| 5156 |
|
|
d=012730 -- ! mem(1366)
|
| 5157 |
|
|
d=006402 -- ! mem(1370)
|
| 5158 |
|
|
d=000023 -- ! mem(1372)
|
| 5159 |
|
|
d=000012 -- ! mem(1374)
|
| 5160 |
|
|
d=077077 -- ! mem(1376)
|
| 5161 |
|
|
#----
|
| 5162 |
|
|
C Exec test 43.2 (MARK with max. # of args)
|
| 5163 |
|
|
# D RE RQ FU DAT
|
| 5164 |
|
|
wsp 001400 -- sp=1400
|
| 5165 |
30 |
wfjm |
cres
|
| 5166 |
2 |
wfjm |
stapc 012740 -- start @ 12740
|
| 5167 |
|
|
wtgo
|
| 5168 |
|
|
rpc d=012764 -- ! pc
|
| 5169 |
|
|
rr5 d=077077 -- ! r5
|
| 5170 |
|
|
rsp d=001400 -- ! sp
|
| 5171 |
|
|
#-----------------------------------------------------------------------------
|
| 5172 |
|
|
C Setup code 44 [base 13000] (Implementation variations)
|
| 5173 |
|
|
# test various PDP11 implementation variations (DCJ11 user guide, table C-1)
|
| 5174 |
|
|
#
|
| 5175 |
|
|
wal 013000 -- code: (to be single stepped mostly)
|
| 5176 |
|
|
bwm 22
|
| 5177 |
|
|
010424 -- mov r4,(r4)+ ; case 1 and 2
|
| 5178 |
|
|
010444 -- mov r4,-(r4)
|
| 5179 |
|
|
010764 -- mov pc,2(r4)
|
| 5180 |
|
|
000002
|
| 5181 |
|
|
000124 -- jmp (r4)+
|
| 5182 |
|
|
000104 -- jmp r4
|
| 5183 |
|
|
000304 -- swab r4
|
| 5184 |
|
|
005214 -- inc (r4)
|
| 5185 |
|
|
#13020
|
| 5186 |
|
|
000006 -- rtt
|
| 5187 |
|
|
000000 -- halt
|
| 5188 |
|
|
000002 -- rti
|
| 5189 |
|
|
000000 -- halt
|
| 5190 |
|
|
010011 -- mov r0,(r1)
|
| 5191 |
|
|
010046 -- mov r0,-(sp)
|
| 5192 |
|
|
000114 -- jmp (r4)
|
| 5193 |
|
|
010021 -- mov r0,(r1)+
|
| 5194 |
|
|
#13040
|
| 5195 |
|
|
012100 -- mov (r1)+,r0
|
| 5196 |
|
|
005221 -- inc (r1)+
|
| 5197 |
|
|
106621 -- mtpd (r1)+
|
| 5198 |
|
|
106506 -- mfpd sp
|
| 5199 |
|
|
106606 -- mtpd sp
|
| 5200 |
|
|
000003 -- bpt
|
| 5201 |
|
|
#-----
|
| 5202 |
|
|
wal 013070 -- code: (target for rtt,rti tests)
|
| 5203 |
|
|
bwm 2
|
| 5204 |
|
|
000240 -- noop
|
| 5205 |
|
|
000000 -- halt
|
| 5206 |
|
|
#-----
|
| 5207 |
|
|
C Exec code 44 (Implementation variations)
|
| 5208 |
|
|
C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source
|
| 5209 |
|
|
#
|
| 5210 |
30 |
wfjm |
cres -- console reset
|
| 5211 |
2 |
wfjm |
wps 000000 -- clear psw
|
| 5212 |
|
|
wr4 001600 -- r4=1600
|
| 5213 |
|
|
wsp 001400 -- sp=1400
|
| 5214 |
|
|
wpc 013000 -- pc=13000
|
| 5215 |
|
|
step -- step (mov r4,(r4)+)
|
| 5216 |
|
|
rpc d=013002 -- ! pc=13002
|
| 5217 |
|
|
rr4 d=001602 -- ! r4=1602
|
| 5218 |
|
|
wal 001600 -- check target location
|
| 5219 |
|
|
rmi d=001600 -- ! ; initial content of R expected for 11/70
|
| 5220 |
|
|
#
|
| 5221 |
|
|
C test 44.2: OPR R,-(R) : decremented before {J11} or after {70} use as source
|
| 5222 |
|
|
#
|
| 5223 |
|
|
wr4 001600 -- r4=1600
|
| 5224 |
|
|
wsp 001400 -- sp=1400
|
| 5225 |
|
|
wpc 013002 -- pc=13002
|
| 5226 |
|
|
step -- step (mov r4,-(r4))
|
| 5227 |
|
|
rpc d=013004 -- ! pc=13004
|
| 5228 |
|
|
rr4 d=001576 -- ! r4=1576
|
| 5229 |
|
|
wal 001600 -- check target location
|
| 5230 |
|
|
rmi d=001600 -- ! ; initial content of R expected for 11/70
|
| 5231 |
|
|
#
|
| 5232 |
|
|
C test 44.3: OPR PC,A(R) : store PC+2 {70} or PC+4 {J11}
|
| 5233 |
|
|
#
|
| 5234 |
|
|
wr4 001600 -- r4=1600
|
| 5235 |
|
|
wsp 001400 -- sp=1400
|
| 5236 |
|
|
wpc 013004 -- pc=13004
|
| 5237 |
|
|
step -- step (mov pc,2(r4))
|
| 5238 |
|
|
rpc d=013010 -- ! pc=13010
|
| 5239 |
|
|
wal 001602 -- check target location
|
| 5240 |
|
|
rmi d=013006 -- ! ; PC+2 expected for 11/70
|
| 5241 |
|
|
#
|
| 5242 |
|
|
C test 44.4: JMP (R)+ : R used {70;J11} or R+2 used {05,10,15,20}
|
| 5243 |
|
|
#
|
| 5244 |
|
|
wr4 013074 -- r4=13074
|
| 5245 |
|
|
wsp 001400 -- sp=1400
|
| 5246 |
|
|
wpc 013010 -- pc=13010
|
| 5247 |
|
|
step -- step (jmp (r4)+)
|
| 5248 |
|
|
rpc d=013074 -- ! pc=13074 ; R expected for 11/70
|
| 5249 |
|
|
rr4 d=013076 -- ! r4=13076
|
| 5250 |
|
|
#
|
| 5251 |
|
|
C test 44.5: JMP R : traps to 10 {44,45,70;J11} or 4 {all others}
|
| 5252 |
|
|
C Note: J11 doc is wrong, 11/70 traps 10, not 4, as stated
|
| 5253 |
|
|
#
|
| 5254 |
|
|
wal 177766 -- clear CPUERR
|
| 5255 |
|
|
wm 000000 --
|
| 5256 |
|
|
wr4 000000 -- r4=0
|
| 5257 |
|
|
wsp 001400 -- sp=1400
|
| 5258 |
|
|
wpc 013012 -- pc=13012
|
| 5259 |
|
|
step -- step (jmp r4) [[s:2]]
|
| 5260 |
|
|
rpc d=000012 -- ! pc=12 ; trap 10 expected for 11/70 [[s:10]]
|
| 5261 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5262 |
|
|
wal 177766 -- check CPUERR
|
| 5263 |
|
|
rm d=000000 -- ! CPUERR: no bit set
|
| 5264 |
|
|
wm 000000 -- clear CPUERR
|
| 5265 |
|
|
#
|
| 5266 |
|
|
C test 44.6: SWAB does not change V {15,20} or clears V {all others}
|
| 5267 |
|
|
#
|
| 5268 |
|
|
wr4 000300 -- r4=3000
|
| 5269 |
|
|
wsp 001400 -- sp=1400
|
| 5270 |
|
|
wpc 013014 -- pc=13014
|
| 5271 |
|
|
wps 000017 -- psw: set all cc flags in psw
|
| 5272 |
|
|
step -- step (swab r4)
|
| 5273 |
|
|
rpc d=013016 -- ! pc=13074
|
| 5274 |
|
|
rr4 d=140000 -- ! r4=140000
|
| 5275 |
|
|
rps d=000004 -- ! psw: Z=1 ; clear V expected for 11/70
|
| 5276 |
|
|
#
|
| 5277 |
|
|
C test 44.7: CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10}
|
| 5278 |
|
|
#
|
| 5279 |
|
|
wr4 177700 -- r4=177700
|
| 5280 |
|
|
wsp 001400 -- sp=1400
|
| 5281 |
|
|
wpc 013016 -- pc=13016
|
| 5282 |
|
|
step -- step (inc (r4)) [[s:2]]
|
| 5283 |
|
|
rpc d=000006 -- ! pc=6 ; trap 4 expected for 11/70 [[s:10]]
|
| 5284 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5285 |
|
|
wal 177766 -- check CPUERR
|
| 5286 |
|
|
rm d=000020 -- ! CPUERR: (iobto=1)
|
| 5287 |
|
|
wm 000000 -- clear CPUERR
|
| 5288 |
|
|
#
|
| 5289 |
|
|
C test 44.10: If RTT sets T bit, trap occurs after instr. following RTT {70,J11}
|
| 5290 |
|
|
#
|
| 5291 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
| 5292 |
|
|
bwm 2
|
| 5293 |
|
|
013070 -- start address (points to: noop, halt)
|
| 5294 |
|
|
000020 -- set T flag in PSW
|
| 5295 |
|
|
wsp 001374 -- sp=1374
|
| 5296 |
|
|
wpc 013020 -- pc=13020
|
| 5297 |
30 |
wfjm |
sta -- start (rtt)
|
| 5298 |
2 |
wfjm |
wtgo
|
| 5299 |
|
|
rpc d=000020 -- ! pc=20 ; T-trap executed
|
| 5300 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5301 |
|
|
wal 001374 -- check stack
|
| 5302 |
|
|
brm 2
|
| 5303 |
|
|
d=013072 -- trap address: address after noop expected for 11/70
|
| 5304 |
|
|
d=000020 -- PSW
|
| 5305 |
30 |
wfjm |
cres -- console reset (to clear T flag)
|
| 5306 |
2 |
wfjm |
#
|
| 5307 |
|
|
C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11}
|
| 5308 |
|
|
#
|
| 5309 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
| 5310 |
|
|
bwm 2
|
| 5311 |
|
|
013070 -- start address (points to: noop, halt)
|
| 5312 |
|
|
000020 -- set T flag in PSW
|
| 5313 |
|
|
wsp 001374 -- sp=1374
|
| 5314 |
|
|
wpc 013024 -- pc=13024
|
| 5315 |
30 |
wfjm |
sta -- start (rti)
|
| 5316 |
2 |
wfjm |
wtgo
|
| 5317 |
|
|
rpc d=000020 -- ! pc=20 ; T-trap executed
|
| 5318 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5319 |
|
|
wal 001374 -- check stack
|
| 5320 |
|
|
brm 2
|
| 5321 |
|
|
d=013070 -- trap address: address of noop expected for 11/70
|
| 5322 |
|
|
d=000020 -- PSW
|
| 5323 |
30 |
wfjm |
cres -- console reset (to clear T flag)
|
| 5324 |
2 |
wfjm |
#
|
| 5325 |
|
|
C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit
|
| 5326 |
|
|
#
|
| 5327 |
|
|
wr0 000030 -- r0=30 (set T bit, N also)
|
| 5328 |
|
|
wr1 177776 -- r1=177776 (PSW address)
|
| 5329 |
|
|
wsp 001400 -- sp=1400
|
| 5330 |
|
|
wpc 013030 -- pc=13030
|
| 5331 |
|
|
step -- step (mov r0,(r1))
|
| 5332 |
|
|
rpc d=013032 -- ! pc=13032
|
| 5333 |
|
|
rps d=000010 -- ! psw: T bit not set expected for 11/70
|
| 5334 |
|
|
#
|
| 5335 |
|
|
C test 44.15: odd address using SP causes HALT {<=20} or emmergency stack {>35}
|
| 5336 |
|
|
#
|
| 5337 |
|
|
wsp 001401 -- sp=1401
|
| 5338 |
|
|
wpc 013032 -- pc=13032
|
| 5339 |
|
|
step -- step (mov r0,-(sp)) [[s:2]]
|
| 5340 |
|
|
rpc d=000006 -- ! pc=6 ; trap 4 [[s:13034]]
|
| 5341 |
|
|
rsp d=000000 -- ! sp=0 ; emergency stack expected for 11/70 [[s:4]]
|
| 5342 |
|
|
wal 000000 -- check emergency stack
|
| 5343 |
|
|
brm 2
|
| 5344 |
|
|
d=013034 -- ! PC of abort [[s:0]]
|
| 5345 |
|
|
d=000000 -- ! PS of abort (currently gets lost...)
|
| 5346 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5347 |
2 |
wfjm |
wal 000000 -- clean tainted memory
|
| 5348 |
|
|
bwm 2
|
| 5349 |
|
|
000000 --
|
| 5350 |
|
|
000000 --
|
| 5351 |
|
|
#
|
| 5352 |
|
|
# simh notes:
|
| 5353 |
|
|
# 1. apparently not consistently implemented in simh. SP is set to 4, but
|
| 5354 |
|
|
# interrupt/trap sequence isn't executed. Effectively, simh halt's.
|
| 5355 |
|
|
#
|
| 5356 |
|
|
# for the test 28/29/30x enable MMU and make address 100000 unavailable
|
| 5357 |
|
|
#
|
| 5358 |
|
|
wal 172310 -- kernel I space DR segment 4 (base 100000)
|
| 5359 |
|
|
wmi 077400 -- slf=127; ed=0(up); acf=0 (non resident)
|
| 5360 |
|
|
#
|
| 5361 |
|
|
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40}
|
| 5362 |
|
|
#
|
| 5363 |
30 |
wfjm |
cres
|
| 5364 |
2 |
wfjm |
wal 177572 -- SSR0
|
| 5365 |
|
|
wmi 000001 -- set enable bit
|
| 5366 |
|
|
wr4 100000 -- r4=100000
|
| 5367 |
|
|
wsp 001400 -- sp=1400
|
| 5368 |
|
|
wpc 013034 -- pc=13034
|
| 5369 |
30 |
wfjm |
sta -- start (jmp (r4))
|
| 5370 |
2 |
wfjm |
wtgo
|
| 5371 |
|
|
rpc d=000254 -- ! pc=254 ; trap 240 ; Note: halt is executed, was cont !
|
| 5372 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5373 |
|
|
wal 001374 -- check stack
|
| 5374 |
|
|
brm 2
|
| 5375 |
|
|
d=100002 -- trap address: PC inc'ed expected for 11/70 [[s:100000]]
|
| 5376 |
|
|
d=000340 -- PSW
|
| 5377 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5378 |
2 |
wfjm |
#
|
| 5379 |
|
|
# simh notes:
|
| 5380 |
|
|
# 1. simh reads instruction, later increments PC. Thus PC not inc'ed in simh.
|
| 5381 |
|
|
#
|
| 5382 |
|
|
C test 44.29/30a: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
| 5383 |
|
|
C test for dstw chain (mov r0,(r1)+)
|
| 5384 |
|
|
#
|
| 5385 |
|
|
wal 177572 -- SSR0
|
| 5386 |
|
|
wmi 000001 -- set enable bit
|
| 5387 |
|
|
wr1 100000 -- r1=100000
|
| 5388 |
|
|
wsp 001400 -- sp=1400
|
| 5389 |
|
|
wpc 013036 -- pc=13036
|
| 5390 |
|
|
step -- step (mov r0,(r1)+) [[s:2]]
|
| 5391 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
| 5392 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5393 |
|
|
rr1 d=100002 -- ! r1=100002
|
| 5394 |
|
|
wal 177572 -- check SSR0/1
|
| 5395 |
|
|
brm 2
|
| 5396 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
| 5397 |
|
|
d=000021 -- ! SSR1: ra=1,2
|
| 5398 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5399 |
2 |
wfjm |
#
|
| 5400 |
|
|
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
| 5401 |
|
|
C test for srcr chain (mov (r1)+,r0)
|
| 5402 |
|
|
#
|
| 5403 |
|
|
wal 177572 -- SSR0
|
| 5404 |
|
|
wmi 000001 -- set enable bit
|
| 5405 |
|
|
wr1 100000 -- r1=100000
|
| 5406 |
|
|
wsp 001400 -- sp=1400
|
| 5407 |
|
|
wpc 013040 -- pc=13040
|
| 5408 |
|
|
step -- step ((mov (r1)+,r0) [[s:2]]
|
| 5409 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
| 5410 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5411 |
|
|
rr1 d=100002 -- ! r1=100002
|
| 5412 |
|
|
wal 177572 -- check SSR0/1
|
| 5413 |
|
|
brm 2
|
| 5414 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
| 5415 |
|
|
d=000021 -- ! SSR1: ra=1,2
|
| 5416 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5417 |
2 |
wfjm |
#
|
| 5418 |
|
|
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
| 5419 |
|
|
C test for dstr chain (inc (r1)+)
|
| 5420 |
|
|
#
|
| 5421 |
|
|
wal 177572 -- SSR0
|
| 5422 |
|
|
wmi 000001 -- set enable bit
|
| 5423 |
|
|
wr1 100000 -- r1=100000
|
| 5424 |
|
|
wsp 001400 -- sp=1400
|
| 5425 |
|
|
wpc 013042 -- pc=13042
|
| 5426 |
|
|
step -- step (inc (r1)+) [[s:2]]
|
| 5427 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
| 5428 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5429 |
|
|
rr1 d=100002 -- ! r1=100002
|
| 5430 |
|
|
wal 177572 -- check SSR0/1
|
| 5431 |
|
|
brm 2
|
| 5432 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
| 5433 |
|
|
d=000021 -- ! SSR1: ra=1,2
|
| 5434 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5435 |
2 |
wfjm |
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
| 5436 |
|
|
C test for dsta chain (mtpd (r1)+)
|
| 5437 |
|
|
#
|
| 5438 |
|
|
wal 177572 -- SSR0
|
| 5439 |
|
|
wmi 000001 -- set enable bit
|
| 5440 |
|
|
wr1 100000 -- r1=100000
|
| 5441 |
|
|
wsp 001376 -- sp=1376
|
| 5442 |
|
|
wpc 013044 -- pc=13044
|
| 5443 |
|
|
wal 001376 -- push a word on stack for mtpd
|
| 5444 |
|
|
wmi 123456 --
|
| 5445 |
|
|
step -- step (mtpd (r1)+) [[s:2]]
|
| 5446 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
| 5447 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5448 |
|
|
rr1 d=100002 -- ! r1=100002
|
| 5449 |
|
|
wal 177572 -- check SSR0/1
|
| 5450 |
|
|
brm 2
|
| 5451 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
| 5452 |
|
|
d=010426 -- ! SSR1: rb=1,2; ra=6,2
|
| 5453 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5454 |
2 |
wfjm |
#
|
| 5455 |
|
|
# simh notes:
|
| 5456 |
|
|
# 1. simh first pops, than writes to destination, reversing ra,rb in SSR1
|
| 5457 |
|
|
#
|
| 5458 |
|
|
# now reset MMU to default
|
| 5459 |
|
|
#
|
| 5460 |
|
|
wal 172310 -- kernel I space DR segment 4 (base 100000)
|
| 5461 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
| 5462 |
|
|
#
|
| 5463 |
|
|
C test 44.39: cmode=10 will cause abort {70,J11}, treated as kmode {23,24}
|
| 5464 |
|
|
#
|
| 5465 |
|
|
wal 177572 -- SSR0
|
| 5466 |
|
|
wmi 000001 -- set enable bit
|
| 5467 |
|
|
wr1 001400 -- r1=1400
|
| 5468 |
|
|
wsp 001400 -- sp=1400
|
| 5469 |
|
|
wps 100000 -- psw: set cm=10, pm=00
|
| 5470 |
|
|
wpc 013042 -- pc=13042
|
| 5471 |
|
|
step -- step (inc (r1)+) [[s:2]]
|
| 5472 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250; as expected for 11/70 [[s:254]]
|
| 5473 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5474 |
|
|
rr1 d=001400 -- ! r1=1400
|
| 5475 |
|
|
wal 177572 -- check SSR0/1
|
| 5476 |
|
|
brm 3
|
| 5477 |
|
|
d=140101 -- ! SSR0: (abo_nr=1,abo_l=1,m=10,seg=0,ena=1) [[s:140301]]
|
| 5478 |
|
|
d=000000 -- ! SSR1: ra=none
|
| 5479 |
|
|
d=013042 -- ! SSR2: PC of failed instruction
|
| 5480 |
|
|
wal 001374 -- check stack
|
| 5481 |
|
|
brm 2
|
| 5482 |
|
|
d=013044 -- ! PC after failed instruction [[s:013042]]
|
| 5483 |
|
|
d=100000 -- ! PS
|
| 5484 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg, PSW)
|
| 5485 |
2 |
wfjm |
#
|
| 5486 |
|
|
# simh notes:
|
| 5487 |
|
|
# 1. simh saves PC of failed instruction on stack, not PC after instruction
|
| 5488 |
|
|
#
|
| 5489 |
|
|
C test 44.43: user mode HALT: trap 4 {70} or 10 {others}
|
| 5490 |
|
|
#
|
| 5491 |
|
|
wal 177766 -- check CPUERR ;??? remove if console reset fixed
|
| 5492 |
|
|
wm 000000 -- clear
|
| 5493 |
|
|
wsp 001400 -- sp=1400
|
| 5494 |
|
|
wps 170000 -- psw: set cm=11, pm=11
|
| 5495 |
|
|
wpc 013022 -- pc=13022
|
| 5496 |
|
|
step -- step (halt in user mode) [[s:2]]
|
| 5497 |
|
|
rpc d=000006 -- ! pc=6 ; trap 4; as expected for 11/70 [[s:10]]
|
| 5498 |
|
|
rsp d=001374 -- ! sp=1374
|
| 5499 |
|
|
wal 001374 -- check stack
|
| 5500 |
|
|
brm 2
|
| 5501 |
|
|
d=013024 -- ! PC after failed instruction
|
| 5502 |
|
|
d=170000 -- ! PS
|
| 5503 |
|
|
wal 177766 -- check CPUERR
|
| 5504 |
|
|
rm d=000200 -- ! CPUERR: (illhalt=1)
|
| 5505 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg, PSW)
|
| 5506 |
2 |
wfjm |
#
|
| 5507 |
|
|
C test 44.44: PDR bit<0> implemented {70} or not {others}
|
| 5508 |
|
|
#
|
| 5509 |
|
|
wal 172310 -- kernel I space DR, segment 4
|
| 5510 |
|
|
wm 077401 -- set acf bit 0: slf=127; ed=0(up); acf=1 (r+trap)
|
| 5511 |
|
|
rm d=077401 -- ! check; works as expected for 11/70
|
| 5512 |
|
|
wm 077406 -- restore: slf=127; ed=0(up); acf=6(w/r)
|
| 5513 |
|
|
#
|
| 5514 |
|
|
C test 44.45: PDR bit<7>(AIB any access) implemented {70} or not {others}
|
| 5515 |
|
|
#
|
| 5516 |
|
|
wal 172300 -- kernel I space DR, reset segment 0 and 1
|
| 5517 |
|
|
bwm 2
|
| 5518 |
|
|
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
|
| 5519 |
|
|
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
|
| 5520 |
|
|
wal 172300 -- check kernel I space DR, segment 0 and 1
|
| 5521 |
|
|
brm 2
|
| 5522 |
|
|
d=077404 -- !
|
| 5523 |
|
|
d=077404 -- !
|
| 5524 |
|
|
wal 177572 -- SSR0
|
| 5525 |
|
|
wmi 000001 -- set enable bit
|
| 5526 |
|
|
wr0 123456 -- r0=123456
|
| 5527 |
|
|
wr1 030000 -- r1=30000
|
| 5528 |
|
|
wsp 001400 -- sp=1400
|
| 5529 |
|
|
wpc 013030 -- pc=13030
|
| 5530 |
|
|
step -- step (mov r0,(r1))
|
| 5531 |
|
|
rpc d=013032 -- ! pc=next
|
| 5532 |
|
|
rsp d=001400 -- ! sp=1400
|
| 5533 |
|
|
wal 030000 -- check target memory, untaint
|
| 5534 |
|
|
rm d=123456 -- !
|
| 5535 |
|
|
wm 000000 --
|
| 5536 |
|
|
wal 172300 -- check kernel I space DR, segment 0 and 1
|
| 5537 |
|
|
brm 2
|
| 5538 |
|
|
d=077604 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=10 (A=1,W=0)
|
| 5539 |
|
|
d=077704 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=11 (A=1,W=1)
|
| 5540 |
|
|
wal 172300 -- kernel I space DR, reset segment 0 and 1
|
| 5541 |
|
|
bwm 2
|
| 5542 |
|
|
077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 5543 |
|
|
077406 -- slf=127; ed=0(up); acf=6(w/r)
|
| 5544 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5545 |
2 |
wfjm |
#
|
| 5546 |
|
|
C test 44.46: Full PAR implemented {44,70,J11} or not {others}
|
| 5547 |
|
|
#
|
| 5548 |
|
|
wal 172350 -- kernel I space AR, segment 4
|
| 5549 |
|
|
wm 177777 -- set all bits
|
| 5550 |
|
|
rm d=177777 -- ! check; works as expected for 11/70
|
| 5551 |
|
|
wm 001000 -- restore: 1000 100000 base
|
| 5552 |
|
|
#
|
| 5553 |
|
|
C test 44.47: MMR0<9>(mmu trap) implemented {70} or not {others}
|
| 5554 |
|
|
#
|
| 5555 |
|
|
wal 177572 -- SSR0
|
| 5556 |
|
|
wm 001000 -- set trap enable
|
| 5557 |
|
|
rm d=001000 -- ! check; works as expected for 11/70
|
| 5558 |
|
|
wm 000000 -- restore
|
| 5559 |
|
|
#
|
| 5560 |
|
|
C test 44.48: MMR3<2:0>(D space) implemented {44,70,J11} or not {others}
|
| 5561 |
|
|
#
|
| 5562 |
|
|
wal 172516 -- SSR3
|
| 5563 |
|
|
wm 000007 -- set D space bis
|
| 5564 |
|
|
rm d=000007 -- ! check; works as expected for 11/70
|
| 5565 |
|
|
wm 000000 -- restore
|
| 5566 |
|
|
#
|
| 5567 |
|
|
C test 44.49: MMR3<5:4>(UMAP, 22 bit) implemented {44,70,J11} or not {others}
|
| 5568 |
|
|
#
|
| 5569 |
|
|
wal 172516 -- SSR3
|
| 5570 |
|
|
wm 000060 -- set D space bits
|
| 5571 |
|
|
rm d=000060 -- ! check; available, as expected for 11/70
|
| 5572 |
|
|
wm 000000 -- restore
|
| 5573 |
|
|
#
|
| 5574 |
|
|
C test 44.50: MMR3<3>(CSM enable) implemented {44,J11} or not {others}
|
| 5575 |
|
|
#
|
| 5576 |
|
|
wal 172516 -- SSR3
|
| 5577 |
|
|
wm 000010 -- set D space bit
|
| 5578 |
|
|
rm d=000000 -- ! check; not available, as expected for 11/70
|
| 5579 |
|
|
wm 000000 -- restore
|
| 5580 |
|
|
#
|
| 5581 |
|
|
C test 44.51: MMR2 tracks fetches {70} or instructions only {others}
|
| 5582 |
|
|
C here W11 behaves like {others}, fetches are not tracked in SSR2
|
| 5583 |
|
|
C Also: instruction complete flag set in SSR0 after bpt.
|
| 5584 |
|
|
#
|
| 5585 |
|
|
wal 177572 -- SSR0
|
| 5586 |
|
|
wmi 000001 -- set enable bit
|
| 5587 |
|
|
wsp 001400 -- sp=1400
|
| 5588 |
|
|
wpc 013052 -- pc=13052
|
| 5589 |
|
|
step -- step (bpt)
|
| 5590 |
|
|
rpc d=000016 -- ! pc=16; trap 14 see note [[s:13054]]
|
| 5591 |
|
|
wal 177572 -- check SSR0/1/2
|
| 5592 |
|
|
brm 3
|
| 5593 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 5594 |
|
|
d=000000 -- ! SSR1: ra=none
|
| 5595 |
|
|
d=013052 -- ! SSR2: PC of bpt
|
| 5596 |
|
|
step -- step (halt)
|
| 5597 |
|
|
rpc d=000020 -- ! pc=20 (after halt)
|
| 5598 |
|
|
wal 177572 -- check SSR0/1/2
|
| 5599 |
|
|
brm 3
|
| 5600 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
| 5601 |
|
|
d=000000 -- ! SSR1: ra=none
|
| 5602 |
|
|
d=000016 -- ! SSR2: PC of halt
|
| 5603 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg, PSW)
|
| 5604 |
2 |
wfjm |
#
|
| 5605 |
|
|
# simh notes:
|
| 5606 |
|
|
# 1. when simh steps over a BPT,IOT,..., the PC is pointing after the
|
| 5607 |
|
|
# instruction. The trap sequence together with first instruction is
|
| 5608 |
|
|
# executed in next step.
|
| 5609 |
|
|
#
|
| 5610 |
|
|
C test 44.52: MT/FPx SP for pmode=10 unpredictable {others} / user SP {J11}
|
| 5611 |
|
|
# write registers
|
| 5612 |
|
|
#
|
| 5613 |
|
|
wr0 000001 -- set r0,..,r7
|
| 5614 |
|
|
wr1 000101 --
|
| 5615 |
|
|
wr2 000201 --
|
| 5616 |
|
|
wr3 000301 --
|
| 5617 |
|
|
wr4 000401 --
|
| 5618 |
|
|
wr5 000501 --
|
| 5619 |
|
|
wsp 001400 --
|
| 5620 |
|
|
wpc 000701 --
|
| 5621 |
|
|
# write register set 1, sm,um stack
|
| 5622 |
|
|
#
|
| 5623 |
|
|
wps 004000 -- psw: cm=kernel, set=1
|
| 5624 |
|
|
wr0 010001 -- set r0,..,r5 [[r10]]
|
| 5625 |
|
|
wr1 010101 -- [[r11]]
|
| 5626 |
|
|
wr2 010201 -- [[r12]]
|
| 5627 |
|
|
wr3 010301 -- [[r13]]
|
| 5628 |
|
|
wr4 010401 -- [[r14]]
|
| 5629 |
|
|
wr5 010501 -- [[r15]]
|
| 5630 |
|
|
wps 044000 -- psw: cm=super(01),set=1
|
| 5631 |
|
|
wsp 010601 -- set ssp [[ssp]]
|
| 5632 |
|
|
wps 144000 -- psw: cm=user(11),set=1
|
| 5633 |
|
|
wsp 110601 -- set usp [[usp]]
|
| 5634 |
|
|
#
|
| 5635 |
|
|
C 52a: MFPS for pmode=10
|
| 5636 |
|
|
#
|
| 5637 |
|
|
wps 020000 -- psw: set cm=00, pm=10
|
| 5638 |
|
|
wpc 013046 -- pc=13046
|
| 5639 |
|
|
step -- step (mfpd sp)
|
| 5640 |
|
|
rpc d=013050 -- ! pc=next
|
| 5641 |
|
|
rsp d=001376 -- ! sp=1376
|
| 5642 |
|
|
wal 001376 -- check stack
|
| 5643 |
|
|
rmi d=013046 -- ! it returns PC like 11/70 unpredictable [[s:0]]
|
| 5644 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5645 |
2 |
wfjm |
#
|
| 5646 |
|
|
# simh note:
|
| 5647 |
|
|
# 1. simh returns 0 here, just unpredictable in a different way ...
|
| 5648 |
|
|
#
|
| 5649 |
|
|
C 52a: MTPS for pmode=10
|
| 5650 |
|
|
#
|
| 5651 |
|
|
wal 001376 -- setup stack with value for mtpd
|
| 5652 |
|
|
wmi 123446 --
|
| 5653 |
|
|
wps 020000 -- psw: set cm=00, pm=10
|
| 5654 |
|
|
wpc 013050 -- pc=13050
|
| 5655 |
|
|
step -- step (mtpd sp)
|
| 5656 |
|
|
rpc d=013052 -- ! pc=next
|
| 5657 |
|
|
rsp d=001400 -- ! sp=1400
|
| 5658 |
|
|
# check registers
|
| 5659 |
|
|
#
|
| 5660 |
|
|
rr0 d=000001 -- ! r0,..,r7
|
| 5661 |
|
|
rr1 d=000101 -- !
|
| 5662 |
|
|
rr2 d=000201 -- !
|
| 5663 |
|
|
rr3 d=000301 -- !
|
| 5664 |
|
|
rr4 d=000401 -- !
|
| 5665 |
|
|
rr5 d=000501 -- !
|
| 5666 |
|
|
# check register set 1, sm,um stack
|
| 5667 |
|
|
#
|
| 5668 |
|
|
wps 004000 -- psw: cm=kernel, set=1
|
| 5669 |
|
|
rr0 d=010001 -- ! r0,..,r5 [[r10]]
|
| 5670 |
|
|
rr1 d=010101 -- ! [[r11]]
|
| 5671 |
|
|
rr2 d=010201 -- ! [[r12]]
|
| 5672 |
|
|
rr3 d=010301 -- ! [[r13]]
|
| 5673 |
|
|
rr4 d=010401 -- ! [[r14]]
|
| 5674 |
|
|
rr5 d=010501 -- ! [[r15]]
|
| 5675 |
|
|
wps 044000 -- psw: cm=super(01),set=1
|
| 5676 |
|
|
rsp d=010601 -- ! ssp [[ssp]]
|
| 5677 |
|
|
wps 144000 -- psw: cm=user(11),set=1
|
| 5678 |
|
|
rsp d=110601 -- ! usp [[usp]]
|
| 5679 |
|
|
# --> all preset values intact; -> mtpd thus noop --> like 11/70 unpredictable
|
| 5680 |
|
|
#
|
| 5681 |
30 |
wfjm |
cres -- console reset (to clear CPUERR reg)
|
| 5682 |
2 |
wfjm |
#
|
| 5683 |
|
|
# simh notes on MMR0:
|
| 5684 |
|
|
# 1. simh doesn't freeze MMR0 bit 7, the instr.compl. bit is set again after
|
| 5685 |
|
|
# executing first instruction of trap handler.
|
| 5686 |
|
|
#
|
| 5687 |
|
|
#-----------------------------------------------------------------------------
|
| 5688 |
|
|
C Setup code 45 [base 13100] (mmr1 and instructions with implicit stack push/pop
|
| 5689 |
|
|
#
|
| 5690 |
|
|
wal 013100 -- code: (to be single stepped mostly)
|
| 5691 |
|
|
bwm 5
|
| 5692 |
|
|
106621 -- mtpd (r1)+
|
| 5693 |
|
|
106521 -- mfpd (r1)+
|
| 5694 |
|
|
004721 -- jsr pc,(r1)+
|
| 5695 |
|
|
000000 -- halt
|
| 5696 |
|
|
#13110
|
| 5697 |
|
|
000207 -- rts pc
|
| 5698 |
|
|
#-----
|
| 5699 |
|
|
C Exec code 45 (mmr1 and instructions with implicit stack push/pop)
|
| 5700 |
|
|
C test 45.1: mtpd (r1)+
|
| 5701 |
|
|
#
|
| 5702 |
30 |
wfjm |
cres
|
| 5703 |
2 |
wfjm |
wal 177572 -- SSR0
|
| 5704 |
|
|
wmi 000001 -- set enable bit
|
| 5705 |
|
|
wal 001376 -- setup stack with value for mtpd
|
| 5706 |
|
|
wmi 123456 --
|
| 5707 |
|
|
wr1 030000 -- r1=30000
|
| 5708 |
|
|
wsp 001376 -- sp=1376
|
| 5709 |
|
|
wpc 013100 -- pc=13100
|
| 5710 |
|
|
step -- step (mtpd (r1)+)
|
| 5711 |
|
|
rpc d=013102 -- ! pc=next
|
| 5712 |
|
|
rsp d=001400 -- ! sp=1400
|
| 5713 |
|
|
rr1 d=030002 -- ! r1=30002
|
| 5714 |
|
|
wal 177572 -- check SSR0/1/2
|
| 5715 |
|
|
brm 3
|
| 5716 |
|
|
d=000003 -- ! SSR0: (seg=1,ena=1)
|
| 5717 |
|
|
d=010426 -- ! SSR1: rb=1,2; ra=6,2
|
| 5718 |
|
|
d=013100 -- ! SSR2: PC of mtpd
|
| 5719 |
|
|
wal 030000 -- check target memory
|
| 5720 |
|
|
rm d=123456 -- !
|
| 5721 |
30 |
wfjm |
cres -- console reset
|
| 5722 |
2 |
wfjm |
#
|
| 5723 |
|
|
C test 45.2: mfpd (r1)+
|
| 5724 |
|
|
#
|
| 5725 |
|
|
wal 177572 -- SSR0
|
| 5726 |
|
|
wmi 000001 -- set enable bit
|
| 5727 |
|
|
wr1 030000 -- r1=30000
|
| 5728 |
|
|
wsp 001400 -- sp=1400
|
| 5729 |
|
|
wpc 013102 -- pc=13102
|
| 5730 |
|
|
step -- step (mfpd (r1)+)
|
| 5731 |
|
|
rpc d=013104 -- ! pc=next
|
| 5732 |
|
|
rsp d=001376 -- ! sp=1376
|
| 5733 |
|
|
rr1 d=030002 -- ! r1=30002
|
| 5734 |
|
|
wal 177572 -- check SSR0/1/2
|
| 5735 |
|
|
brm 3
|
| 5736 |
|
|
d=000001 -- ! SSR0: (seg=0,ena=1)
|
| 5737 |
|
|
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
|
| 5738 |
|
|
d=013102 -- ! SSR2: PC of mtpd
|
| 5739 |
|
|
wal 001376 -- check stack
|
| 5740 |
|
|
rmi d=123456 -- !
|
| 5741 |
|
|
wal 030000 -- clear tainted target memory
|
| 5742 |
|
|
wm 000000 --
|
| 5743 |
30 |
wfjm |
cres -- console reset
|
| 5744 |
2 |
wfjm |
#
|
| 5745 |
|
|
C test 45.3: jsr pc,(r1)+ and rts pc
|
| 5746 |
|
|
#
|
| 5747 |
|
|
wal 177572 -- SSR0
|
| 5748 |
|
|
wmi 000001 -- set enable bit
|
| 5749 |
|
|
wr1 013110 -- r1=13110
|
| 5750 |
|
|
wsp 001400 -- sp=1400
|
| 5751 |
|
|
wpc 013104 -- pc=13104
|
| 5752 |
|
|
step -- step (jsr pc,(r1)+)
|
| 5753 |
|
|
rpc d=013110 -- ! pc=target
|
| 5754 |
|
|
rsp d=001376 -- ! sp=1376
|
| 5755 |
|
|
rr1 d=013112 -- ! r1=13112
|
| 5756 |
|
|
wal 177572 -- check SSR0/1/2
|
| 5757 |
|
|
brm 3
|
| 5758 |
|
|
d=000001 -- ! SSR0: (seg=0,ena=1)
|
| 5759 |
|
|
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
|
| 5760 |
|
|
d=013104 -- ! SSR2: PC of jsr
|
| 5761 |
|
|
wal 001376 -- check stack
|
| 5762 |
|
|
rmi d=013106 -- ! PC after jsr
|
| 5763 |
|
|
step -- step (rts pc)
|
| 5764 |
|
|
rpc d=013106 -- ! pc=target
|
| 5765 |
|
|
rsp d=001400 -- ! sp=1400
|
| 5766 |
|
|
wal 177572 -- check SSR0/1/2
|
| 5767 |
|
|
brm 3
|
| 5768 |
|
|
d=000001 -- ! SSR0: (seg=0,ena=1)
|
| 5769 |
|
|
d=000026 -- ! SSR1: ra=6,2 [[s:0]]
|
| 5770 |
|
|
d=013110 -- ! SSR2: PC of rts
|
| 5771 |
30 |
wfjm |
cres -- console reset
|
| 5772 |
2 |
wfjm |
#
|
| 5773 |
|
|
# simh notes:
|
| 5774 |
|
|
# 1. simh reads stack and incremets sp later. In case of an MMU abort on
|
| 5775 |
|
|
# stack read, simh SSR1 will be 0, while W11 shows the sp increment
|
| 5776 |
|
|
#
|
| 5777 |
|
|
#-----------------------------------------------------------------------------
|
| 5778 |
|
|
C Setup code 46 [base 13200] (systematic result+cc test of 1+2op instructions)
|
| 5779 |
|
|
# the following codes expect:
|
| 5780 |
|
|
# r0-> psw
|
| 5781 |
|
|
# r1-> loop count
|
| 5782 |
|
|
# r2-> input ptr
|
| 5783 |
|
|
# r3-> output ptr
|
| 5784 |
|
|
# r4-> src reg
|
| 5785 |
|
|
# r5-> dst reg
|
| 5786 |
|
|
#
|
| 5787 |
|
|
wal 013200 -- code 1: test 1op register
|
| 5788 |
|
|
bwm 8
|
| 5789 |
|
|
000230 -- spl 0
|
| 5790 |
|
|
012205 -- L1: mov (r2)+,r5 ; load dst
|
| 5791 |
|
|
000000 -- halt ; ccmov set cc's
|
| 5792 |
|
|
000000 -- halt ; iut instr. under test
|
| 5793 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
| 5794 |
|
|
010523 -- mov r5,(r3)+ ; save dst
|
| 5795 |
|
|
077106 -- sob r1,L1 (.-6)
|
| 5796 |
|
|
000000 -- halt
|
| 5797 |
|
|
#----
|
| 5798 |
|
|
wal 013220 -- code 2: test 1op memory
|
| 5799 |
|
|
bwm 8
|
| 5800 |
|
|
000230 -- spl 0
|
| 5801 |
|
|
012215 -- L1: mov (r2)+,(r5) ; load dst
|
| 5802 |
|
|
000000 -- halt ; ccmov set cc's
|
| 5803 |
|
|
000000 -- halt ; iut instr. under test
|
| 5804 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
| 5805 |
|
|
011523 -- mov (r5),(r3)+ ; save dst
|
| 5806 |
|
|
077106 -- sob r1,L1 (.-6)
|
| 5807 |
|
|
000000 -- halt
|
| 5808 |
|
|
#-----
|
| 5809 |
|
|
wal 013240 -- code 3: test 2op register
|
| 5810 |
|
|
bwm 9
|
| 5811 |
|
|
000230 -- spl 0
|
| 5812 |
|
|
012204 -- L1: mov (r2)+,r4 ; load src
|
| 5813 |
|
|
012205 -- mov (r2)+,r5 ; load dst
|
| 5814 |
|
|
000000 -- halt ; ccmov set cc's
|
| 5815 |
|
|
000000 -- halt ; iut instr. under test
|
| 5816 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
| 5817 |
|
|
010523 -- mov r5,(r3)+ ; save dst
|
| 5818 |
|
|
077107 -- sob r1,L1 (.-7)
|
| 5819 |
|
|
#13260
|
| 5820 |
|
|
000000 -- halt
|
| 5821 |
|
|
#-----
|
| 5822 |
|
|
wal 013270 -- code 4: test 2op memory
|
| 5823 |
|
|
bwm 9
|
| 5824 |
|
|
000230 -- spl 0
|
| 5825 |
|
|
012214 -- L1: mov (r2)+,(r4) ; load src
|
| 5826 |
|
|
012215 -- mov (r2)+,(r5) ; load dst
|
| 5827 |
|
|
000000 -- halt ; ccmov set cc's
|
| 5828 |
|
|
#13300
|
| 5829 |
|
|
000000 -- halt ; iut instr. under test
|
| 5830 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
| 5831 |
|
|
011523 -- mov (r5),(r3)+ ; save dst
|
| 5832 |
|
|
077107 -- sob r1,L1 (.-7)
|
| 5833 |
|
|
000000 -- halt
|
| 5834 |
|
|
#----
|
| 5835 |
|
|
C Exec code 46 pass 1 (systematic result+cc test of 1+2op instructions; word)
|
| 5836 |
|
|
C Exec test 46.1wr: COM - reg
|
| 5837 |
|
|
#
|
| 5838 |
|
|
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst
|
| 5839 |
|
|
bwm 5
|
| 5840 |
|
|
000000 -- com 000000
|
| 5841 |
|
|
000001 -- com 000001
|
| 5842 |
|
|
077777 -- com 077777
|
| 5843 |
|
|
100000 -- com 100000
|
| 5844 |
|
|
177777 -- com 177777
|
| 5845 |
|
|
wal 013204 -- setup test instructions:
|
| 5846 |
|
|
bwm 2
|
| 5847 |
|
|
000241 -- ccmov= clc
|
| 5848 |
|
|
005105 -- iut= com r5
|
| 5849 |
|
|
wr0 177776 -- r0=177776
|
| 5850 |
|
|
wr1 000005 -- r1=5
|
| 5851 |
|
|
wr2 036000 -- r2=36000
|
| 5852 |
|
|
wr3 037000 -- r3=37000
|
| 5853 |
|
|
wr4 000000 -- r4=0
|
| 5854 |
|
|
wr5 000000 -- r5=0
|
| 5855 |
|
|
wsp 001400 -- sp=1400
|
| 5856 |
30 |
wfjm |
cres
|
| 5857 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 5858 |
|
|
wtgo
|
| 5859 |
|
|
rpc d=013220 -- ! pc=halt
|
| 5860 |
|
|
rr1 d=000000 -- ! r1=0
|
| 5861 |
|
|
wal 037000 -- check result area
|
| 5862 |
|
|
brm 10
|
| 5863 |
|
|
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
|
| 5864 |
|
|
d=177777 -- !
|
| 5865 |
|
|
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
|
| 5866 |
|
|
d=177776 -- !
|
| 5867 |
|
|
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
|
| 5868 |
|
|
d=100000 -- !
|
| 5869 |
|
|
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
|
| 5870 |
|
|
d=077777 -- !
|
| 5871 |
|
|
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
|
| 5872 |
|
|
d=000000 -- !
|
| 5873 |
|
|
#--------
|
| 5874 |
|
|
C Exec test 46.1wm: COM - mem
|
| 5875 |
|
|
#
|
| 5876 |
|
|
wal 013224 -- setup test instructions:
|
| 5877 |
|
|
bwm 2
|
| 5878 |
|
|
000241 -- ccmov= clc
|
| 5879 |
|
|
005115 -- iut= com (r5)
|
| 5880 |
|
|
wr0 177776 -- r0=177776
|
| 5881 |
|
|
wr1 000005 -- r1=5
|
| 5882 |
|
|
wr2 036000 -- r2=36000
|
| 5883 |
|
|
wr3 037000 -- r3=37000
|
| 5884 |
|
|
wr4 001400 -- r4=1400
|
| 5885 |
|
|
wr5 001402 -- r5=1402
|
| 5886 |
|
|
wsp 001400 -- sp=1400
|
| 5887 |
30 |
wfjm |
cres
|
| 5888 |
2 |
wfjm |
stapc 013220 -- start @ 13220 (1op mem)
|
| 5889 |
|
|
wtgo
|
| 5890 |
|
|
rpc d=013240 -- ! pc=halt
|
| 5891 |
|
|
rr1 d=000000 -- ! r1=0
|
| 5892 |
|
|
wal 037000 -- check result area
|
| 5893 |
|
|
brm 10
|
| 5894 |
|
|
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
|
| 5895 |
|
|
d=177777 -- !
|
| 5896 |
|
|
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
|
| 5897 |
|
|
d=177776 -- !
|
| 5898 |
|
|
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
|
| 5899 |
|
|
d=100000 -- !
|
| 5900 |
|
|
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
|
| 5901 |
|
|
d=077777 -- !
|
| 5902 |
|
|
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
|
| 5903 |
|
|
d=000000 -- !
|
| 5904 |
|
|
#--------
|
| 5905 |
|
|
C Exec test 46.2wrc0: INC - reg,C=0
|
| 5906 |
|
|
#
|
| 5907 |
|
|
wal 013204 -- setup test instructions:
|
| 5908 |
|
|
bwm 2
|
| 5909 |
|
|
000241 -- ccmov= clc
|
| 5910 |
|
|
005205 -- iut= inc r5
|
| 5911 |
|
|
wr0 177776 -- r0=177776
|
| 5912 |
|
|
wr1 000005 -- r1=5
|
| 5913 |
|
|
wr2 036000 -- r2=36000
|
| 5914 |
|
|
wr3 037000 -- r3=37000
|
| 5915 |
|
|
wr4 000000 -- r4=0
|
| 5916 |
|
|
wr5 000000 -- r5=0
|
| 5917 |
|
|
wsp 001400 -- sp=1400
|
| 5918 |
30 |
wfjm |
cres
|
| 5919 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 5920 |
|
|
wtgo
|
| 5921 |
|
|
rpc d=013220 -- ! pc=halt
|
| 5922 |
|
|
rr1 d=000000 -- ! r1=0
|
| 5923 |
|
|
wal 037000 -- check result area
|
| 5924 |
|
|
brm 10
|
| 5925 |
|
|
d=000000 -- ! inc 000000 -> n0z0v0c0; 000001
|
| 5926 |
|
|
d=000001 -- !
|
| 5927 |
|
|
d=000000 -- ! inc 000001 -> n0z0v0c0; 000002
|
| 5928 |
|
|
d=000002 -- !
|
| 5929 |
|
|
d=000012 -- ! inc 077777 -> n1z0v1c0; 100000
|
| 5930 |
|
|
d=100000 -- !
|
| 5931 |
|
|
d=000010 -- ! inc 100000 -> n1z0v0c0; 100001
|
| 5932 |
|
|
d=100001 -- !
|
| 5933 |
|
|
d=000004 -- ! inc 177777 -> n0z1v0c0; 000000
|
| 5934 |
|
|
d=000000 -- !
|
| 5935 |
|
|
#--------
|
| 5936 |
|
|
C Exec test 46.2wrc1: INC - reg,C=1
|
| 5937 |
|
|
#
|
| 5938 |
|
|
wal 013204 -- setup test instructions:
|
| 5939 |
|
|
bwm 2
|
| 5940 |
|
|
000261 -- ccmov= sec
|
| 5941 |
|
|
005205 -- iut= inc r5
|
| 5942 |
|
|
wr0 177776 -- r0=177776
|
| 5943 |
|
|
wr1 000005 -- r1=5
|
| 5944 |
|
|
wr2 036000 -- r2=36000
|
| 5945 |
|
|
wr3 037000 -- r3=37000
|
| 5946 |
|
|
wr4 000000 -- r4=0
|
| 5947 |
|
|
wr5 000000 -- r5=0
|
| 5948 |
|
|
wsp 001400 -- sp=1400
|
| 5949 |
30 |
wfjm |
cres
|
| 5950 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 5951 |
|
|
wtgo
|
| 5952 |
|
|
rpc d=013220 -- ! pc=halt
|
| 5953 |
|
|
rr1 d=000000 -- ! r1=0
|
| 5954 |
|
|
wal 037000 -- check result area
|
| 5955 |
|
|
brm 10
|
| 5956 |
|
|
d=000001 -- ! inc 000000 -> n0z0v0c1; 000001
|
| 5957 |
|
|
d=000001 -- !
|
| 5958 |
|
|
d=000001 -- ! inc 000001 -> n0z0v0c1; 000002
|
| 5959 |
|
|
d=000002 -- !
|
| 5960 |
|
|
d=000013 -- ! inc 077777 -> n1z0v1c1; 100000
|
| 5961 |
|
|
d=100000 -- !
|
| 5962 |
|
|
d=000011 -- ! inc 100000 -> n1z0v0c1; 100001
|
| 5963 |
|
|
d=100001 -- !
|
| 5964 |
|
|
d=000005 -- ! inc 177777 -> n0z1v0c1; 000000
|
| 5965 |
|
|
d=000000 -- !
|
| 5966 |
|
|
#--------
|
| 5967 |
|
|
C Exec test 46.3wrc0: DEC - reg,C=0
|
| 5968 |
|
|
#
|
| 5969 |
|
|
wal 013204 -- setup test instructions:
|
| 5970 |
|
|
bwm 2
|
| 5971 |
|
|
000241 -- ccmov= clc
|
| 5972 |
|
|
005305 -- iut= dec r5
|
| 5973 |
|
|
wr0 177776 -- r0=177776
|
| 5974 |
|
|
wr1 000005 -- r1=5
|
| 5975 |
|
|
wr2 036000 -- r2=36000
|
| 5976 |
|
|
wr3 037000 -- r3=37000
|
| 5977 |
|
|
wr4 000000 -- r4=0
|
| 5978 |
|
|
wr5 000000 -- r5=0
|
| 5979 |
|
|
wsp 001400 -- sp=1400
|
| 5980 |
30 |
wfjm |
cres
|
| 5981 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 5982 |
|
|
wtgo
|
| 5983 |
|
|
rpc d=013220 -- ! pc=halt
|
| 5984 |
|
|
rr1 d=000000 -- ! r1=0
|
| 5985 |
|
|
wal 037000 -- check result area
|
| 5986 |
|
|
brm 10
|
| 5987 |
|
|
d=000010 -- ! dec 000000 -> n1z0v0c0; 177777
|
| 5988 |
|
|
d=177777 -- !
|
| 5989 |
|
|
d=000004 -- ! dec 000001 -> n0z1v0c0; 000000
|
| 5990 |
|
|
d=000000 -- !
|
| 5991 |
|
|
d=000000 -- ! dec 077777 -> n0z0v0c0; 077776
|
| 5992 |
|
|
d=077776 -- !
|
| 5993 |
|
|
d=000002 -- ! dec 100000 -> n0z0v1c0; 077777
|
| 5994 |
|
|
d=077777 -- !
|
| 5995 |
|
|
d=000010 -- ! dec 177777 -> n1z0v0c0; 177776
|
| 5996 |
|
|
d=177776 -- !
|
| 5997 |
|
|
#--------
|
| 5998 |
|
|
C Exec test 46.3wrc1: DEC - reg,C=1
|
| 5999 |
|
|
#
|
| 6000 |
|
|
wal 013204 -- setup test instructions:
|
| 6001 |
|
|
bwm 2
|
| 6002 |
|
|
000261 -- ccmov= sec
|
| 6003 |
|
|
005305 -- iut= dec r5
|
| 6004 |
|
|
wr0 177776 -- r0=177776
|
| 6005 |
|
|
wr1 000005 -- r1=5
|
| 6006 |
|
|
wr2 036000 -- r2=36000
|
| 6007 |
|
|
wr3 037000 -- r3=37000
|
| 6008 |
|
|
wr4 000000 -- r4=0
|
| 6009 |
|
|
wr5 000000 -- r5=0
|
| 6010 |
|
|
wsp 001400 -- sp=1400
|
| 6011 |
30 |
wfjm |
cres
|
| 6012 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6013 |
|
|
wtgo
|
| 6014 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6015 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6016 |
|
|
wal 037000 -- check result area
|
| 6017 |
|
|
brm 10
|
| 6018 |
|
|
d=000011 -- ! dec 000000 -> n1z0v0c1; 177777
|
| 6019 |
|
|
d=177777 -- !
|
| 6020 |
|
|
d=000005 -- ! dec 000001 -> n0z1v0c1; 000000
|
| 6021 |
|
|
d=000000 -- !
|
| 6022 |
|
|
d=000001 -- ! dec 077777 -> n0z0v0c1; 077776
|
| 6023 |
|
|
d=077776 -- !
|
| 6024 |
|
|
d=000003 -- ! dec 100000 -> n0z0v1c1; 077777
|
| 6025 |
|
|
d=077777 -- !
|
| 6026 |
|
|
d=000011 -- ! dec 177777 -> n1z0v0c1; 177776
|
| 6027 |
|
|
d=177776 -- !
|
| 6028 |
|
|
#--------
|
| 6029 |
|
|
C Exec test 46.4wr: NEG - reg
|
| 6030 |
|
|
#
|
| 6031 |
|
|
wal 013204 -- setup test instructions:
|
| 6032 |
|
|
bwm 2
|
| 6033 |
|
|
000241 -- ccmov= clc
|
| 6034 |
|
|
005405 -- iut= neg r5
|
| 6035 |
|
|
wr0 177776 -- r0=177776
|
| 6036 |
|
|
wr1 000005 -- r1=5
|
| 6037 |
|
|
wr2 036000 -- r2=36000
|
| 6038 |
|
|
wr3 037000 -- r3=37000
|
| 6039 |
|
|
wr4 000000 -- r4=0
|
| 6040 |
|
|
wr5 000000 -- r5=0
|
| 6041 |
|
|
wsp 001400 -- sp=1400
|
| 6042 |
30 |
wfjm |
cres
|
| 6043 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6044 |
|
|
wtgo
|
| 6045 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6046 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6047 |
|
|
wal 037000 -- check result area
|
| 6048 |
|
|
brm 10
|
| 6049 |
|
|
d=000004 -- ! neg 000000 -> n0z1v0c0; 000000
|
| 6050 |
|
|
d=000000 -- !
|
| 6051 |
|
|
d=000011 -- ! neg 000001 -> n1z0v0c1; 177777
|
| 6052 |
|
|
d=177777 -- !
|
| 6053 |
|
|
d=000011 -- ! neg 077777 -> n1z0v0c1; 100001
|
| 6054 |
|
|
d=100001 -- !
|
| 6055 |
|
|
d=000013 -- ! neg 100000 -> n1z0v1c1; 100000
|
| 6056 |
|
|
d=100000 -- !
|
| 6057 |
|
|
d=000001 -- ! neg 177777 -> n0z0v0c1; 000001
|
| 6058 |
|
|
d=000001 -- !
|
| 6059 |
|
|
#--------
|
| 6060 |
|
|
C Exec test 46.5wrc0: ADC - reg,C=0
|
| 6061 |
|
|
#
|
| 6062 |
|
|
wal 013204 -- setup test instructions:
|
| 6063 |
|
|
bwm 2
|
| 6064 |
|
|
000241 -- ccmov= clc
|
| 6065 |
|
|
005505 -- iut= adc r5
|
| 6066 |
|
|
wr0 177776 -- r0=177776
|
| 6067 |
|
|
wr1 000005 -- r1=5
|
| 6068 |
|
|
wr2 036000 -- r2=36000
|
| 6069 |
|
|
wr3 037000 -- r3=37000
|
| 6070 |
|
|
wr4 000000 -- r4=0
|
| 6071 |
|
|
wr5 000000 -- r5=0
|
| 6072 |
|
|
wsp 001400 -- sp=1400
|
| 6073 |
30 |
wfjm |
cres
|
| 6074 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6075 |
|
|
wtgo
|
| 6076 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6077 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6078 |
|
|
wal 037000 -- check result area
|
| 6079 |
|
|
brm 10
|
| 6080 |
|
|
d=000004 -- ! adc 000000 -> n0z1v0c0; 000000
|
| 6081 |
|
|
d=000000 -- !
|
| 6082 |
|
|
d=000000 -- ! adc 000001 -> n0z0v0c0; 000001
|
| 6083 |
|
|
d=000001 -- !
|
| 6084 |
|
|
d=000000 -- ! adc 077777 -> n0z0v0c0; 077777
|
| 6085 |
|
|
d=077777 -- !
|
| 6086 |
|
|
d=000010 -- ! adc 100000 -> n1z0v0c0; 100000
|
| 6087 |
|
|
d=100000 -- !
|
| 6088 |
|
|
d=000010 -- ! adc 177777 -> n1z0v0c0; 177777
|
| 6089 |
|
|
d=177777 -- !
|
| 6090 |
|
|
#--------
|
| 6091 |
|
|
C Exec test 46.5wrc1: ADC - reg,C=1
|
| 6092 |
|
|
#
|
| 6093 |
|
|
wal 013204 -- setup test instructions:
|
| 6094 |
|
|
bwm 2
|
| 6095 |
|
|
000261 -- ccmov= sec
|
| 6096 |
|
|
005505 -- iut= adc r5
|
| 6097 |
|
|
wr0 177776 -- r0=177776
|
| 6098 |
|
|
wr1 000005 -- r1=5
|
| 6099 |
|
|
wr2 036000 -- r2=36000
|
| 6100 |
|
|
wr3 037000 -- r3=37000
|
| 6101 |
|
|
wr4 000000 -- r4=0
|
| 6102 |
|
|
wr5 000000 -- r5=0
|
| 6103 |
|
|
wsp 001400 -- sp=1400
|
| 6104 |
30 |
wfjm |
cres
|
| 6105 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6106 |
|
|
wtgo
|
| 6107 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6108 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6109 |
|
|
wal 037000 -- check result area
|
| 6110 |
|
|
brm 10
|
| 6111 |
|
|
d=000000 -- ! adc 000000 -> n0z0v0c0; 000001
|
| 6112 |
|
|
d=000001 -- !
|
| 6113 |
|
|
d=000000 -- ! adc 000001 -> n0z0v0c0; 000002
|
| 6114 |
|
|
d=000002 -- !
|
| 6115 |
|
|
d=000012 -- ! adc 077777 -> n1z0v1c0; 100000
|
| 6116 |
|
|
d=100000 -- !
|
| 6117 |
|
|
d=000010 -- ! adc 100000 -> n1z0v0c0; 100001
|
| 6118 |
|
|
d=100001 -- !
|
| 6119 |
|
|
d=000005 -- ! adc 177777 -> n0z1v0c1; 000000
|
| 6120 |
|
|
d=000000 -- !
|
| 6121 |
|
|
#--------
|
| 6122 |
|
|
C Exec test 46.6wrc0: SBC - reg,C=0
|
| 6123 |
|
|
#
|
| 6124 |
|
|
wal 013204 -- setup test instructions:
|
| 6125 |
|
|
bwm 2
|
| 6126 |
|
|
000241 -- ccmov= clc
|
| 6127 |
|
|
005605 -- iut= sbc r5
|
| 6128 |
|
|
wr0 177776 -- r0=177776
|
| 6129 |
|
|
wr1 000005 -- r1=5
|
| 6130 |
|
|
wr2 036000 -- r2=36000
|
| 6131 |
|
|
wr3 037000 -- r3=37000
|
| 6132 |
|
|
wr4 000000 -- r4=0
|
| 6133 |
|
|
wr5 000000 -- r5=0
|
| 6134 |
|
|
wsp 001400 -- sp=1400
|
| 6135 |
30 |
wfjm |
cres
|
| 6136 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6137 |
|
|
wtgo
|
| 6138 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6139 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6140 |
|
|
wal 037000 -- check result area
|
| 6141 |
|
|
brm 10
|
| 6142 |
|
|
d=000004 -- ! sbc 000000 -> n0z1v0c0; 000000
|
| 6143 |
|
|
d=000000 -- !
|
| 6144 |
|
|
d=000000 -- ! sbc 000001 -> n0z0v0c0; 000001
|
| 6145 |
|
|
d=000001 -- !
|
| 6146 |
|
|
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077777
|
| 6147 |
|
|
d=077777 -- !
|
| 6148 |
|
|
d=000010 -- ! sbc 100000 -> n1z0v0c0; 100000
|
| 6149 |
|
|
d=100000 -- !
|
| 6150 |
|
|
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177777
|
| 6151 |
|
|
d=177777 -- !
|
| 6152 |
|
|
#--------
|
| 6153 |
|
|
C Exec test 46.6wrc1: SBC - reg,C=1
|
| 6154 |
|
|
#
|
| 6155 |
|
|
wal 013204 -- setup test instructions:
|
| 6156 |
|
|
bwm 2
|
| 6157 |
|
|
000261 -- ccmov= sec
|
| 6158 |
|
|
005605 -- iut= sbc r5
|
| 6159 |
|
|
wr0 177776 -- r0=177776
|
| 6160 |
|
|
wr1 000005 -- r1=5
|
| 6161 |
|
|
wr2 036000 -- r2=36000
|
| 6162 |
|
|
wr3 037000 -- r3=37000
|
| 6163 |
|
|
wr4 000000 -- r4=0
|
| 6164 |
|
|
wr5 000000 -- r5=0
|
| 6165 |
|
|
wsp 001400 -- sp=1400
|
| 6166 |
30 |
wfjm |
cres
|
| 6167 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6168 |
|
|
wtgo
|
| 6169 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6170 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6171 |
|
|
wal 037000 -- check result area
|
| 6172 |
|
|
brm 10
|
| 6173 |
|
|
d=000011 -- ! sbc 000000 -> n1z0v0c1; 177777
|
| 6174 |
|
|
d=177777 -- !
|
| 6175 |
|
|
d=000004 -- ! sbc 000001 -> n0z1v0c0; 000000
|
| 6176 |
|
|
d=000000 -- !
|
| 6177 |
|
|
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077776
|
| 6178 |
|
|
d=077776 -- !
|
| 6179 |
|
|
d=000002 -- ! sbc 100000 -> n0z0v1c0; 077777
|
| 6180 |
|
|
d=077777 -- !
|
| 6181 |
|
|
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177776
|
| 6182 |
|
|
d=177776 -- !
|
| 6183 |
|
|
#--------
|
| 6184 |
|
|
C Exec test 46.7wr: TST - reg
|
| 6185 |
|
|
#
|
| 6186 |
|
|
wal 013204 -- setup test instructions:
|
| 6187 |
|
|
bwm 2
|
| 6188 |
|
|
000261 -- ccmov= sec
|
| 6189 |
|
|
005705 -- iut= tst r5
|
| 6190 |
|
|
wr0 177776 -- r0=177776
|
| 6191 |
|
|
wr1 000005 -- r1=5
|
| 6192 |
|
|
wr2 036000 -- r2=36000
|
| 6193 |
|
|
wr3 037000 -- r3=37000
|
| 6194 |
|
|
wr4 000000 -- r4=0
|
| 6195 |
|
|
wr5 000000 -- r5=0
|
| 6196 |
|
|
wsp 001400 -- sp=1400
|
| 6197 |
30 |
wfjm |
cres
|
| 6198 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6199 |
|
|
wtgo
|
| 6200 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6201 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6202 |
|
|
wal 037000 -- check result area
|
| 6203 |
|
|
brm 10
|
| 6204 |
|
|
d=000004 -- ! tst 000000 -> n0z1v0c0;
|
| 6205 |
|
|
d=000000 -- !
|
| 6206 |
|
|
d=000000 -- ! tst 000001 -> n0z0v0c0;
|
| 6207 |
|
|
d=000001 -- !
|
| 6208 |
|
|
d=000000 -- ! tst 077777 -> n0z0v0c0;
|
| 6209 |
|
|
d=077777 -- !
|
| 6210 |
|
|
d=000010 -- ! tst 100000 -> n1z0v0c0;
|
| 6211 |
|
|
d=100000 -- !
|
| 6212 |
|
|
d=000010 -- ! tst 177777 -> n1z0v0c0;
|
| 6213 |
|
|
d=177777 -- !
|
| 6214 |
|
|
#--------
|
| 6215 |
|
|
C Exec test 46.7wm: TST - mem
|
| 6216 |
|
|
#
|
| 6217 |
|
|
wal 013224 -- setup test instructions:
|
| 6218 |
|
|
bwm 2
|
| 6219 |
|
|
000261 -- ccmov= sec
|
| 6220 |
|
|
005715 -- iut= tst (r5)
|
| 6221 |
|
|
wr0 177776 -- r0=177776
|
| 6222 |
|
|
wr1 000005 -- r1=5
|
| 6223 |
|
|
wr2 036000 -- r2=36000
|
| 6224 |
|
|
wr3 037000 -- r3=37000
|
| 6225 |
|
|
wr4 001400 -- r4=1400
|
| 6226 |
|
|
wr5 001402 -- r5=1402
|
| 6227 |
|
|
wsp 001400 -- sp=1400
|
| 6228 |
30 |
wfjm |
cres
|
| 6229 |
2 |
wfjm |
stapc 013220 -- start @ 13220 (1op mem)
|
| 6230 |
|
|
wtgo
|
| 6231 |
|
|
rpc d=013240 -- ! pc=halt
|
| 6232 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6233 |
|
|
wal 037000 -- check result area
|
| 6234 |
|
|
brm 10
|
| 6235 |
|
|
d=000004 -- ! tst 000000 -> n0z1v0c0;
|
| 6236 |
|
|
d=000000 -- !
|
| 6237 |
|
|
d=000000 -- ! tst 000001 -> n0z0v0c0;
|
| 6238 |
|
|
d=000001 -- !
|
| 6239 |
|
|
d=000000 -- ! tst 077777 -> n0z0v0c0;
|
| 6240 |
|
|
d=077777 -- !
|
| 6241 |
|
|
d=000010 -- ! tst 100000 -> n1z0v0c0;
|
| 6242 |
|
|
d=100000 -- !
|
| 6243 |
|
|
d=000010 -- ! tst 177777 -> n1z0v0c0;
|
| 6244 |
|
|
d=177777 -- !
|
| 6245 |
|
|
#--------
|
| 6246 |
|
|
C Exec test 46.8wrc0: ROR - reg, C=0
|
| 6247 |
|
|
#
|
| 6248 |
|
|
wal 036000 -- setup test vector: for ror,rol,ars,asl
|
| 6249 |
|
|
bwm 7
|
| 6250 |
|
|
000000 -- ror 000000
|
| 6251 |
|
|
000001 -- ror 000001
|
| 6252 |
|
|
100000 -- ror 100000
|
| 6253 |
|
|
000100 -- ror 000100
|
| 6254 |
|
|
000101 -- ror 000101
|
| 6255 |
|
|
040100 -- ror 040100
|
| 6256 |
|
|
100100 -- ror 100100
|
| 6257 |
|
|
wal 013204 -- setup test instructions:
|
| 6258 |
|
|
bwm 2
|
| 6259 |
|
|
000241 -- ccmov= clc
|
| 6260 |
|
|
006005 -- iut= ror r5
|
| 6261 |
|
|
wr0 177776 -- r0=177776
|
| 6262 |
|
|
wr1 000007 -- r1=7
|
| 6263 |
|
|
wr2 036000 -- r2=36000
|
| 6264 |
|
|
wr3 037000 -- r3=37000
|
| 6265 |
|
|
wr4 000000 -- r4=0
|
| 6266 |
|
|
wr5 000000 -- r5=0
|
| 6267 |
|
|
wsp 001400 -- sp=1400
|
| 6268 |
30 |
wfjm |
cres
|
| 6269 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6270 |
|
|
wtgo
|
| 6271 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6272 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6273 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6274 |
|
|
brm 14
|
| 6275 |
|
|
d=000004 -- ! ror 000000 -> n0z1v0c0; 000000
|
| 6276 |
|
|
d=000000 -- !
|
| 6277 |
|
|
d=000007 -- ! ror 000001 -> n0z1v1c1; 000000
|
| 6278 |
|
|
d=000000 -- !
|
| 6279 |
|
|
d=000000 -- ! ror 100000 -> n0z0v0c0; 040000
|
| 6280 |
|
|
d=040000 -- !
|
| 6281 |
|
|
d=000000 -- ! ror 000100 -> n0z0v0c0; 000040
|
| 6282 |
|
|
d=000040 -- !
|
| 6283 |
|
|
d=000003 -- ! ror 000101 -> n0z0v1c1; 000040
|
| 6284 |
|
|
d=000040 -- !
|
| 6285 |
|
|
d=000000 -- ! ror 040100 -> n0z0v0c0; 020040
|
| 6286 |
|
|
d=020040 -- !
|
| 6287 |
|
|
d=000000 -- ! ror 100100 -> n0z0v0c0; 040040
|
| 6288 |
|
|
d=040040 -- !
|
| 6289 |
|
|
#--------
|
| 6290 |
|
|
C Exec test 46.8wrc1: ROR - reg, C=1
|
| 6291 |
|
|
#
|
| 6292 |
|
|
wal 013204 -- setup test instructions:
|
| 6293 |
|
|
bwm 2
|
| 6294 |
|
|
000261 -- ccmov= sec
|
| 6295 |
|
|
006005 -- iut= ror r5
|
| 6296 |
|
|
wr0 177776 -- r0=177776
|
| 6297 |
|
|
wr1 000007 -- r1=7
|
| 6298 |
|
|
wr2 036000 -- r2=36000
|
| 6299 |
|
|
wr3 037000 -- r3=37000
|
| 6300 |
|
|
wr4 000000 -- r4=0
|
| 6301 |
|
|
wr5 000000 -- r5=0
|
| 6302 |
|
|
wsp 001400 -- sp=1400
|
| 6303 |
30 |
wfjm |
cres
|
| 6304 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6305 |
|
|
wtgo
|
| 6306 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6307 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6308 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6309 |
|
|
brm 14
|
| 6310 |
|
|
d=000012 -- ! ror 000000 -> n1z0v1c0; 100000
|
| 6311 |
|
|
d=100000 -- !
|
| 6312 |
|
|
d=000011 -- ! ror 000001 -> n1z0v0c1; 100000
|
| 6313 |
|
|
d=100000 -- !
|
| 6314 |
|
|
d=000012 -- ! ror 100000 -> n1z0v1c0; 140000
|
| 6315 |
|
|
d=140000 -- !
|
| 6316 |
|
|
d=000012 -- ! ror 000100 -> n1z0v1c0; 100040
|
| 6317 |
|
|
d=100040 -- !
|
| 6318 |
|
|
d=000011 -- ! ror 000101 -> n1z0v0c1; 100040
|
| 6319 |
|
|
d=100040 -- !
|
| 6320 |
|
|
d=000012 -- ! ror 040100 -> n1z0v1c0; 120040
|
| 6321 |
|
|
d=120040 -- !
|
| 6322 |
|
|
d=000012 -- ! ror 100100 -> n1z0v1c0; 140040
|
| 6323 |
|
|
d=140040 -- !
|
| 6324 |
|
|
#--------
|
| 6325 |
|
|
C Exec test 46.9wrc0: ROL - reg, C=0
|
| 6326 |
|
|
#
|
| 6327 |
|
|
wal 013204 -- setup test instructions:
|
| 6328 |
|
|
bwm 2
|
| 6329 |
|
|
000241 -- ccmov= clc
|
| 6330 |
|
|
006105 -- iut= rol r5
|
| 6331 |
|
|
wr0 177776 -- r0=177776
|
| 6332 |
|
|
wr1 000007 -- r1=7
|
| 6333 |
|
|
wr2 036000 -- r2=36000
|
| 6334 |
|
|
wr3 037000 -- r3=37000
|
| 6335 |
|
|
wr4 000000 -- r4=0
|
| 6336 |
|
|
wr5 000000 -- r5=0
|
| 6337 |
|
|
wsp 001400 -- sp=1400
|
| 6338 |
30 |
wfjm |
cres
|
| 6339 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6340 |
|
|
wtgo
|
| 6341 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6342 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6343 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6344 |
|
|
brm 14
|
| 6345 |
|
|
d=000004 -- ! rol 000000 -> n0z1v0c0; 000000
|
| 6346 |
|
|
d=000000 -- !
|
| 6347 |
|
|
d=000000 -- ! rol 000001 -> n0z0v0c0; 000002
|
| 6348 |
|
|
d=000002 -- !
|
| 6349 |
|
|
d=000007 -- ! rol 100000 -> n0z1v1c1; 000000
|
| 6350 |
|
|
d=000000 -- !
|
| 6351 |
|
|
d=000000 -- ! rol 000100 -> n0z0v0c0; 000200
|
| 6352 |
|
|
d=000200 -- !
|
| 6353 |
|
|
d=000000 -- ! rol 000101 -> n0z0v0c0; 000202
|
| 6354 |
|
|
d=000202 -- !
|
| 6355 |
|
|
d=000012 -- ! rol 040100 -> n1z0v1c0; 100200
|
| 6356 |
|
|
d=100200 -- !
|
| 6357 |
|
|
d=000003 -- ! rol 100100 -> n0z0v1c1; 000200
|
| 6358 |
|
|
d=000200 -- !
|
| 6359 |
|
|
#--------
|
| 6360 |
|
|
C Exec test 46.9wrc1: ROL - reg, C=1
|
| 6361 |
|
|
#
|
| 6362 |
|
|
wal 013204 -- setup test instructions:
|
| 6363 |
|
|
bwm 2
|
| 6364 |
|
|
000261 -- ccmov= sec
|
| 6365 |
|
|
006105 -- iut= rol r5
|
| 6366 |
|
|
wr0 177776 -- r0=177776
|
| 6367 |
|
|
wr1 000007 -- r1=7
|
| 6368 |
|
|
wr2 036000 -- r2=36000
|
| 6369 |
|
|
wr3 037000 -- r3=37000
|
| 6370 |
|
|
wr4 000000 -- r4=0
|
| 6371 |
|
|
wr5 000000 -- r5=0
|
| 6372 |
|
|
wsp 001400 -- sp=1400
|
| 6373 |
30 |
wfjm |
cres
|
| 6374 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6375 |
|
|
wtgo
|
| 6376 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6377 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6378 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6379 |
|
|
brm 14
|
| 6380 |
|
|
d=000000 -- ! rol 000000 -> n0z0v0c0; 000001
|
| 6381 |
|
|
d=000001 -- !
|
| 6382 |
|
|
d=000000 -- ! rol 000001 -> n0z0v0c0; 000003
|
| 6383 |
|
|
d=000003 -- !
|
| 6384 |
|
|
d=000003 -- ! rol 100000 -> n0z0v1c1; 000001
|
| 6385 |
|
|
d=000001 -- !
|
| 6386 |
|
|
d=000000 -- ! rol 000100 -> n0z0v0c0; 000201
|
| 6387 |
|
|
d=000201 -- !
|
| 6388 |
|
|
d=000000 -- ! rol 000101 -> n0z0v0c0; 000203
|
| 6389 |
|
|
d=000203 -- !
|
| 6390 |
|
|
d=000012 -- ! rol 040100 -> n1z0v1c0; 100201
|
| 6391 |
|
|
d=100201 -- !
|
| 6392 |
|
|
d=000003 -- ! rol 100100 -> n0z0v1c1; 000201
|
| 6393 |
|
|
d=000201 -- !
|
| 6394 |
|
|
#--------
|
| 6395 |
|
|
C Exec test 46.10wrc0: ASR - reg, C=0
|
| 6396 |
|
|
#
|
| 6397 |
|
|
wal 013204 -- setup test instructions:
|
| 6398 |
|
|
bwm 2
|
| 6399 |
|
|
000241 -- ccmov= clc
|
| 6400 |
|
|
006205 -- iut= asr r5
|
| 6401 |
|
|
wr0 177776 -- r0=177776
|
| 6402 |
|
|
wr1 000007 -- r1=7
|
| 6403 |
|
|
wr2 036000 -- r2=36000
|
| 6404 |
|
|
wr3 037000 -- r3=37000
|
| 6405 |
|
|
wr4 000000 -- r4=0
|
| 6406 |
|
|
wr5 000000 -- r5=0
|
| 6407 |
|
|
wsp 001400 -- sp=1400
|
| 6408 |
30 |
wfjm |
cres
|
| 6409 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6410 |
|
|
wtgo
|
| 6411 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6412 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6413 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6414 |
|
|
brm 14
|
| 6415 |
|
|
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
|
| 6416 |
|
|
d=000000 -- !
|
| 6417 |
|
|
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
|
| 6418 |
|
|
d=000000 -- !
|
| 6419 |
|
|
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
|
| 6420 |
|
|
d=140000 -- !
|
| 6421 |
|
|
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
|
| 6422 |
|
|
d=000040 -- !
|
| 6423 |
|
|
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
|
| 6424 |
|
|
d=000040 -- !
|
| 6425 |
|
|
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
|
| 6426 |
|
|
d=020040 -- !
|
| 6427 |
|
|
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
|
| 6428 |
|
|
d=140040 -- !
|
| 6429 |
|
|
#--------
|
| 6430 |
|
|
C Exec test 46.10wrc1: ASR - reg, C=1
|
| 6431 |
|
|
#
|
| 6432 |
|
|
wal 013204 -- setup test instructions:
|
| 6433 |
|
|
bwm 2
|
| 6434 |
|
|
000261 -- ccmov= sec
|
| 6435 |
|
|
006205 -- iut= asr r5
|
| 6436 |
|
|
wr0 177776 -- r0=177776
|
| 6437 |
|
|
wr1 000007 -- r1=7
|
| 6438 |
|
|
wr2 036000 -- r2=36000
|
| 6439 |
|
|
wr3 037000 -- r3=37000
|
| 6440 |
|
|
wr4 000000 -- r4=0
|
| 6441 |
|
|
wr5 000000 -- r5=0
|
| 6442 |
|
|
wsp 001400 -- sp=1400
|
| 6443 |
30 |
wfjm |
cres
|
| 6444 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6445 |
|
|
wtgo
|
| 6446 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6447 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6448 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6449 |
|
|
brm 14
|
| 6450 |
|
|
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
|
| 6451 |
|
|
d=000000 -- !
|
| 6452 |
|
|
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
|
| 6453 |
|
|
d=000000 -- !
|
| 6454 |
|
|
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
|
| 6455 |
|
|
d=140000 -- !
|
| 6456 |
|
|
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
|
| 6457 |
|
|
d=000040 -- !
|
| 6458 |
|
|
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
|
| 6459 |
|
|
d=000040 -- !
|
| 6460 |
|
|
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
|
| 6461 |
|
|
d=020040 -- !
|
| 6462 |
|
|
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
|
| 6463 |
|
|
d=140040 -- !
|
| 6464 |
|
|
#--------
|
| 6465 |
|
|
C Exec test 46.11wrc0: ASL - reg, C=0
|
| 6466 |
|
|
#
|
| 6467 |
|
|
wal 013204 -- setup test instructions:
|
| 6468 |
|
|
bwm 2
|
| 6469 |
|
|
000241 -- ccmov= clc
|
| 6470 |
|
|
006305 -- iut= asl r5
|
| 6471 |
|
|
wr0 177776 -- r0=177776
|
| 6472 |
|
|
wr1 000007 -- r1=7
|
| 6473 |
|
|
wr2 036000 -- r2=36000
|
| 6474 |
|
|
wr3 037000 -- r3=37000
|
| 6475 |
|
|
wr4 000000 -- r4=0
|
| 6476 |
|
|
wr5 000000 -- r5=0
|
| 6477 |
|
|
wsp 001400 -- sp=1400
|
| 6478 |
30 |
wfjm |
cres
|
| 6479 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6480 |
|
|
wtgo
|
| 6481 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6482 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6483 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6484 |
|
|
brm 14
|
| 6485 |
|
|
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
|
| 6486 |
|
|
d=000000 -- !
|
| 6487 |
|
|
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
|
| 6488 |
|
|
d=000002 -- !
|
| 6489 |
|
|
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
|
| 6490 |
|
|
d=000000 -- !
|
| 6491 |
|
|
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
|
| 6492 |
|
|
d=000200 -- !
|
| 6493 |
|
|
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
|
| 6494 |
|
|
d=000202 -- !
|
| 6495 |
|
|
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
|
| 6496 |
|
|
d=100200 -- !
|
| 6497 |
|
|
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
|
| 6498 |
|
|
d=000200 -- !
|
| 6499 |
|
|
#--------
|
| 6500 |
|
|
C Exec test 46.11wrc1: ASL - reg, C=1
|
| 6501 |
|
|
#
|
| 6502 |
|
|
wal 013204 -- setup test instructions:
|
| 6503 |
|
|
bwm 2
|
| 6504 |
|
|
000261 -- ccmov= sec
|
| 6505 |
|
|
006305 -- iut= asl r5
|
| 6506 |
|
|
wr0 177776 -- r0=177776
|
| 6507 |
|
|
wr1 000007 -- r1=7
|
| 6508 |
|
|
wr2 036000 -- r2=36000
|
| 6509 |
|
|
wr3 037000 -- r3=37000
|
| 6510 |
|
|
wr4 000000 -- r4=0
|
| 6511 |
|
|
wr5 000000 -- r5=0
|
| 6512 |
|
|
wsp 001400 -- sp=1400
|
| 6513 |
30 |
wfjm |
cres
|
| 6514 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 6515 |
|
|
wtgo
|
| 6516 |
|
|
rpc d=013220 -- ! pc=halt
|
| 6517 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6518 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 6519 |
|
|
brm 14
|
| 6520 |
|
|
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
|
| 6521 |
|
|
d=000000 -- !
|
| 6522 |
|
|
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
|
| 6523 |
|
|
d=000002 -- !
|
| 6524 |
|
|
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
|
| 6525 |
|
|
d=000000 -- !
|
| 6526 |
|
|
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
|
| 6527 |
|
|
d=000200 -- !
|
| 6528 |
|
|
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
|
| 6529 |
|
|
d=000202 -- !
|
| 6530 |
|
|
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
|
| 6531 |
|
|
d=100200 -- !
|
| 6532 |
|
|
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
|
| 6533 |
|
|
d=000200 -- !
|
| 6534 |
|
|
#--------
|
| 6535 |
|
|
C Exec test 46.12wrc0: MOV - reg, C=0
|
| 6536 |
|
|
#
|
| 6537 |
|
|
wal 036000 -- setup test vector: for mov
|
| 6538 |
|
|
bwm 6
|
| 6539 |
|
|
000000 -- mov 000000,000000
|
| 6540 |
|
|
000000 --
|
| 6541 |
|
|
000001 -- mov 000001,000000
|
| 6542 |
|
|
000000 --
|
| 6543 |
|
|
100000 -- mov 100000,000000
|
| 6544 |
|
|
000000 --
|
| 6545 |
|
|
wal 013246 -- setup test instructions:
|
| 6546 |
|
|
bwm 2
|
| 6547 |
|
|
000241 -- ccmov= clc
|
| 6548 |
|
|
010405 -- iut= mov r4,r5
|
| 6549 |
|
|
wr0 177776 -- r0=177776
|
| 6550 |
|
|
wr1 000003 -- r1=3
|
| 6551 |
|
|
wr2 036000 -- r2=36000
|
| 6552 |
|
|
wr3 037000 -- r3=37000
|
| 6553 |
|
|
wr4 000000 -- r4=0
|
| 6554 |
|
|
wr5 000000 -- r5=0
|
| 6555 |
|
|
wsp 001400 -- sp=1400
|
| 6556 |
30 |
wfjm |
cres
|
| 6557 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6558 |
|
|
wtgo
|
| 6559 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6560 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6561 |
|
|
wal 037000 -- check result area
|
| 6562 |
|
|
brm 6
|
| 6563 |
|
|
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
|
| 6564 |
|
|
d=000000 -- !
|
| 6565 |
|
|
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
|
| 6566 |
|
|
d=000001 -- !
|
| 6567 |
|
|
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
|
| 6568 |
|
|
d=100000 -- !
|
| 6569 |
|
|
#--------
|
| 6570 |
|
|
C Exec test 46.12wrc1: MOV - reg, C=1
|
| 6571 |
|
|
#
|
| 6572 |
|
|
wal 013246 -- setup test instructions:
|
| 6573 |
|
|
bwm 2
|
| 6574 |
|
|
000261 -- ccmov= sec
|
| 6575 |
|
|
010405 -- iut= mov r4,r5
|
| 6576 |
|
|
wr0 177776 -- r0=177776
|
| 6577 |
|
|
wr1 000003 -- r1=3
|
| 6578 |
|
|
wr2 036000 -- r2=36000
|
| 6579 |
|
|
wr3 037000 -- r3=37000
|
| 6580 |
|
|
wr4 000000 -- r4=0
|
| 6581 |
|
|
wr5 000000 -- r5=0
|
| 6582 |
|
|
wsp 001400 -- sp=1400
|
| 6583 |
30 |
wfjm |
cres
|
| 6584 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6585 |
|
|
wtgo
|
| 6586 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6587 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6588 |
|
|
wal 037000 -- check result area
|
| 6589 |
|
|
brm 6
|
| 6590 |
|
|
d=000005 -- ! mov 000000,000000 -> n0z1v0c1; 000000
|
| 6591 |
|
|
d=000000 -- !
|
| 6592 |
|
|
d=000001 -- ! mov 000001,000000 -> n0z0v0c1; 000001
|
| 6593 |
|
|
d=000001 -- !
|
| 6594 |
|
|
d=000011 -- ! mov 100000,000000 -> n1z0v0c1; 100000
|
| 6595 |
|
|
d=100000 -- !
|
| 6596 |
|
|
#--------
|
| 6597 |
|
|
C Exec test 46.12mc0: MOV - mem, C=0
|
| 6598 |
|
|
#
|
| 6599 |
|
|
wal 013276 -- setup test instructions:
|
| 6600 |
|
|
bwm 2
|
| 6601 |
|
|
000241 -- ccmov= clc
|
| 6602 |
|
|
011415 -- iut= mov (r4),(r5)
|
| 6603 |
|
|
wr0 177776 -- r0=177776
|
| 6604 |
|
|
wr1 000003 -- r1=3
|
| 6605 |
|
|
wr2 036000 -- r2=36000
|
| 6606 |
|
|
wr3 037000 -- r3=37000
|
| 6607 |
|
|
wr4 001400 -- r4=1400
|
| 6608 |
|
|
wr5 001402 -- r5=1402
|
| 6609 |
|
|
wsp 001400 -- sp=1400
|
| 6610 |
30 |
wfjm |
cres
|
| 6611 |
2 |
wfjm |
stapc 013270 -- start @ 13270 (2op mem)
|
| 6612 |
|
|
wtgo
|
| 6613 |
|
|
rpc d=013312 -- ! pc=halt
|
| 6614 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6615 |
|
|
wal 037000 -- check result area
|
| 6616 |
|
|
brm 6
|
| 6617 |
|
|
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
|
| 6618 |
|
|
d=000000 -- !
|
| 6619 |
|
|
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
|
| 6620 |
|
|
d=000001 -- !
|
| 6621 |
|
|
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
|
| 6622 |
|
|
d=100000 -- !
|
| 6623 |
|
|
#--------
|
| 6624 |
|
|
C Exec test 46.13wrc0: BIT - reg, C=0
|
| 6625 |
|
|
#
|
| 6626 |
|
|
wal 036000 -- setup test vector: for bit,bic,bis,xor
|
| 6627 |
|
|
bwm 12
|
| 6628 |
|
|
000000 -- bit 000000,000000
|
| 6629 |
|
|
000000 --
|
| 6630 |
|
|
000011 -- bit 000011,000000
|
| 6631 |
|
|
000000 --
|
| 6632 |
|
|
000011 -- bit 000011,000110
|
| 6633 |
|
|
000110 --
|
| 6634 |
|
|
000011 -- bit 000011,001100
|
| 6635 |
|
|
001100 --
|
| 6636 |
|
|
110000 -- bit 110000,011000
|
| 6637 |
|
|
011000 --
|
| 6638 |
|
|
110000 -- bit 110000,110000
|
| 6639 |
|
|
110000 --
|
| 6640 |
|
|
wal 013246 -- setup test instructions:
|
| 6641 |
|
|
bwm 2
|
| 6642 |
|
|
000241 -- ccmov= clc
|
| 6643 |
|
|
030405 -- iut= bit r4,r5
|
| 6644 |
|
|
wr0 177776 -- r0=177776
|
| 6645 |
|
|
wr1 000006 -- r1=6
|
| 6646 |
|
|
wr2 036000 -- r2=36000
|
| 6647 |
|
|
wr3 037000 -- r3=37000
|
| 6648 |
|
|
wr4 000000 -- r4=0
|
| 6649 |
|
|
wr5 000000 -- r5=0
|
| 6650 |
|
|
wsp 001400 -- sp=1400
|
| 6651 |
30 |
wfjm |
cres
|
| 6652 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6653 |
|
|
wtgo
|
| 6654 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6655 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6656 |
|
|
wal 037000 -- check result area
|
| 6657 |
|
|
brm 12
|
| 6658 |
|
|
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
|
| 6659 |
|
|
d=000000 -- !
|
| 6660 |
|
|
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
|
| 6661 |
|
|
d=000000 -- !
|
| 6662 |
|
|
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
|
| 6663 |
|
|
d=000110 -- !
|
| 6664 |
|
|
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
|
| 6665 |
|
|
d=001100 -- !
|
| 6666 |
|
|
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
|
| 6667 |
|
|
d=011000 -- !
|
| 6668 |
|
|
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
|
| 6669 |
|
|
d=110000 -- !
|
| 6670 |
|
|
#--------
|
| 6671 |
|
|
C Exec test 46.13wrc1: BIT - reg, C=1
|
| 6672 |
|
|
#
|
| 6673 |
|
|
wal 013246 -- setup test instructions:
|
| 6674 |
|
|
bwm 2
|
| 6675 |
|
|
000261 -- ccmov= sec
|
| 6676 |
|
|
030405 -- iut= bit r4,r5
|
| 6677 |
|
|
wr0 177776 -- r0=177776
|
| 6678 |
|
|
wr1 000006 -- r1=6
|
| 6679 |
|
|
wr2 036000 -- r2=36000
|
| 6680 |
|
|
wr3 037000 -- r3=37000
|
| 6681 |
|
|
wr4 000000 -- r4=0
|
| 6682 |
|
|
wr5 000000 -- r5=0
|
| 6683 |
|
|
wsp 001400 -- sp=1400
|
| 6684 |
30 |
wfjm |
cres
|
| 6685 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6686 |
|
|
wtgo
|
| 6687 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6688 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6689 |
|
|
wal 037000 -- check result area
|
| 6690 |
|
|
brm 12
|
| 6691 |
|
|
d=000005 -- ! bit 000000,000000 -> n0z1v0c1; (000000)
|
| 6692 |
|
|
d=000000 -- !
|
| 6693 |
|
|
d=000005 -- ! bit 000011,000000 -> n0z1v0c1; (000000)
|
| 6694 |
|
|
d=000000 -- !
|
| 6695 |
|
|
d=000001 -- ! bit 000011,000110 -> n0z0v0c1; (000010)
|
| 6696 |
|
|
d=000110 -- !
|
| 6697 |
|
|
d=000005 -- ! bit 000011,001100 -> n0z1v0c1; (000000)
|
| 6698 |
|
|
d=001100 -- !
|
| 6699 |
|
|
d=000001 -- ! bit 110000,011000 -> n0z0v0c1; (010000)
|
| 6700 |
|
|
d=011000 -- !
|
| 6701 |
|
|
d=000011 -- ! bit 110000,110000 -> n1z0v0c1; (100000)
|
| 6702 |
|
|
d=110000 -- !
|
| 6703 |
|
|
#--------
|
| 6704 |
|
|
C Exec test 46.13wmc0: BIT - mem, C=0
|
| 6705 |
|
|
#
|
| 6706 |
|
|
wal 013276 -- setup test instructions:
|
| 6707 |
|
|
bwm 2
|
| 6708 |
|
|
000241 -- ccmov= clc
|
| 6709 |
|
|
031415 -- iut= bit (r4),(r5)
|
| 6710 |
|
|
wr0 177776 -- r0=177776
|
| 6711 |
|
|
wr1 000006 -- r1=6
|
| 6712 |
|
|
wr2 036000 -- r2=36000
|
| 6713 |
|
|
wr3 037000 -- r3=37000
|
| 6714 |
|
|
wr4 001400 -- r4=1400
|
| 6715 |
|
|
wr5 001402 -- r5=1402
|
| 6716 |
|
|
wsp 001400 -- sp=1400
|
| 6717 |
30 |
wfjm |
cres
|
| 6718 |
2 |
wfjm |
stapc 013270 -- start @ 13270 (2op mem)
|
| 6719 |
|
|
wtgo
|
| 6720 |
|
|
rpc d=013312 -- ! pc=halt
|
| 6721 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6722 |
|
|
wal 037000 -- check result area
|
| 6723 |
|
|
brm 12
|
| 6724 |
|
|
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
|
| 6725 |
|
|
d=000000 -- !
|
| 6726 |
|
|
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
|
| 6727 |
|
|
d=000000 -- !
|
| 6728 |
|
|
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
|
| 6729 |
|
|
d=000110 -- !
|
| 6730 |
|
|
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
|
| 6731 |
|
|
d=001100 -- !
|
| 6732 |
|
|
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
|
| 6733 |
|
|
d=011000 -- !
|
| 6734 |
|
|
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
|
| 6735 |
|
|
d=110000 -- !
|
| 6736 |
|
|
#--------
|
| 6737 |
|
|
C Exec test 46.14wrc0: BIC - reg, C=0
|
| 6738 |
|
|
#
|
| 6739 |
|
|
wal 013246 -- setup test instructions:
|
| 6740 |
|
|
bwm 2
|
| 6741 |
|
|
000241 -- ccmov= clc
|
| 6742 |
|
|
040405 -- iut= bic r4,r5
|
| 6743 |
|
|
wr0 177776 -- r0=177776
|
| 6744 |
|
|
wr1 000006 -- r1=6
|
| 6745 |
|
|
wr2 036000 -- r2=36000
|
| 6746 |
|
|
wr3 037000 -- r3=37000
|
| 6747 |
|
|
wr4 000000 -- r4=0
|
| 6748 |
|
|
wr5 000000 -- r5=0
|
| 6749 |
|
|
wsp 001400 -- sp=1400
|
| 6750 |
30 |
wfjm |
cres
|
| 6751 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6752 |
|
|
wtgo
|
| 6753 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6754 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6755 |
|
|
wal 037000 -- check result area
|
| 6756 |
|
|
brm 12
|
| 6757 |
|
|
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
|
| 6758 |
|
|
d=000000 -- !
|
| 6759 |
|
|
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
|
| 6760 |
|
|
d=000000 -- !
|
| 6761 |
|
|
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
|
| 6762 |
|
|
d=000100 -- !
|
| 6763 |
|
|
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
|
| 6764 |
|
|
d=001100 -- !
|
| 6765 |
|
|
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
|
| 6766 |
|
|
d=001000 -- !
|
| 6767 |
|
|
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
|
| 6768 |
|
|
d=000000 -- !
|
| 6769 |
|
|
#--------
|
| 6770 |
|
|
C Exec test 46.14wrc1: BIC - reg, C=1
|
| 6771 |
|
|
#
|
| 6772 |
|
|
wal 013246 -- setup test instructions:
|
| 6773 |
|
|
bwm 2
|
| 6774 |
|
|
000261 -- ccmov= sec
|
| 6775 |
|
|
040405 -- iut= bic r4,r5
|
| 6776 |
|
|
wr0 177776 -- r0=177776
|
| 6777 |
|
|
wr1 000006 -- r1=6
|
| 6778 |
|
|
wr2 036000 -- r2=36000
|
| 6779 |
|
|
wr3 037000 -- r3=37000
|
| 6780 |
|
|
wr4 000000 -- r4=0
|
| 6781 |
|
|
wr5 000000 -- r5=0
|
| 6782 |
|
|
wsp 001400 -- sp=1400
|
| 6783 |
30 |
wfjm |
cres
|
| 6784 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6785 |
|
|
wtgo
|
| 6786 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6787 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6788 |
|
|
wal 037000 -- check result area
|
| 6789 |
|
|
brm 12
|
| 6790 |
|
|
d=000005 -- ! bic 000000,000000 -> n0z1v0c1; 000000
|
| 6791 |
|
|
d=000000 -- !
|
| 6792 |
|
|
d=000005 -- ! bic 000011,000000 -> n0z1v0c1; 000000
|
| 6793 |
|
|
d=000000 -- !
|
| 6794 |
|
|
d=000001 -- ! bic 000011,000110 -> n0z0v0c1; 000100
|
| 6795 |
|
|
d=000100 -- !
|
| 6796 |
|
|
d=000001 -- ! bic 000011,001100 -> n0z0v0c1; 001100
|
| 6797 |
|
|
d=001100 -- !
|
| 6798 |
|
|
d=000001 -- ! bic 110000,011000 -> n0z0v0c1; 001000
|
| 6799 |
|
|
d=001000 -- !
|
| 6800 |
|
|
d=000005 -- ! bic 110000,110000 -> n0z1v0c1; 000000
|
| 6801 |
|
|
d=000000 -- !
|
| 6802 |
|
|
#--------
|
| 6803 |
|
|
C Exec test 46.14wrc0: BIC - mem, C=0
|
| 6804 |
|
|
#
|
| 6805 |
|
|
wal 013276 -- setup test instructions:
|
| 6806 |
|
|
bwm 2
|
| 6807 |
|
|
000241 -- ccmov= clc
|
| 6808 |
|
|
041415 -- iut= bic (r4),(r5)
|
| 6809 |
|
|
wr0 177776 -- r0=177776
|
| 6810 |
|
|
wr1 000006 -- r1=6
|
| 6811 |
|
|
wr2 036000 -- r2=36000
|
| 6812 |
|
|
wr3 037000 -- r3=37000
|
| 6813 |
|
|
wr4 001400 -- r4=1400
|
| 6814 |
|
|
wr5 001402 -- r5=1402
|
| 6815 |
|
|
wsp 001400 -- sp=1400
|
| 6816 |
30 |
wfjm |
cres
|
| 6817 |
2 |
wfjm |
stapc 013270 -- start @ 13270 (2op mem)
|
| 6818 |
|
|
wtgo
|
| 6819 |
|
|
rpc d=013312 -- ! pc=halt
|
| 6820 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6821 |
|
|
wal 037000 -- check result area
|
| 6822 |
|
|
brm 12
|
| 6823 |
|
|
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
|
| 6824 |
|
|
d=000000 -- !
|
| 6825 |
|
|
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
|
| 6826 |
|
|
d=000000 -- !
|
| 6827 |
|
|
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
|
| 6828 |
|
|
d=000100 -- !
|
| 6829 |
|
|
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
|
| 6830 |
|
|
d=001100 -- !
|
| 6831 |
|
|
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
|
| 6832 |
|
|
d=001000 -- !
|
| 6833 |
|
|
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
|
| 6834 |
|
|
d=000000 -- !
|
| 6835 |
|
|
#--------
|
| 6836 |
|
|
C Exec test 46.15wrc0: BIS - reg, C=0
|
| 6837 |
|
|
#
|
| 6838 |
|
|
wal 013246 -- setup test instructions:
|
| 6839 |
|
|
bwm 2
|
| 6840 |
|
|
000241 -- ccmov= clc
|
| 6841 |
|
|
050405 -- iut= bis r4,r5
|
| 6842 |
|
|
wr0 177776 -- r0=177776
|
| 6843 |
|
|
wr1 000006 -- r1=6
|
| 6844 |
|
|
wr2 036000 -- r2=36000
|
| 6845 |
|
|
wr3 037000 -- r3=37000
|
| 6846 |
|
|
wr4 000000 -- r4=0
|
| 6847 |
|
|
wr5 000000 -- r5=0
|
| 6848 |
|
|
wsp 001400 -- sp=1400
|
| 6849 |
30 |
wfjm |
cres
|
| 6850 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6851 |
|
|
wtgo
|
| 6852 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6853 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6854 |
|
|
wal 037000 -- check result area
|
| 6855 |
|
|
brm 12
|
| 6856 |
|
|
d=000004 -- ! bis 000000,000000 -> n0z1v0c0; 000000
|
| 6857 |
|
|
d=000000 -- !
|
| 6858 |
|
|
d=000000 -- ! bis 000011,000000 -> n0z0v0c0; 000011
|
| 6859 |
|
|
d=000011 -- !
|
| 6860 |
|
|
d=000000 -- ! bis 000011,000110 -> n0z0v0c0; 000111
|
| 6861 |
|
|
d=000111 -- !
|
| 6862 |
|
|
d=000000 -- ! bis 000011,001100 -> n0z0v0c0; 001111
|
| 6863 |
|
|
d=001111 -- !
|
| 6864 |
|
|
d=000010 -- ! bis 110000,011000 -> n1z0v0c0; 111000
|
| 6865 |
|
|
d=111000 -- !
|
| 6866 |
|
|
d=000010 -- ! bis 110000,110000 -> n1z0v0c0; 110000
|
| 6867 |
|
|
d=110000 -- !
|
| 6868 |
|
|
#--------
|
| 6869 |
|
|
C Exec test 46.15wrc1: BIS - reg, C=1
|
| 6870 |
|
|
#
|
| 6871 |
|
|
wal 013246 -- setup test instructions:
|
| 6872 |
|
|
bwm 2
|
| 6873 |
|
|
000261 -- ccmov= sec
|
| 6874 |
|
|
050405 -- iut= bis r4,r5
|
| 6875 |
|
|
wr0 177776 -- r0=177776
|
| 6876 |
|
|
wr1 000006 -- r1=6
|
| 6877 |
|
|
wr2 036000 -- r2=36000
|
| 6878 |
|
|
wr3 037000 -- r3=37000
|
| 6879 |
|
|
wr4 000000 -- r4=0
|
| 6880 |
|
|
wr5 000000 -- r5=0
|
| 6881 |
|
|
wsp 001400 -- sp=1400
|
| 6882 |
30 |
wfjm |
cres
|
| 6883 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6884 |
|
|
wtgo
|
| 6885 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6886 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6887 |
|
|
wal 037000 -- check result area
|
| 6888 |
|
|
brm 12
|
| 6889 |
|
|
d=000005 -- ! bis 000000,000000 -> n0z1v0c1; 000000
|
| 6890 |
|
|
d=000000 -- !
|
| 6891 |
|
|
d=000001 -- ! bis 000011,000000 -> n0z0v0c1; 000011
|
| 6892 |
|
|
d=000011 -- !
|
| 6893 |
|
|
d=000001 -- ! bis 000011,000110 -> n0z0v0c1; 000111
|
| 6894 |
|
|
d=000111 -- !
|
| 6895 |
|
|
d=000001 -- ! bis 000011,001100 -> n0z0v0c1; 001111
|
| 6896 |
|
|
d=001111 -- !
|
| 6897 |
|
|
d=000011 -- ! bis 110000,011000 -> n1z0v0c1; 111000
|
| 6898 |
|
|
d=111000 -- !
|
| 6899 |
|
|
d=000011 -- ! bis 110000,110000 -> n1z0v0c1; 110000
|
| 6900 |
|
|
d=110000 -- !
|
| 6901 |
|
|
#--------
|
| 6902 |
|
|
C Exec test 46.16wrc0: XOR - reg, C=0
|
| 6903 |
|
|
#
|
| 6904 |
|
|
wal 013246 -- setup test instructions:
|
| 6905 |
|
|
bwm 2
|
| 6906 |
|
|
000241 -- ccmov= clc
|
| 6907 |
|
|
074405 -- iut= xor r4,r5
|
| 6908 |
|
|
wr0 177776 -- r0=177776
|
| 6909 |
|
|
wr1 000006 -- r1=6
|
| 6910 |
|
|
wr2 036000 -- r2=36000
|
| 6911 |
|
|
wr3 037000 -- r3=37000
|
| 6912 |
|
|
wr4 000000 -- r4=0
|
| 6913 |
|
|
wr5 000000 -- r5=0
|
| 6914 |
|
|
wsp 001400 -- sp=1400
|
| 6915 |
30 |
wfjm |
cres
|
| 6916 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6917 |
|
|
wtgo
|
| 6918 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6919 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6920 |
|
|
wal 037000 -- check result area
|
| 6921 |
|
|
brm 12
|
| 6922 |
|
|
d=000004 -- ! xor 000000,000000 -> n0z1v0c0; 000000
|
| 6923 |
|
|
d=000000 -- !
|
| 6924 |
|
|
d=000000 -- ! xor 000011,000000 -> n0z0v0c0; 000011
|
| 6925 |
|
|
d=000011 -- !
|
| 6926 |
|
|
d=000000 -- ! xor 000011,000110 -> n0z0v0c0; 000101
|
| 6927 |
|
|
d=000101 -- !
|
| 6928 |
|
|
d=000000 -- ! xor 000011,001100 -> n0z0v0c0; 001111
|
| 6929 |
|
|
d=001111 -- !
|
| 6930 |
|
|
d=000010 -- ! xor 110000,011000 -> n1z0v0c0; 101000
|
| 6931 |
|
|
d=101000 -- !
|
| 6932 |
|
|
d=000004 -- ! xor 110000,110000 -> n1z0v0c0; 000000
|
| 6933 |
|
|
d=000000 -- !
|
| 6934 |
|
|
#--------
|
| 6935 |
|
|
C Exec test 46.16wrc1: XOR - reg, C=1
|
| 6936 |
|
|
#
|
| 6937 |
|
|
wal 013246 -- setup test instructions:
|
| 6938 |
|
|
bwm 2
|
| 6939 |
|
|
000261 -- ccmov= sec
|
| 6940 |
|
|
074405 -- iut= xor r4,r5
|
| 6941 |
|
|
wr0 177776 -- r0=177776
|
| 6942 |
|
|
wr1 000006 -- r1=6
|
| 6943 |
|
|
wr2 036000 -- r2=36000
|
| 6944 |
|
|
wr3 037000 -- r3=37000
|
| 6945 |
|
|
wr4 000000 -- r4=0
|
| 6946 |
|
|
wr5 000000 -- r5=0
|
| 6947 |
|
|
wsp 001400 -- sp=1400
|
| 6948 |
30 |
wfjm |
cres
|
| 6949 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 6950 |
|
|
wtgo
|
| 6951 |
|
|
rpc d=013262 -- ! pc=halt
|
| 6952 |
|
|
rr1 d=000000 -- ! r1=0
|
| 6953 |
|
|
wal 037000 -- check result area
|
| 6954 |
|
|
brm 12
|
| 6955 |
|
|
d=000005 -- ! xor 000000,000000 -> n0z1v0c1; 000000
|
| 6956 |
|
|
d=000000 -- !
|
| 6957 |
|
|
d=000001 -- ! xor 000011,000000 -> n0z0v0c1; 000011
|
| 6958 |
|
|
d=000011 -- !
|
| 6959 |
|
|
d=000001 -- ! xor 000011,000110 -> n0z0v0c1; 000101
|
| 6960 |
|
|
d=000101 -- !
|
| 6961 |
|
|
d=000001 -- ! xor 000011,001100 -> n0z0v0c1; 001111
|
| 6962 |
|
|
d=001111 -- !
|
| 6963 |
|
|
d=000011 -- ! xor 110000,011000 -> n1z0v0c1; 101000
|
| 6964 |
|
|
d=101000 -- !
|
| 6965 |
|
|
d=000005 -- ! xor 110000,110000 -> n1z0v0c1; 000000
|
| 6966 |
|
|
d=000000 -- !
|
| 6967 |
|
|
#--------
|
| 6968 |
|
|
C Exec test 46.17wr: CMP - reg
|
| 6969 |
|
|
#
|
| 6970 |
|
|
wal 036000 -- setup test vector: for cmp,add,sub
|
| 6971 |
|
|
bwm 38
|
| 6972 |
|
|
000000 -- cmp 000000,000000
|
| 6973 |
|
|
000000 --
|
| 6974 |
|
|
000001 -- cmp 000001,000000
|
| 6975 |
|
|
000000 --
|
| 6976 |
|
|
177777 -- cmp 177777,000000
|
| 6977 |
|
|
000000 --
|
| 6978 |
|
|
000000 -- cmp 000000,000001
|
| 6979 |
|
|
000001 --
|
| 6980 |
|
|
000001 -- cmp 000001,000001
|
| 6981 |
|
|
000001 --
|
| 6982 |
|
|
177777 -- cmp 177777,000001
|
| 6983 |
|
|
000001 --
|
| 6984 |
|
|
077776 -- cmp 077776,077777
|
| 6985 |
|
|
077777 --
|
| 6986 |
|
|
077777 -- cmp 077777,077777
|
| 6987 |
|
|
077777 --
|
| 6988 |
|
|
100000 -- cmp 100000,077777
|
| 6989 |
|
|
077777 --
|
| 6990 |
|
|
000001 -- cmp 000001,077777
|
| 6991 |
|
|
077777 --
|
| 6992 |
|
|
177777 -- cmp 177777,077777
|
| 6993 |
|
|
077777 --
|
| 6994 |
|
|
077777 -- cmp 077777,100000
|
| 6995 |
|
|
100000 --
|
| 6996 |
|
|
100000 -- cmp 100000,100000
|
| 6997 |
|
|
100000 --
|
| 6998 |
|
|
100001 -- cmp 100001,100000
|
| 6999 |
|
|
100000 --
|
| 7000 |
|
|
000001 -- cmp 000001,100000
|
| 7001 |
|
|
100000 --
|
| 7002 |
|
|
177777 -- cmp 177777,100000
|
| 7003 |
|
|
100000 --
|
| 7004 |
|
|
000000 -- cmp 000000,177777
|
| 7005 |
|
|
177777 --
|
| 7006 |
|
|
000001 -- cmp 000001,177777
|
| 7007 |
|
|
177777 --
|
| 7008 |
|
|
177777 -- cmp 177777,177777
|
| 7009 |
|
|
177777 --
|
| 7010 |
|
|
wal 013246 -- setup test instructions:
|
| 7011 |
|
|
bwm 2
|
| 7012 |
|
|
000241 -- ccmov= clc
|
| 7013 |
|
|
020405 -- iut= cmp r4,r5
|
| 7014 |
|
|
wr0 177776 -- r0=177776
|
| 7015 |
|
|
wr1 000023 -- r1=23 (19.)
|
| 7016 |
|
|
wr2 036000 -- r2=36000
|
| 7017 |
|
|
wr3 037000 -- r3=37000
|
| 7018 |
|
|
wr4 000000 -- r4=0
|
| 7019 |
|
|
wr5 000000 -- r5=0
|
| 7020 |
|
|
wsp 001400 -- sp=1400
|
| 7021 |
30 |
wfjm |
cres
|
| 7022 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 7023 |
|
|
wtgo
|
| 7024 |
|
|
rpc d=013262 -- ! pc=halt
|
| 7025 |
|
|
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
|
| 7026 |
|
|
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
|
| 7027 |
|
|
brm 38
|
| 7028 |
|
|
d=000004 -- ! cmp 000000,000000 -> n0z1v0c0; (000000)
|
| 7029 |
|
|
d=000000 -- !
|
| 7030 |
|
|
d=000000 -- ! cmp 000001,000000 -> n0z0v0c0; (000001)
|
| 7031 |
|
|
d=000000 -- !
|
| 7032 |
|
|
d=000010 -- ! cmp 177777,000000 -> n1z0v0c0; (177777)
|
| 7033 |
|
|
d=000000 -- !
|
| 7034 |
|
|
d=000011 -- ! cmp 000000,000001 -> n1z0v0c1; (177777+C)
|
| 7035 |
|
|
d=000001 -- !
|
| 7036 |
|
|
d=000004 -- ! cmp 000001,000001 -> n0z1v0c0; (000000)
|
| 7037 |
|
|
d=000001 -- !
|
| 7038 |
|
|
d=000010 -- ! cmp 177777,000001 -> n1z0v0c0; (177776)
|
| 7039 |
|
|
d=000001 -- !
|
| 7040 |
|
|
d=000011 -- ! cmp 077776,077777 -> n1z0v0c1; (177777+C)
|
| 7041 |
|
|
d=077777 -- !
|
| 7042 |
|
|
d=000004 -- ! cmp 077777,077777 -> n0z1v0c0; (000000)
|
| 7043 |
|
|
d=077777 -- !
|
| 7044 |
|
|
d=000002 -- ! cmp 100000,077777 -> n0z0v1c0; (000001)
|
| 7045 |
|
|
d=077777 -- !
|
| 7046 |
|
|
d=000011 -- ! cmp 000001,077777 -> n1z0v0c1; (100002+C)
|
| 7047 |
|
|
d=077777 -- !
|
| 7048 |
|
|
d=000010 -- ! cmp 177777,077777 -> n1z0v0c0; (100000)
|
| 7049 |
|
|
d=077777 -- !
|
| 7050 |
|
|
d=000013 -- ! cmp 077777,100000 -> n1z0v1c1; (177777+C)
|
| 7051 |
|
|
d=100000 -- !
|
| 7052 |
|
|
d=000004 -- ! cmp 100000,100000 -> n0z1v0c0; (000000)
|
| 7053 |
|
|
d=100000 -- !
|
| 7054 |
|
|
d=000000 -- ! cmp 100001,100000 -> n0z0v0c0; (000001)
|
| 7055 |
|
|
d=100000 -- !
|
| 7056 |
|
|
d=000013 -- ! cmp 000001,100000 -> n1z0v1c1; (100001+C)
|
| 7057 |
|
|
d=100000 -- !
|
| 7058 |
|
|
d=000000 -- ! cmp 177777,100000 -> n0z0v0c0; (077777)
|
| 7059 |
|
|
d=100000 -- !
|
| 7060 |
|
|
d=000001 -- ! cmp 000000,177777 -> n0z0v0c1; (000001+C)
|
| 7061 |
|
|
d=177777 -- !
|
| 7062 |
|
|
d=000001 -- ! cmp 000001,177777 -> n0z0v0c1; (000002+C)
|
| 7063 |
|
|
d=177777 -- !
|
| 7064 |
|
|
d=000004 -- ! cmp 177777,177777 -> n0z1v0c0; (000000)
|
| 7065 |
|
|
d=177777 -- !
|
| 7066 |
|
|
#--------
|
| 7067 |
|
|
C Exec test 46.18r: ADD - reg
|
| 7068 |
|
|
#
|
| 7069 |
|
|
wal 013246 -- setup test instructions:
|
| 7070 |
|
|
bwm 2
|
| 7071 |
|
|
000241 -- ccmov= clc
|
| 7072 |
|
|
060405 -- iut= add r4,r5
|
| 7073 |
|
|
wr0 177776 -- r0=177776
|
| 7074 |
|
|
wr1 000023 -- r1=23 (19.)
|
| 7075 |
|
|
wr2 036000 -- r2=36000
|
| 7076 |
|
|
wr3 037000 -- r3=37000
|
| 7077 |
|
|
wr4 000000 -- r4=0
|
| 7078 |
|
|
wr5 000000 -- r5=0
|
| 7079 |
|
|
wsp 001400 -- sp=1400
|
| 7080 |
30 |
wfjm |
cres
|
| 7081 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 7082 |
|
|
wtgo
|
| 7083 |
|
|
rpc d=013262 -- ! pc=halt
|
| 7084 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7085 |
|
|
wal 037000 -- check result area (Note: V=1 if s eq d and r neq d)
|
| 7086 |
|
|
brm 38
|
| 7087 |
|
|
d=000004 -- ! add 000000,000000 -> n0z1v0c0; 000000
|
| 7088 |
|
|
d=000000 -- !
|
| 7089 |
|
|
d=000000 -- ! add 000001,000000 -> n0z0v0c0; 000001
|
| 7090 |
|
|
d=000001 -- !
|
| 7091 |
|
|
d=000010 -- ! add 177777,000000 -> n1z0v0c0; 177777
|
| 7092 |
|
|
d=177777 -- !
|
| 7093 |
|
|
d=000000 -- ! add 000000,000001 -> n0z0v0c0; 000001
|
| 7094 |
|
|
d=000001 -- !
|
| 7095 |
|
|
d=000000 -- ! add 000001,000001 -> n0z0v0c0; 000002
|
| 7096 |
|
|
d=000002 -- !
|
| 7097 |
|
|
d=000005 -- ! add 177777,000001 -> n0z1v0c1; 000000+C
|
| 7098 |
|
|
d=000000 -- !
|
| 7099 |
|
|
d=000012 -- ! add 077776,077777 -> n1z0v1c0; 177775
|
| 7100 |
|
|
d=177775 -- !
|
| 7101 |
|
|
d=000012 -- ! add 077777,077777 -> n1z0v1c0; 177776
|
| 7102 |
|
|
d=177776 -- !
|
| 7103 |
|
|
d=000010 -- ! add 100000,077777 -> n1z0v0c0; 177777
|
| 7104 |
|
|
d=177777 -- !
|
| 7105 |
|
|
d=000012 -- ! add 000001,077777 -> n1z0v1c0; 100000
|
| 7106 |
|
|
d=100000 -- !
|
| 7107 |
|
|
d=000001 -- ! add 177777,077777 -> n0z0v0c1; 077776+C
|
| 7108 |
|
|
d=077776 -- !
|
| 7109 |
|
|
d=000010 -- ! add 077777,100000 -> n1z0v0c1; 177777+C
|
| 7110 |
|
|
d=177777 -- !
|
| 7111 |
|
|
d=000007 -- ! add 100000,100000 -> n0z1v1c1; 000000+C
|
| 7112 |
|
|
d=000000 -- !
|
| 7113 |
|
|
d=000003 -- ! add 100001,100000 -> n0z0v1c1; 000001+C
|
| 7114 |
|
|
d=000001 -- !
|
| 7115 |
|
|
d=000010 -- ! add 000001,100000 -> n1z0v0c0; 100001
|
| 7116 |
|
|
d=100001 -- !
|
| 7117 |
|
|
d=000003 -- ! add 177777,100000 -> n0z0v1c1; 077777+C
|
| 7118 |
|
|
d=077777 -- !
|
| 7119 |
|
|
d=000010 -- ! add 000000,177777 -> n1z0v0c0; 177777
|
| 7120 |
|
|
d=177777 -- !
|
| 7121 |
|
|
d=000005 -- ! add 000001,177777 -> n0z1v0c1; 000000+C
|
| 7122 |
|
|
d=000000 -- !
|
| 7123 |
|
|
d=000011 -- ! add 177777,177777 -> n1z0v0c1; 177776+C
|
| 7124 |
|
|
d=177776 -- !
|
| 7125 |
|
|
#--------
|
| 7126 |
|
|
C Exec test 46.19r: SUB - reg
|
| 7127 |
|
|
#
|
| 7128 |
|
|
wal 013246 -- setup test instructions:
|
| 7129 |
|
|
bwm 2
|
| 7130 |
|
|
000241 -- ccmov= clc
|
| 7131 |
|
|
160405 -- iut= sub r4,r5
|
| 7132 |
|
|
wr0 177776 -- r0=177776
|
| 7133 |
|
|
wr1 000023 -- r1=23 (19.)
|
| 7134 |
|
|
wr2 036000 -- r2=36000
|
| 7135 |
|
|
wr3 037000 -- r3=37000
|
| 7136 |
|
|
wr4 000000 -- r4=0
|
| 7137 |
|
|
wr5 000000 -- r5=0
|
| 7138 |
|
|
wsp 001400 -- sp=1400
|
| 7139 |
30 |
wfjm |
cres
|
| 7140 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 7141 |
|
|
wtgo
|
| 7142 |
|
|
rpc d=013262 -- ! pc=halt
|
| 7143 |
|
|
rr1 d=000000 -- ! r1=0 (Note: C=1 if src > dst unsigned)
|
| 7144 |
|
|
wal 037000 -- check result area (Note: V=1 if s xor d and r eq s)
|
| 7145 |
|
|
brm 38
|
| 7146 |
|
|
d=000004 -- ! sub 000000,000000 -> n0z1v0c0; 000000
|
| 7147 |
|
|
d=000000 -- !
|
| 7148 |
|
|
d=000011 -- ! sub 000001,000000 -> n1z0v0c1; 177777+C
|
| 7149 |
|
|
d=177777 -- !
|
| 7150 |
|
|
d=000001 -- ! sub 177777,000000 -> n0z0v0c1; 000001+C
|
| 7151 |
|
|
d=000001 -- !
|
| 7152 |
|
|
d=000000 -- ! sub 000000,000001 -> n0z0v0c0; 000001
|
| 7153 |
|
|
d=000001 -- !
|
| 7154 |
|
|
d=000004 -- ! sub 000001,000001 -> n0z1v0c0; 000000
|
| 7155 |
|
|
d=000000 -- !
|
| 7156 |
|
|
d=000001 -- ! sub 177777,000001 -> n0z0v0c1; 000002+C
|
| 7157 |
|
|
d=000002 -- !
|
| 7158 |
|
|
d=000000 -- ! sub 077776,077777 -> n0z0v0c0; 000001
|
| 7159 |
|
|
d=000001 -- !
|
| 7160 |
|
|
d=000004 -- ! sub 077777,077777 -> n0z1v0c0; 000000
|
| 7161 |
|
|
d=000000 -- !
|
| 7162 |
|
|
d=000013 -- ! sub 100000,077777 -> n1z0v1c1; 177777+C
|
| 7163 |
|
|
d=177777 -- !
|
| 7164 |
|
|
d=000000 -- ! sub 000001,077777 -> n0z0v0c0; 077776
|
| 7165 |
|
|
d=077776 -- !
|
| 7166 |
|
|
d=000013 -- ! sub 177777,077777 -> n1z0v1c1; 100000+C
|
| 7167 |
|
|
d=100000 -- !
|
| 7168 |
|
|
d=000002 -- ! sub 077777,100000 -> n0z0v1c0; 000001
|
| 7169 |
|
|
d=000001 -- !
|
| 7170 |
|
|
d=000004 -- ! sub 100000,100000 -> n0z1v0c0; 000000
|
| 7171 |
|
|
d=000000 -- !
|
| 7172 |
|
|
d=000011 -- ! sub 100001,100000 -> n1z0v0c1; 177777+C
|
| 7173 |
|
|
d=177777 -- !
|
| 7174 |
|
|
d=000002 -- ! sub 000001,100000 -> n0z0v1c0; 077777
|
| 7175 |
|
|
d=077777 -- !
|
| 7176 |
|
|
d=000011 -- ! sub 177777,100000 -> n1z0v0c1: 100001+C
|
| 7177 |
|
|
d=100001 -- !
|
| 7178 |
|
|
d=000010 -- ! sub 000000,177777 -> n1z0v0c0; 177777
|
| 7179 |
|
|
d=177777 -- !
|
| 7180 |
|
|
d=000010 -- ! sub 000001,177777 -> n1z0v0c0; 177776
|
| 7181 |
|
|
d=177776 -- !
|
| 7182 |
|
|
d=000004 -- ! sub 177777,177777 -> n0z1v0c0; 000000
|
| 7183 |
|
|
d=000000 -- !
|
| 7184 |
|
|
#
|
| 7185 |
|
|
C Exec test 46.20r: SWAP - reg
|
| 7186 |
|
|
#
|
| 7187 |
|
|
wal 036000 -- setup test vector: for swap
|
| 7188 |
|
|
bwm 9
|
| 7189 |
|
|
000000 -- swap 000000
|
| 7190 |
|
|
000001 -- swap 000001
|
| 7191 |
|
|
000200 -- swap 000200
|
| 7192 |
|
|
000400 -- swap 000400
|
| 7193 |
|
|
100000 -- swap 100000
|
| 7194 |
|
|
000401 -- swap 000401
|
| 7195 |
|
|
000600 -- swap 000600
|
| 7196 |
|
|
100001 -- swap 100001
|
| 7197 |
|
|
100200 -- swap 100200
|
| 7198 |
|
|
wal 013204 -- setup test instructions:
|
| 7199 |
|
|
bwm 2
|
| 7200 |
|
|
000241 -- ccmov= clc
|
| 7201 |
|
|
000305 -- iut= swap r5
|
| 7202 |
|
|
wr0 177776 -- r0=177776
|
| 7203 |
|
|
wr1 000011 -- r1=11 (9.)
|
| 7204 |
|
|
wr2 036000 -- r2=36000
|
| 7205 |
|
|
wr3 037000 -- r3=37000
|
| 7206 |
|
|
wr4 000000 -- r4=0
|
| 7207 |
|
|
wr5 000000 -- r5=0
|
| 7208 |
|
|
wsp 001400 -- sp=1400
|
| 7209 |
30 |
wfjm |
cres
|
| 7210 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7211 |
|
|
wtgo
|
| 7212 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7213 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7214 |
|
|
wal 037000 -- check result area (Note: N,Z from lsb of result)
|
| 7215 |
|
|
brm 18
|
| 7216 |
|
|
d=000004 -- ! swap 000000 -> n0z1v0c0; 000000
|
| 7217 |
|
|
d=000000 -- !
|
| 7218 |
|
|
d=000004 -- ! swap 000001 -> n0z1v0c0; 000400
|
| 7219 |
|
|
d=000400 -- !
|
| 7220 |
|
|
d=000004 -- ! swap 000200 -> n0z1v0c0; 100000
|
| 7221 |
|
|
d=100000 -- !
|
| 7222 |
|
|
d=000000 -- ! swap 000400 -> n0z0v0c0; 000001
|
| 7223 |
|
|
d=000001 -- !
|
| 7224 |
|
|
d=000010 -- ! swap 100000 -> n1z0v0c0; 000200
|
| 7225 |
|
|
d=000200 -- !
|
| 7226 |
|
|
d=000000 -- ! swap 000401 -> n0z0v0c0; 000401
|
| 7227 |
|
|
d=000401 -- !
|
| 7228 |
|
|
d=000000 -- ! swap 000600 -> n0z0v0c0; 100001
|
| 7229 |
|
|
d=100001 -- !
|
| 7230 |
|
|
d=000010 -- ! swap 100001 -> n1z0v0c0; 000600
|
| 7231 |
|
|
d=000600 -- !
|
| 7232 |
|
|
d=000010 -- ! swap 100200 -> n1z0v0c0; 100200
|
| 7233 |
|
|
d=100200 -- !
|
| 7234 |
|
|
#--------
|
| 7235 |
|
|
C Exec code 46 pass 2 (systematic result+cc test of 1+2op instructions; byte)
|
| 7236 |
|
|
C Exec test 46.1br: COMB - reg
|
| 7237 |
|
|
#
|
| 7238 |
|
|
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst (b)
|
| 7239 |
|
|
bwm 5
|
| 7240 |
|
|
000000 -- comb 000000
|
| 7241 |
|
|
000001 -- comb 000001
|
| 7242 |
|
|
000177 -- comb 000177
|
| 7243 |
|
|
000200 -- comb 000200
|
| 7244 |
|
|
000377 -- comb 000377
|
| 7245 |
|
|
wal 013204 -- setup test instructions:
|
| 7246 |
|
|
bwm 2
|
| 7247 |
|
|
000241 -- ccmov= clc
|
| 7248 |
|
|
105105 -- iut= comb r5
|
| 7249 |
|
|
wr0 177776 -- r0=177776
|
| 7250 |
|
|
wr1 000005 -- r1=5
|
| 7251 |
|
|
wr2 036000 -- r2=36000
|
| 7252 |
|
|
wr3 037000 -- r3=37000
|
| 7253 |
|
|
wr4 000000 -- r4=0
|
| 7254 |
|
|
wr5 000000 -- r5=0
|
| 7255 |
|
|
wsp 001400 -- sp=1400
|
| 7256 |
30 |
wfjm |
cres
|
| 7257 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7258 |
|
|
wtgo
|
| 7259 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7260 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7261 |
|
|
wal 037000 -- check result area
|
| 7262 |
|
|
brm 10
|
| 7263 |
|
|
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
|
| 7264 |
|
|
d=000377 -- !
|
| 7265 |
|
|
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
|
| 7266 |
|
|
d=000376 -- !
|
| 7267 |
|
|
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
|
| 7268 |
|
|
d=000200 -- !
|
| 7269 |
|
|
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
|
| 7270 |
|
|
d=000177 -- !
|
| 7271 |
|
|
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
|
| 7272 |
|
|
d=000000 -- !
|
| 7273 |
|
|
#--------
|
| 7274 |
|
|
C Exec test 46.1bm: COMB - mem
|
| 7275 |
|
|
#
|
| 7276 |
|
|
wal 013224 -- setup test instructions:
|
| 7277 |
|
|
bwm 2
|
| 7278 |
|
|
000241 -- ccmov= clc
|
| 7279 |
|
|
105115 -- iut= comb (r5)
|
| 7280 |
|
|
wr0 177776 -- r0=177776
|
| 7281 |
|
|
wr1 000005 -- r1=5
|
| 7282 |
|
|
wr2 036000 -- r2=36000
|
| 7283 |
|
|
wr3 037000 -- r3=37000
|
| 7284 |
|
|
wr4 001400 -- r4=1400
|
| 7285 |
|
|
wr5 001402 -- r5=1402
|
| 7286 |
|
|
wsp 001400 -- sp=1400
|
| 7287 |
30 |
wfjm |
cres
|
| 7288 |
2 |
wfjm |
stapc 013220 -- start @ 13220 (1op mem)
|
| 7289 |
|
|
wtgo
|
| 7290 |
|
|
rpc d=013240 -- ! pc=halt
|
| 7291 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7292 |
|
|
wal 037000 -- check result area
|
| 7293 |
|
|
brm 10
|
| 7294 |
|
|
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
|
| 7295 |
|
|
d=000377 -- !
|
| 7296 |
|
|
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
|
| 7297 |
|
|
d=000376 -- !
|
| 7298 |
|
|
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
|
| 7299 |
|
|
d=000200 -- !
|
| 7300 |
|
|
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
|
| 7301 |
|
|
d=000177 -- !
|
| 7302 |
|
|
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
|
| 7303 |
|
|
d=000000 -- !
|
| 7304 |
|
|
#--------
|
| 7305 |
|
|
C Exec test 46.2brc0: INCB - reg,C=0
|
| 7306 |
|
|
#
|
| 7307 |
|
|
wal 013204 -- setup test instructions:
|
| 7308 |
|
|
bwm 2
|
| 7309 |
|
|
000241 -- ccmov= clc
|
| 7310 |
|
|
105205 -- iut= incb r5
|
| 7311 |
|
|
wr0 177776 -- r0=177776
|
| 7312 |
|
|
wr1 000005 -- r1=5
|
| 7313 |
|
|
wr2 036000 -- r2=36000
|
| 7314 |
|
|
wr3 037000 -- r3=37000
|
| 7315 |
|
|
wr4 000000 -- r4=0
|
| 7316 |
|
|
wr5 000000 -- r5=0
|
| 7317 |
|
|
wsp 001400 -- sp=1400
|
| 7318 |
30 |
wfjm |
cres
|
| 7319 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7320 |
|
|
wtgo
|
| 7321 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7322 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7323 |
|
|
wal 037000 -- check result area
|
| 7324 |
|
|
brm 10
|
| 7325 |
|
|
d=000000 -- ! incb 000000 -> n0z0v0c0; 000001
|
| 7326 |
|
|
d=000001 -- !
|
| 7327 |
|
|
d=000000 -- ! incb 000001 -> n0z0v0c0; 000002
|
| 7328 |
|
|
d=000002 -- !
|
| 7329 |
|
|
d=000012 -- ! incb 000177 -> n1z0v1c0; 000200
|
| 7330 |
|
|
d=000200 -- !
|
| 7331 |
|
|
d=000010 -- ! incb 000200 -> n1z0v0c0; 000201
|
| 7332 |
|
|
d=000201 -- !
|
| 7333 |
|
|
d=000004 -- ! incb 000377 -> n0z1v0c0; 000000
|
| 7334 |
|
|
d=000000 -- !
|
| 7335 |
|
|
#--------
|
| 7336 |
|
|
C Exec test 46.2brc1: INCB - reg,C=1
|
| 7337 |
|
|
#
|
| 7338 |
|
|
wal 013204 -- setup test instructions:
|
| 7339 |
|
|
bwm 2
|
| 7340 |
|
|
000261 -- ccmov= sec
|
| 7341 |
|
|
105205 -- iut= incb r5
|
| 7342 |
|
|
wr0 177776 -- r0=177776
|
| 7343 |
|
|
wr1 000005 -- r1=5
|
| 7344 |
|
|
wr2 036000 -- r2=36000
|
| 7345 |
|
|
wr3 037000 -- r3=37000
|
| 7346 |
|
|
wr4 000000 -- r4=0
|
| 7347 |
|
|
wr5 000000 -- r5=0
|
| 7348 |
|
|
wsp 001400 -- sp=1400
|
| 7349 |
30 |
wfjm |
cres
|
| 7350 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7351 |
|
|
wtgo
|
| 7352 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7353 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7354 |
|
|
wal 037000 -- check result area
|
| 7355 |
|
|
brm 10
|
| 7356 |
|
|
d=000001 -- ! incb 000000 -> n0z0v0c1; 000001
|
| 7357 |
|
|
d=000001 -- !
|
| 7358 |
|
|
d=000001 -- ! incb 000001 -> n0z0v0c1; 000002
|
| 7359 |
|
|
d=000002 -- !
|
| 7360 |
|
|
d=000013 -- ! incb 000177 -> n1z0v1c1; 000200
|
| 7361 |
|
|
d=000200 -- !
|
| 7362 |
|
|
d=000011 -- ! incb 000200 -> n1z0v0c1; 000201
|
| 7363 |
|
|
d=000201 -- !
|
| 7364 |
|
|
d=000005 -- ! incb 000377 -> n0z1v0c1; 000000
|
| 7365 |
|
|
d=000000 -- !
|
| 7366 |
|
|
#--------
|
| 7367 |
|
|
C Exec test 46.3brc0: DECB - reg,C=0
|
| 7368 |
|
|
#
|
| 7369 |
|
|
wal 013204 -- setup test instructions:
|
| 7370 |
|
|
bwm 2
|
| 7371 |
|
|
000241 -- ccmov= clc
|
| 7372 |
|
|
105305 -- iut= decb r5
|
| 7373 |
|
|
wr0 177776 -- r0=177776
|
| 7374 |
|
|
wr1 000005 -- r1=5
|
| 7375 |
|
|
wr2 036000 -- r2=36000
|
| 7376 |
|
|
wr3 037000 -- r3=37000
|
| 7377 |
|
|
wr4 000000 -- r4=0
|
| 7378 |
|
|
wr5 000000 -- r5=0
|
| 7379 |
|
|
wsp 001400 -- sp=1400
|
| 7380 |
30 |
wfjm |
cres
|
| 7381 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7382 |
|
|
wtgo
|
| 7383 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7384 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7385 |
|
|
wal 037000 -- check result area
|
| 7386 |
|
|
brm 10
|
| 7387 |
|
|
d=000010 -- ! decb 000000 -> n1z0v0c0; 000377
|
| 7388 |
|
|
d=000377 -- !
|
| 7389 |
|
|
d=000004 -- ! decb 000001 -> n0z1v0c0; 000000
|
| 7390 |
|
|
d=000000 -- !
|
| 7391 |
|
|
d=000000 -- ! decb 000177 -> n0z0v0c0; 000176
|
| 7392 |
|
|
d=000176 -- !
|
| 7393 |
|
|
d=000002 -- ! decb 000200 -> n0z0v1c0; 000177
|
| 7394 |
|
|
d=000177 -- !
|
| 7395 |
|
|
d=000010 -- ! decb 000377 -> n1z0v0c0; 000376
|
| 7396 |
|
|
d=000376 -- !
|
| 7397 |
|
|
#--------
|
| 7398 |
|
|
C Exec test 46.3brc1: DECB - reg,C=1
|
| 7399 |
|
|
#
|
| 7400 |
|
|
wal 013204 -- setup test instructions:
|
| 7401 |
|
|
bwm 2
|
| 7402 |
|
|
000261 -- ccmov= sec
|
| 7403 |
|
|
105305 -- iut= decb r5
|
| 7404 |
|
|
wr0 177776 -- r0=177776
|
| 7405 |
|
|
wr1 000005 -- r1=5
|
| 7406 |
|
|
wr2 036000 -- r2=36000
|
| 7407 |
|
|
wr3 037000 -- r3=37000
|
| 7408 |
|
|
wr4 000000 -- r4=0
|
| 7409 |
|
|
wr5 000000 -- r5=0
|
| 7410 |
|
|
wsp 001400 -- sp=1400
|
| 7411 |
30 |
wfjm |
cres
|
| 7412 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7413 |
|
|
wtgo
|
| 7414 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7415 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7416 |
|
|
wal 037000 -- check result area
|
| 7417 |
|
|
brm 10
|
| 7418 |
|
|
d=000011 -- ! decb 000000 -> n1z0v0c1; 000377
|
| 7419 |
|
|
d=000377 -- !
|
| 7420 |
|
|
d=000005 -- ! decb 000001 -> n0z1v0c1; 000000
|
| 7421 |
|
|
d=000000 -- !
|
| 7422 |
|
|
d=000001 -- ! decb 000177 -> n0z0v0c1; 000176
|
| 7423 |
|
|
d=000176 -- !
|
| 7424 |
|
|
d=000003 -- ! decb 000200 -> n0z0v1c1; 000177
|
| 7425 |
|
|
d=000177 -- !
|
| 7426 |
|
|
d=000011 -- ! decb 000377 -> n1z0v0c1; 000376
|
| 7427 |
|
|
d=000376 -- !
|
| 7428 |
|
|
#--------
|
| 7429 |
|
|
C Exec test 46.4br: NEGB - reg
|
| 7430 |
|
|
#
|
| 7431 |
|
|
wal 013204 -- setup test instructions:
|
| 7432 |
|
|
bwm 2
|
| 7433 |
|
|
000241 -- ccmov= clc
|
| 7434 |
|
|
105405 -- iut= negb r5
|
| 7435 |
|
|
wr0 177776 -- r0=177776
|
| 7436 |
|
|
wr1 000005 -- r1=5
|
| 7437 |
|
|
wr2 036000 -- r2=36000
|
| 7438 |
|
|
wr3 037000 -- r3=37000
|
| 7439 |
|
|
wr4 000000 -- r4=0
|
| 7440 |
|
|
wr5 000000 -- r5=0
|
| 7441 |
|
|
wsp 001400 -- sp=1400
|
| 7442 |
30 |
wfjm |
cres
|
| 7443 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7444 |
|
|
wtgo
|
| 7445 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7446 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7447 |
|
|
wal 037000 -- check result area
|
| 7448 |
|
|
brm 10
|
| 7449 |
|
|
d=000004 -- ! negb 000000 -> n0z1v0c0; 000000
|
| 7450 |
|
|
d=000000 -- !
|
| 7451 |
|
|
d=000011 -- ! negb 000001 -> n1z0v0c1; 000377
|
| 7452 |
|
|
d=000377 -- !
|
| 7453 |
|
|
d=000011 -- ! negb 000177 -> n1z0v0c1; 000201
|
| 7454 |
|
|
d=000201 -- !
|
| 7455 |
|
|
d=000013 -- ! negb 000200 -> n1z0v1c1; 000200
|
| 7456 |
|
|
d=000200 -- !
|
| 7457 |
|
|
d=000001 -- ! negb 000377 -> n0z0v0c1; 000001
|
| 7458 |
|
|
d=000001 -- !
|
| 7459 |
|
|
#--------
|
| 7460 |
|
|
C Exec test 46.5brc0: ADCB - reg,C=0
|
| 7461 |
|
|
#
|
| 7462 |
|
|
wal 013204 -- setup test instructions:
|
| 7463 |
|
|
bwm 2
|
| 7464 |
|
|
000241 -- ccmov= clc
|
| 7465 |
|
|
105505 -- iut= adcb r5
|
| 7466 |
|
|
wr0 177776 -- r0=177776
|
| 7467 |
|
|
wr1 000005 -- r1=5
|
| 7468 |
|
|
wr2 036000 -- r2=36000
|
| 7469 |
|
|
wr3 037000 -- r3=37000
|
| 7470 |
|
|
wr4 000000 -- r4=0
|
| 7471 |
|
|
wr5 000000 -- r5=0
|
| 7472 |
|
|
wsp 001400 -- sp=1400
|
| 7473 |
30 |
wfjm |
cres
|
| 7474 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7475 |
|
|
wtgo
|
| 7476 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7477 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7478 |
|
|
wal 037000 -- check result area
|
| 7479 |
|
|
brm 10
|
| 7480 |
|
|
d=000004 -- ! adcb 000000 -> n0z1v0c0; 000000
|
| 7481 |
|
|
d=000000 -- !
|
| 7482 |
|
|
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000001
|
| 7483 |
|
|
d=000001 -- !
|
| 7484 |
|
|
d=000000 -- ! adcb 000177 -> n0z0v0c0; 000177
|
| 7485 |
|
|
d=000177 -- !
|
| 7486 |
|
|
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000200
|
| 7487 |
|
|
d=000200 -- !
|
| 7488 |
|
|
d=000010 -- ! adcb 000377 -> n1z0v0c0; 000377
|
| 7489 |
|
|
d=000377 -- !
|
| 7490 |
|
|
#--------
|
| 7491 |
|
|
C Exec test 46.5brc1: ADCB - reg,C=1
|
| 7492 |
|
|
#
|
| 7493 |
|
|
wal 013204 -- setup test instructions:
|
| 7494 |
|
|
bwm 2
|
| 7495 |
|
|
000261 -- ccmov= sec
|
| 7496 |
|
|
105505 -- iut= adcb r5
|
| 7497 |
|
|
wr0 177776 -- r0=177776
|
| 7498 |
|
|
wr1 000005 -- r1=5
|
| 7499 |
|
|
wr2 036000 -- r2=36000
|
| 7500 |
|
|
wr3 037000 -- r3=37000
|
| 7501 |
|
|
wr4 000000 -- r4=0
|
| 7502 |
|
|
wr5 000000 -- r5=0
|
| 7503 |
|
|
wsp 001400 -- sp=1400
|
| 7504 |
30 |
wfjm |
cres
|
| 7505 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7506 |
|
|
wtgo
|
| 7507 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7508 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7509 |
|
|
wal 037000 -- check result area
|
| 7510 |
|
|
brm 10
|
| 7511 |
|
|
d=000000 -- ! adcb 000000 -> n0z0v0c0; 000001
|
| 7512 |
|
|
d=000001 -- !
|
| 7513 |
|
|
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000002
|
| 7514 |
|
|
d=000002 -- !
|
| 7515 |
|
|
d=000012 -- ! adcb 000177 -> n1z0v1c0; 000200
|
| 7516 |
|
|
d=000200 -- !
|
| 7517 |
|
|
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000201
|
| 7518 |
|
|
d=000201 -- !
|
| 7519 |
|
|
d=000005 -- ! adcb 000377 -> n0z1v0c1; 000000
|
| 7520 |
|
|
d=000000 -- !
|
| 7521 |
|
|
#--------
|
| 7522 |
|
|
C Exec test 46.6brc0: SBCB - reg,C=0
|
| 7523 |
|
|
#
|
| 7524 |
|
|
wal 013204 -- setup test instructions:
|
| 7525 |
|
|
bwm 2
|
| 7526 |
|
|
000241 -- ccmov= clc
|
| 7527 |
|
|
105605 -- iut= sbcb r5
|
| 7528 |
|
|
wr0 177776 -- r0=177776
|
| 7529 |
|
|
wr1 000005 -- r1=5
|
| 7530 |
|
|
wr2 036000 -- r2=36000
|
| 7531 |
|
|
wr3 037000 -- r3=37000
|
| 7532 |
|
|
wr4 000000 -- r4=0
|
| 7533 |
|
|
wr5 000000 -- r5=0
|
| 7534 |
|
|
wsp 001400 -- sp=1400
|
| 7535 |
30 |
wfjm |
cres
|
| 7536 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7537 |
|
|
wtgo
|
| 7538 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7539 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7540 |
|
|
wal 037000 -- check result area
|
| 7541 |
|
|
brm 10
|
| 7542 |
|
|
d=000004 -- ! sbcb 000000 -> n0z1v0c0; 000000
|
| 7543 |
|
|
d=000000 -- !
|
| 7544 |
|
|
d=000000 -- ! sbcb 000001 -> n0z0v0c0; 000001
|
| 7545 |
|
|
d=000001 -- !
|
| 7546 |
|
|
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000177
|
| 7547 |
|
|
d=000177 -- !
|
| 7548 |
|
|
d=000010 -- ! sbcb 000200 -> n1z0v0c0; 000200
|
| 7549 |
|
|
d=000200 -- !
|
| 7550 |
|
|
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000377
|
| 7551 |
|
|
d=000377 -- !
|
| 7552 |
|
|
#--------
|
| 7553 |
|
|
C Exec test 46.6brc1: SBCB - reg,C=1
|
| 7554 |
|
|
#
|
| 7555 |
|
|
wal 013204 -- setup test instructions:
|
| 7556 |
|
|
bwm 2
|
| 7557 |
|
|
000261 -- ccmov= sec
|
| 7558 |
|
|
105605 -- iut= sbcb r5
|
| 7559 |
|
|
wr0 177776 -- r0=177776
|
| 7560 |
|
|
wr1 000005 -- r1=5
|
| 7561 |
|
|
wr2 036000 -- r2=36000
|
| 7562 |
|
|
wr3 037000 -- r3=37000
|
| 7563 |
|
|
wr4 000000 -- r4=0
|
| 7564 |
|
|
wr5 000000 -- r5=0
|
| 7565 |
|
|
wsp 001400 -- sp=1400
|
| 7566 |
30 |
wfjm |
cres
|
| 7567 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7568 |
|
|
wtgo
|
| 7569 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7570 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7571 |
|
|
wal 037000 -- check result area
|
| 7572 |
|
|
brm 10
|
| 7573 |
|
|
d=000011 -- ! sbcb 000000 -> n1z0v0c1; 000377
|
| 7574 |
|
|
d=000377 -- !
|
| 7575 |
|
|
d=000004 -- ! sbcb 000001 -> n0z1v0c0; 000000
|
| 7576 |
|
|
d=000000 -- !
|
| 7577 |
|
|
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000176
|
| 7578 |
|
|
d=000176 -- !
|
| 7579 |
|
|
d=000002 -- ! sbcb 000200 -> n0z0v1c0; 000177
|
| 7580 |
|
|
d=000177 -- !
|
| 7581 |
|
|
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000376
|
| 7582 |
|
|
d=000376 -- !
|
| 7583 |
|
|
#--------
|
| 7584 |
|
|
C Exec test 46.7br: TSTB - reg
|
| 7585 |
|
|
#
|
| 7586 |
|
|
wal 013204 -- setup test instructions:
|
| 7587 |
|
|
bwm 2
|
| 7588 |
|
|
000261 -- ccmov= sec
|
| 7589 |
|
|
105705 -- iut= tstb r5
|
| 7590 |
|
|
wr0 177776 -- r0=177776
|
| 7591 |
|
|
wr1 000005 -- r1=5
|
| 7592 |
|
|
wr2 036000 -- r2=36000
|
| 7593 |
|
|
wr3 037000 -- r3=37000
|
| 7594 |
|
|
wr4 000000 -- r4=0
|
| 7595 |
|
|
wr5 000000 -- r5=0
|
| 7596 |
|
|
wsp 001400 -- sp=1400
|
| 7597 |
30 |
wfjm |
cres
|
| 7598 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7599 |
|
|
wtgo
|
| 7600 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7601 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7602 |
|
|
wal 037000 -- check result area
|
| 7603 |
|
|
brm 10
|
| 7604 |
|
|
d=000004 -- ! tstb 000000 -> n0z1v0c0;
|
| 7605 |
|
|
d=000000 -- !
|
| 7606 |
|
|
d=000000 -- ! tstb 000001 -> n0z0v0c0;
|
| 7607 |
|
|
d=000001 -- !
|
| 7608 |
|
|
d=000000 -- ! tstb 000177 -> n0z0v0c0;
|
| 7609 |
|
|
d=000177 -- !
|
| 7610 |
|
|
d=000010 -- ! tstb 000200 -> n1z0v0c0;
|
| 7611 |
|
|
d=000200 -- !
|
| 7612 |
|
|
d=000010 -- ! tstb 000377 -> n1z0v0c0;
|
| 7613 |
|
|
d=000377 -- !
|
| 7614 |
|
|
#--------
|
| 7615 |
|
|
C Exec test 46.7bm: TSTB - mem
|
| 7616 |
|
|
#
|
| 7617 |
|
|
wal 013224 -- setup test instructions:
|
| 7618 |
|
|
bwm 2
|
| 7619 |
|
|
000261 -- ccmov= sec
|
| 7620 |
|
|
105715 -- iut= tstb (r5)
|
| 7621 |
|
|
wr0 177776 -- r0=177776
|
| 7622 |
|
|
wr1 000005 -- r1=5
|
| 7623 |
|
|
wr2 036000 -- r2=36000
|
| 7624 |
|
|
wr3 037000 -- r3=37000
|
| 7625 |
|
|
wr4 001400 -- r4=1400
|
| 7626 |
|
|
wr5 001402 -- r5=1402
|
| 7627 |
|
|
wsp 001400 -- sp=1400
|
| 7628 |
30 |
wfjm |
cres
|
| 7629 |
2 |
wfjm |
stapc 013220 -- start @ 13220 (1op mem)
|
| 7630 |
|
|
wtgo
|
| 7631 |
|
|
rpc d=013240 -- ! pc=halt
|
| 7632 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7633 |
|
|
wal 037000 -- check result area
|
| 7634 |
|
|
brm 10
|
| 7635 |
|
|
d=000004 -- ! tstb 000000 -> n0z1v0c0;
|
| 7636 |
|
|
d=000000 -- !
|
| 7637 |
|
|
d=000000 -- ! tstb 000001 -> n0z0v0c0;
|
| 7638 |
|
|
d=000001 -- !
|
| 7639 |
|
|
d=000000 -- ! tstb 000177 -> n0z0v0c0;
|
| 7640 |
|
|
d=000177 -- !
|
| 7641 |
|
|
d=000010 -- ! tstb 000200 -> n1z0v0c0;
|
| 7642 |
|
|
d=000200 -- !
|
| 7643 |
|
|
d=000010 -- ! tstb 000377 -> n1z0v0c0;
|
| 7644 |
|
|
d=000377 -- !
|
| 7645 |
|
|
#--------
|
| 7646 |
|
|
C Exec test 46.8brc0: RORB - reg, C=0
|
| 7647 |
|
|
#
|
| 7648 |
|
|
wal 036000 -- setup test vector: for ror,rol,ars,asl (b)
|
| 7649 |
|
|
bwm 7
|
| 7650 |
|
|
000000 -- ror 000000
|
| 7651 |
|
|
000001 -- ror 000001
|
| 7652 |
|
|
000200 -- ror 000200
|
| 7653 |
|
|
000010 -- ror 000010
|
| 7654 |
|
|
000011 -- ror 000011
|
| 7655 |
|
|
000110 -- ror 000110
|
| 7656 |
|
|
000210 -- ror 000210
|
| 7657 |
|
|
wal 013204 -- setup test instructions:
|
| 7658 |
|
|
bwm 2
|
| 7659 |
|
|
000241 -- ccmov= clc
|
| 7660 |
|
|
106005 -- iut= rorb r5
|
| 7661 |
|
|
wr0 177776 -- r0=177776
|
| 7662 |
|
|
wr1 000007 -- r1=7
|
| 7663 |
|
|
wr2 036000 -- r2=36000
|
| 7664 |
|
|
wr3 037000 -- r3=37000
|
| 7665 |
|
|
wr4 000000 -- r4=0
|
| 7666 |
|
|
wr5 000000 -- r5=0
|
| 7667 |
|
|
wsp 001400 -- sp=1400
|
| 7668 |
30 |
wfjm |
cres
|
| 7669 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7670 |
|
|
wtgo
|
| 7671 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7672 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7673 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7674 |
|
|
brm 14
|
| 7675 |
|
|
d=000004 -- ! rorb 000000 -> n0z1v0c0; 000000
|
| 7676 |
|
|
d=000000 -- !
|
| 7677 |
|
|
d=000007 -- ! rorb 000001 -> n0z1v1c1; 000000
|
| 7678 |
|
|
d=000000 -- !
|
| 7679 |
|
|
d=000000 -- ! rorb 000200 -> n0z0v0c0; 000100
|
| 7680 |
|
|
d=000100 -- !
|
| 7681 |
|
|
d=000000 -- ! rorb 000010 -> n0z0v0c0; 000004
|
| 7682 |
|
|
d=000004 -- !
|
| 7683 |
|
|
d=000003 -- ! rorb 000011 -> n0z0v1c1; 000004
|
| 7684 |
|
|
d=000004 -- !
|
| 7685 |
|
|
d=000000 -- ! rorb 000110 -> n0z0v0c0; 000044
|
| 7686 |
|
|
d=000044 -- !
|
| 7687 |
|
|
d=000000 -- ! rorb 000210 -> n0z0v0c0; 000104
|
| 7688 |
|
|
d=000104 -- !
|
| 7689 |
|
|
#--------
|
| 7690 |
|
|
C Exec test 46.8brc1: RORB - reg, C=1
|
| 7691 |
|
|
#
|
| 7692 |
|
|
wal 013204 -- setup test instructions:
|
| 7693 |
|
|
bwm 2
|
| 7694 |
|
|
000261 -- ccmov= sec
|
| 7695 |
|
|
106005 -- iut= rorb r5
|
| 7696 |
|
|
wr0 177776 -- r0=177776
|
| 7697 |
|
|
wr1 000007 -- r1=7
|
| 7698 |
|
|
wr2 036000 -- r2=36000
|
| 7699 |
|
|
wr3 037000 -- r3=37000
|
| 7700 |
|
|
wr4 000000 -- r4=0
|
| 7701 |
|
|
wr5 000000 -- r5=0
|
| 7702 |
|
|
wsp 001400 -- sp=1400
|
| 7703 |
30 |
wfjm |
cres
|
| 7704 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7705 |
|
|
wtgo
|
| 7706 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7707 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7708 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7709 |
|
|
brm 14
|
| 7710 |
|
|
d=000012 -- ! rorb 000000 -> n1z0v1c0; 000200
|
| 7711 |
|
|
d=000200 -- !
|
| 7712 |
|
|
d=000011 -- ! rorb 000001 -> n1z0v0c1; 000200
|
| 7713 |
|
|
d=000200 -- !
|
| 7714 |
|
|
d=000012 -- ! rorb 000200 -> n1z0v1c0; 000300
|
| 7715 |
|
|
d=000300 -- !
|
| 7716 |
|
|
d=000012 -- ! rorb 000010 -> n1z0v1c0; 000204
|
| 7717 |
|
|
d=000204 -- !
|
| 7718 |
|
|
d=000011 -- ! rorb 000011 -> n1z0v0c1; 000204
|
| 7719 |
|
|
d=000204 -- !
|
| 7720 |
|
|
d=000012 -- ! rorb 000110 -> n1z0v1c0; 000244
|
| 7721 |
|
|
d=000244 -- !
|
| 7722 |
|
|
d=000012 -- ! rorb 000210 -> n1z0v1c0; 000304
|
| 7723 |
|
|
d=000304 -- !
|
| 7724 |
|
|
#--------
|
| 7725 |
|
|
C Exec test 46.9brc0: ROLB - reg, C=0
|
| 7726 |
|
|
#
|
| 7727 |
|
|
wal 013204 -- setup test instructions:
|
| 7728 |
|
|
bwm 2
|
| 7729 |
|
|
000241 -- ccmov= clc
|
| 7730 |
|
|
106105 -- iut= rolb r5
|
| 7731 |
|
|
wr0 177776 -- r0=177776
|
| 7732 |
|
|
wr1 000007 -- r1=7
|
| 7733 |
|
|
wr2 036000 -- r2=36000
|
| 7734 |
|
|
wr3 037000 -- r3=37000
|
| 7735 |
|
|
wr4 000000 -- r4=0
|
| 7736 |
|
|
wr5 000000 -- r5=0
|
| 7737 |
|
|
wsp 001400 -- sp=1400
|
| 7738 |
30 |
wfjm |
cres
|
| 7739 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7740 |
|
|
wtgo
|
| 7741 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7742 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7743 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7744 |
|
|
brm 14
|
| 7745 |
|
|
d=000004 -- ! rolb 000000 -> n0z1v0c0; 000000
|
| 7746 |
|
|
d=000000 -- !
|
| 7747 |
|
|
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000002
|
| 7748 |
|
|
d=000002 -- !
|
| 7749 |
|
|
d=000007 -- ! rolb 000200 -> n0z1v1c1; 000000
|
| 7750 |
|
|
d=000000 -- !
|
| 7751 |
|
|
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000020
|
| 7752 |
|
|
d=000020 -- !
|
| 7753 |
|
|
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000022
|
| 7754 |
|
|
d=000022 -- !
|
| 7755 |
|
|
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000220
|
| 7756 |
|
|
d=000220 -- !
|
| 7757 |
|
|
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000020
|
| 7758 |
|
|
d=000020 -- !
|
| 7759 |
|
|
#--------
|
| 7760 |
|
|
C Exec test 46.9brc1: ROLB - reg, C=1
|
| 7761 |
|
|
#
|
| 7762 |
|
|
wal 013204 -- setup test instructions:
|
| 7763 |
|
|
bwm 2
|
| 7764 |
|
|
000261 -- ccmov= sec
|
| 7765 |
|
|
106105 -- iut= rolb r5
|
| 7766 |
|
|
wr0 177776 -- r0=177776
|
| 7767 |
|
|
wr1 000007 -- r1=7
|
| 7768 |
|
|
wr2 036000 -- r2=36000
|
| 7769 |
|
|
wr3 037000 -- r3=37000
|
| 7770 |
|
|
wr4 000000 -- r4=0
|
| 7771 |
|
|
wr5 000000 -- r5=0
|
| 7772 |
|
|
wsp 001400 -- sp=1400
|
| 7773 |
30 |
wfjm |
cres
|
| 7774 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7775 |
|
|
wtgo
|
| 7776 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7777 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7778 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7779 |
|
|
brm 14
|
| 7780 |
|
|
d=000000 -- ! rolb 000000 -> n0z0v0c0; 000001
|
| 7781 |
|
|
d=000001 -- !
|
| 7782 |
|
|
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000003
|
| 7783 |
|
|
d=000003 -- !
|
| 7784 |
|
|
d=000003 -- ! rolb 000200 -> n0z0v1c1; 000001
|
| 7785 |
|
|
d=000001 -- !
|
| 7786 |
|
|
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000021
|
| 7787 |
|
|
d=000021 -- !
|
| 7788 |
|
|
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000023
|
| 7789 |
|
|
d=000023 -- !
|
| 7790 |
|
|
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000221
|
| 7791 |
|
|
d=000221 -- !
|
| 7792 |
|
|
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000021
|
| 7793 |
|
|
d=000021 -- !
|
| 7794 |
|
|
#--------
|
| 7795 |
|
|
C Exec test 46.10brc0: ASRB - reg, C=0
|
| 7796 |
|
|
#
|
| 7797 |
|
|
wal 013204 -- setup test instructions:
|
| 7798 |
|
|
bwm 2
|
| 7799 |
|
|
000241 -- ccmov= clc
|
| 7800 |
|
|
106205 -- iut= asrb r5
|
| 7801 |
|
|
wr0 177776 -- r0=177776
|
| 7802 |
|
|
wr1 000007 -- r1=7
|
| 7803 |
|
|
wr2 036000 -- r2=36000
|
| 7804 |
|
|
wr3 037000 -- r3=37000
|
| 7805 |
|
|
wr4 000000 -- r4=0
|
| 7806 |
|
|
wr5 000000 -- r5=0
|
| 7807 |
|
|
wsp 001400 -- sp=1400
|
| 7808 |
30 |
wfjm |
cres
|
| 7809 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7810 |
|
|
wtgo
|
| 7811 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7812 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7813 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7814 |
|
|
brm 14
|
| 7815 |
|
|
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
|
| 7816 |
|
|
d=000000 -- !
|
| 7817 |
|
|
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
|
| 7818 |
|
|
d=000000 -- !
|
| 7819 |
|
|
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
|
| 7820 |
|
|
d=000300 -- !
|
| 7821 |
|
|
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
|
| 7822 |
|
|
d=000004 -- !
|
| 7823 |
|
|
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
|
| 7824 |
|
|
d=000004 -- !
|
| 7825 |
|
|
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
|
| 7826 |
|
|
d=000044 -- !
|
| 7827 |
|
|
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
|
| 7828 |
|
|
d=000304 -- !
|
| 7829 |
|
|
#--------
|
| 7830 |
|
|
C Exec test 46.10brc1: ASRB - reg, C=1
|
| 7831 |
|
|
#
|
| 7832 |
|
|
wal 013204 -- setup test instructions:
|
| 7833 |
|
|
bwm 2
|
| 7834 |
|
|
000261 -- ccmov= sec
|
| 7835 |
|
|
106205 -- iut= asrb r5
|
| 7836 |
|
|
wr0 177776 -- r0=177776
|
| 7837 |
|
|
wr1 000007 -- r1=7
|
| 7838 |
|
|
wr2 036000 -- r2=36000
|
| 7839 |
|
|
wr3 037000 -- r3=37000
|
| 7840 |
|
|
wr4 000000 -- r4=0
|
| 7841 |
|
|
wr5 000000 -- r5=0
|
| 7842 |
|
|
wsp 001400 -- sp=1400
|
| 7843 |
30 |
wfjm |
cres
|
| 7844 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7845 |
|
|
wtgo
|
| 7846 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7847 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7848 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7849 |
|
|
brm 14
|
| 7850 |
|
|
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
|
| 7851 |
|
|
d=000000 -- !
|
| 7852 |
|
|
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
|
| 7853 |
|
|
d=000000 -- !
|
| 7854 |
|
|
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
|
| 7855 |
|
|
d=000300 -- !
|
| 7856 |
|
|
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
|
| 7857 |
|
|
d=000004 -- !
|
| 7858 |
|
|
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
|
| 7859 |
|
|
d=000004 -- !
|
| 7860 |
|
|
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
|
| 7861 |
|
|
d=000044 -- !
|
| 7862 |
|
|
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
|
| 7863 |
|
|
d=000304 -- !
|
| 7864 |
|
|
#--------
|
| 7865 |
|
|
C Exec test 46.11brc0: ASLB - reg, C=0
|
| 7866 |
|
|
#
|
| 7867 |
|
|
wal 013204 -- setup test instructions:
|
| 7868 |
|
|
bwm 2
|
| 7869 |
|
|
000241 -- ccmov= clc
|
| 7870 |
|
|
106305 -- iut= aslb r5
|
| 7871 |
|
|
wr0 177776 -- r0=177776
|
| 7872 |
|
|
wr1 000007 -- r1=7
|
| 7873 |
|
|
wr2 036000 -- r2=36000
|
| 7874 |
|
|
wr3 037000 -- r3=37000
|
| 7875 |
|
|
wr4 000000 -- r4=0
|
| 7876 |
|
|
wr5 000000 -- r5=0
|
| 7877 |
|
|
wsp 001400 -- sp=1400
|
| 7878 |
30 |
wfjm |
cres
|
| 7879 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7880 |
|
|
wtgo
|
| 7881 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7882 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7883 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7884 |
|
|
brm 14
|
| 7885 |
|
|
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
|
| 7886 |
|
|
d=000000 -- !
|
| 7887 |
|
|
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
|
| 7888 |
|
|
d=000002 -- !
|
| 7889 |
|
|
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
|
| 7890 |
|
|
d=000000 -- !
|
| 7891 |
|
|
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
|
| 7892 |
|
|
d=000020 -- !
|
| 7893 |
|
|
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
|
| 7894 |
|
|
d=000022 -- !
|
| 7895 |
|
|
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
|
| 7896 |
|
|
d=000220 -- !
|
| 7897 |
|
|
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
|
| 7898 |
|
|
d=000020 -- !
|
| 7899 |
|
|
#--------
|
| 7900 |
|
|
C Exec test 46.11brc1: ASLB - reg, C=1
|
| 7901 |
|
|
#
|
| 7902 |
|
|
wal 013204 -- setup test instructions:
|
| 7903 |
|
|
bwm 2
|
| 7904 |
|
|
000261 -- ccmov= sec
|
| 7905 |
|
|
106305 -- iut= aslb r5
|
| 7906 |
|
|
wr0 177776 -- r0=177776
|
| 7907 |
|
|
wr1 000007 -- r1=7
|
| 7908 |
|
|
wr2 036000 -- r2=36000
|
| 7909 |
|
|
wr3 037000 -- r3=37000
|
| 7910 |
|
|
wr4 000000 -- r4=0
|
| 7911 |
|
|
wr5 000000 -- r5=0
|
| 7912 |
|
|
wsp 001400 -- sp=1400
|
| 7913 |
30 |
wfjm |
cres
|
| 7914 |
2 |
wfjm |
stapc 013200 -- start @ 13200 (1op reg)
|
| 7915 |
|
|
wtgo
|
| 7916 |
|
|
rpc d=013220 -- ! pc=halt
|
| 7917 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7918 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
| 7919 |
|
|
brm 14
|
| 7920 |
|
|
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
|
| 7921 |
|
|
d=000000 -- !
|
| 7922 |
|
|
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
|
| 7923 |
|
|
d=000002 -- !
|
| 7924 |
|
|
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
|
| 7925 |
|
|
d=000000 -- !
|
| 7926 |
|
|
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
|
| 7927 |
|
|
d=000020 -- !
|
| 7928 |
|
|
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
|
| 7929 |
|
|
d=000022 -- !
|
| 7930 |
|
|
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
|
| 7931 |
|
|
d=000220 -- !
|
| 7932 |
|
|
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
|
| 7933 |
|
|
d=000020 -- !
|
| 7934 |
|
|
#--------
|
| 7935 |
|
|
C Exec test 46.12brc0: MOVB - reg, C=0
|
| 7936 |
|
|
#
|
| 7937 |
|
|
wal 036000 -- setup test vector: for mov
|
| 7938 |
|
|
bwm 6
|
| 7939 |
|
|
000000 -- movb 000000,000000
|
| 7940 |
|
|
000000 --
|
| 7941 |
|
|
000001 -- movb 000001,000000
|
| 7942 |
|
|
000000 --
|
| 7943 |
|
|
000200 -- movb 000200,000000
|
| 7944 |
|
|
000000 --
|
| 7945 |
|
|
wal 013246 -- setup test instructions:
|
| 7946 |
|
|
bwm 2
|
| 7947 |
|
|
000241 -- ccmov= clc
|
| 7948 |
|
|
110405 -- iut= movb r4,r5
|
| 7949 |
|
|
wr0 177776 -- r0=177776
|
| 7950 |
|
|
wr1 000003 -- r1=3
|
| 7951 |
|
|
wr2 036000 -- r2=36000
|
| 7952 |
|
|
wr3 037000 -- r3=37000
|
| 7953 |
|
|
wr4 000000 -- r4=0
|
| 7954 |
|
|
wr5 000000 -- r5=0
|
| 7955 |
|
|
wsp 001400 -- sp=1400
|
| 7956 |
30 |
wfjm |
cres
|
| 7957 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 7958 |
|
|
wtgo
|
| 7959 |
|
|
rpc d=013262 -- ! pc=halt
|
| 7960 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7961 |
|
|
wal 037000 -- check result area
|
| 7962 |
|
|
brm 6
|
| 7963 |
|
|
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
|
| 7964 |
|
|
d=000000 -- !
|
| 7965 |
|
|
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
|
| 7966 |
|
|
d=000001 -- !
|
| 7967 |
|
|
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 177600
|
| 7968 |
|
|
d=177600 -- !
|
| 7969 |
|
|
#--------
|
| 7970 |
|
|
C Exec test 46.12brc1: MOVB - reg, C=1
|
| 7971 |
|
|
#
|
| 7972 |
|
|
wal 013246 -- setup test instructions:
|
| 7973 |
|
|
bwm 2
|
| 7974 |
|
|
000261 -- ccmov= sec
|
| 7975 |
|
|
110405 -- iut= movb r4,r5
|
| 7976 |
|
|
wr0 177776 -- r0=177776
|
| 7977 |
|
|
wr1 000003 -- r1=3
|
| 7978 |
|
|
wr2 036000 -- r2=36000
|
| 7979 |
|
|
wr3 037000 -- r3=37000
|
| 7980 |
|
|
wr4 000000 -- r4=0
|
| 7981 |
|
|
wr5 000000 -- r5=0
|
| 7982 |
|
|
wsp 001400 -- sp=1400
|
| 7983 |
30 |
wfjm |
cres
|
| 7984 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 7985 |
|
|
wtgo
|
| 7986 |
|
|
rpc d=013262 -- ! pc=halt
|
| 7987 |
|
|
rr1 d=000000 -- ! r1=0
|
| 7988 |
|
|
wal 037000 -- check result area
|
| 7989 |
|
|
brm 6
|
| 7990 |
|
|
d=000005 -- ! movb 000000,000000 -> n0z1v0c1; 000000
|
| 7991 |
|
|
d=000000 -- !
|
| 7992 |
|
|
d=000001 -- ! movb 000001,000000 -> n0z0v0c1; 000001
|
| 7993 |
|
|
d=000001 -- !
|
| 7994 |
|
|
d=000011 -- ! movb 000200,000000 -> n1z0v0c1; 177600
|
| 7995 |
|
|
d=177600 -- !
|
| 7996 |
|
|
#--------
|
| 7997 |
|
|
C Exec test 46.12bmc0: MOVB - mem, C=0
|
| 7998 |
|
|
#
|
| 7999 |
|
|
wal 013276 -- setup test instructions:
|
| 8000 |
|
|
bwm 2
|
| 8001 |
|
|
000241 -- ccmov= clc
|
| 8002 |
|
|
111415 -- iut= movb (r4),(r5)
|
| 8003 |
|
|
wr0 177776 -- r0=177776
|
| 8004 |
|
|
wr1 000003 -- r1=3
|
| 8005 |
|
|
wr2 036000 -- r2=36000
|
| 8006 |
|
|
wr3 037000 -- r3=37000
|
| 8007 |
|
|
wr4 001400 -- r4=1400
|
| 8008 |
|
|
wr5 001402 -- r5=1402
|
| 8009 |
|
|
wsp 001400 -- sp=1400
|
| 8010 |
30 |
wfjm |
cres
|
| 8011 |
2 |
wfjm |
stapc 013270 -- start @ 13270 (2op mem)
|
| 8012 |
|
|
wtgo
|
| 8013 |
|
|
rpc d=013312 -- ! pc=halt
|
| 8014 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8015 |
|
|
wal 037000 -- check result area
|
| 8016 |
|
|
brm 6
|
| 8017 |
|
|
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
|
| 8018 |
|
|
d=000000 -- !
|
| 8019 |
|
|
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
|
| 8020 |
|
|
d=000001 -- !
|
| 8021 |
|
|
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 000200
|
| 8022 |
|
|
d=000200 -- !
|
| 8023 |
|
|
#--------
|
| 8024 |
|
|
C Exec test 46.13brc0: BITB - reg, C=0
|
| 8025 |
|
|
#
|
| 8026 |
|
|
wal 036000 -- setup test vector: for bit,bic,bis (b)
|
| 8027 |
|
|
bwm 12
|
| 8028 |
|
|
000000 -- bitb 000000,000000
|
| 8029 |
|
|
000000 --
|
| 8030 |
|
|
000003 -- bitb 000003,000000
|
| 8031 |
|
|
000000 --
|
| 8032 |
|
|
000003 -- bitb 000003,000006
|
| 8033 |
|
|
000006 --
|
| 8034 |
|
|
000003 -- bitb 000003,000014
|
| 8035 |
|
|
000014 --
|
| 8036 |
|
|
000300 -- bitb 000300,000140
|
| 8037 |
|
|
000140 --
|
| 8038 |
|
|
000300 -- bitb 000300,000300
|
| 8039 |
|
|
000300 --
|
| 8040 |
|
|
wal 013246 -- setup test instructions:
|
| 8041 |
|
|
bwm 2
|
| 8042 |
|
|
000241 -- ccmov= clc
|
| 8043 |
|
|
130405 -- iut= bitb r4,r5
|
| 8044 |
|
|
wr0 177776 -- r0=177776
|
| 8045 |
|
|
wr1 000006 -- r1=6
|
| 8046 |
|
|
wr2 036000 -- r2=36000
|
| 8047 |
|
|
wr3 037000 -- r3=37000
|
| 8048 |
|
|
wr4 000000 -- r4=0
|
| 8049 |
|
|
wr5 000000 -- r5=0
|
| 8050 |
|
|
wsp 001400 -- sp=1400
|
| 8051 |
30 |
wfjm |
cres
|
| 8052 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 8053 |
|
|
wtgo
|
| 8054 |
|
|
rpc d=013262 -- ! pc=halt
|
| 8055 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8056 |
|
|
wal 037000 -- check result area
|
| 8057 |
|
|
brm 12
|
| 8058 |
|
|
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
|
| 8059 |
|
|
d=000000 -- !
|
| 8060 |
|
|
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
|
| 8061 |
|
|
d=000000 -- !
|
| 8062 |
|
|
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
|
| 8063 |
|
|
d=000006 -- !
|
| 8064 |
|
|
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
|
| 8065 |
|
|
d=000014 -- !
|
| 8066 |
|
|
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
|
| 8067 |
|
|
d=000140 -- !
|
| 8068 |
|
|
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
|
| 8069 |
|
|
d=000300 -- !
|
| 8070 |
|
|
#--------
|
| 8071 |
|
|
C Exec test 46.13brc1: BITB - reg, C=1
|
| 8072 |
|
|
#
|
| 8073 |
|
|
wal 013246 -- setup test instructions:
|
| 8074 |
|
|
bwm 2
|
| 8075 |
|
|
000261 -- ccmov= sec
|
| 8076 |
|
|
130405 -- iut= bitb r4,r5
|
| 8077 |
|
|
wr0 177776 -- r0=177776
|
| 8078 |
|
|
wr1 000006 -- r1=6
|
| 8079 |
|
|
wr2 036000 -- r2=36000
|
| 8080 |
|
|
wr3 037000 -- r3=37000
|
| 8081 |
|
|
wr4 000000 -- r4=0
|
| 8082 |
|
|
wr5 000000 -- r5=0
|
| 8083 |
|
|
wsp 001400 -- sp=1400
|
| 8084 |
30 |
wfjm |
cres
|
| 8085 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 8086 |
|
|
wtgo
|
| 8087 |
|
|
rpc d=013262 -- ! pc=halt
|
| 8088 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8089 |
|
|
wal 037000 -- check result area
|
| 8090 |
|
|
brm 12
|
| 8091 |
|
|
d=000005 -- ! bitb 000000,000000 -> n0z1v0c1; (000000)
|
| 8092 |
|
|
d=000000 -- !
|
| 8093 |
|
|
d=000005 -- ! bitb 000003,000000 -> n0z1v0c1; (000000)
|
| 8094 |
|
|
d=000000 -- !
|
| 8095 |
|
|
d=000001 -- ! bitb 000003,000006 -> n0z0v0c1; (000002)
|
| 8096 |
|
|
d=000006 -- !
|
| 8097 |
|
|
d=000005 -- ! bitb 000003,000014 -> n0z1v0c1; (000000)
|
| 8098 |
|
|
d=000014 -- !
|
| 8099 |
|
|
d=000001 -- ! bitb 000300,000140 -> n0z0v0c1; (000100)
|
| 8100 |
|
|
d=000140 -- !
|
| 8101 |
|
|
d=000011 -- ! bitb 000300,000300 -> n1z0v0c1; (000300)
|
| 8102 |
|
|
d=000300 -- !
|
| 8103 |
|
|
#--------
|
| 8104 |
|
|
C Exec test 46.13bmc0: BITB - mem, C=0
|
| 8105 |
|
|
#
|
| 8106 |
|
|
wal 013276 -- setup test instructions:
|
| 8107 |
|
|
bwm 2
|
| 8108 |
|
|
000241 -- ccmov= clc
|
| 8109 |
|
|
131415 -- iut= bitb (r4),(r5)
|
| 8110 |
|
|
wr0 177776 -- r0=177776
|
| 8111 |
|
|
wr1 000006 -- r1=6
|
| 8112 |
|
|
wr2 036000 -- r2=36000
|
| 8113 |
|
|
wr3 037000 -- r3=37000
|
| 8114 |
|
|
wr4 001400 -- r4=1400
|
| 8115 |
|
|
wr5 001402 -- r5=1402
|
| 8116 |
|
|
wsp 001400 -- sp=1400
|
| 8117 |
30 |
wfjm |
cres
|
| 8118 |
2 |
wfjm |
stapc 013270 -- start @ 13270 (2op mem)
|
| 8119 |
|
|
wtgo
|
| 8120 |
|
|
rpc d=013312 -- ! pc=halt
|
| 8121 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8122 |
|
|
wal 037000 -- check result area
|
| 8123 |
|
|
brm 12
|
| 8124 |
|
|
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
|
| 8125 |
|
|
d=000000 -- !
|
| 8126 |
|
|
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
|
| 8127 |
|
|
d=000000 -- !
|
| 8128 |
|
|
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
|
| 8129 |
|
|
d=000006 -- !
|
| 8130 |
|
|
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
|
| 8131 |
|
|
d=000014 -- !
|
| 8132 |
|
|
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
|
| 8133 |
|
|
d=000140 -- !
|
| 8134 |
|
|
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
|
| 8135 |
|
|
d=000300 -- !
|
| 8136 |
|
|
#--------
|
| 8137 |
|
|
C Exec test 46.14brc0: BICB - reg, C=0
|
| 8138 |
|
|
#
|
| 8139 |
|
|
wal 013246 -- setup test instructions:
|
| 8140 |
|
|
bwm 2
|
| 8141 |
|
|
000241 -- ccmov= clc
|
| 8142 |
|
|
140405 -- iut= bicb r4,r5
|
| 8143 |
|
|
wr0 177776 -- r0=177776
|
| 8144 |
|
|
wr1 000006 -- r1=6
|
| 8145 |
|
|
wr2 036000 -- r2=36000
|
| 8146 |
|
|
wr3 037000 -- r3=37000
|
| 8147 |
|
|
wr4 000000 -- r4=0
|
| 8148 |
|
|
wr5 000000 -- r5=0
|
| 8149 |
|
|
wsp 001400 -- sp=1400
|
| 8150 |
30 |
wfjm |
cres
|
| 8151 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 8152 |
|
|
wtgo
|
| 8153 |
|
|
rpc d=013262 -- ! pc=halt
|
| 8154 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8155 |
|
|
wal 037000 -- check result area
|
| 8156 |
|
|
brm 12
|
| 8157 |
|
|
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
|
| 8158 |
|
|
d=000000 -- !
|
| 8159 |
|
|
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
|
| 8160 |
|
|
d=000000 -- !
|
| 8161 |
|
|
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
|
| 8162 |
|
|
d=000004 -- !
|
| 8163 |
|
|
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
|
| 8164 |
|
|
d=000014 -- !
|
| 8165 |
|
|
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
|
| 8166 |
|
|
d=000040 -- !
|
| 8167 |
|
|
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
|
| 8168 |
|
|
d=000000 -- !
|
| 8169 |
|
|
#--------
|
| 8170 |
|
|
C Exec test 46.14brc1: BICB - reg, C=1
|
| 8171 |
|
|
#
|
| 8172 |
|
|
wal 013246 -- setup test instructions:
|
| 8173 |
|
|
bwm 2
|
| 8174 |
|
|
000261 -- ccmov= sec
|
| 8175 |
|
|
140405 -- iut= bicb r4,r5
|
| 8176 |
|
|
wr0 177776 -- r0=177776
|
| 8177 |
|
|
wr1 000006 -- r1=6
|
| 8178 |
|
|
wr2 036000 -- r2=36000
|
| 8179 |
|
|
wr3 037000 -- r3=37000
|
| 8180 |
|
|
wr4 000000 -- r4=0
|
| 8181 |
|
|
wr5 000000 -- r5=0
|
| 8182 |
|
|
wsp 001400 -- sp=1400
|
| 8183 |
30 |
wfjm |
cres
|
| 8184 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 8185 |
|
|
wtgo
|
| 8186 |
|
|
rpc d=013262 -- ! pc=halt
|
| 8187 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8188 |
|
|
wal 037000 -- check result area
|
| 8189 |
|
|
brm 12
|
| 8190 |
|
|
d=000005 -- ! bicb 000000,000000 -> n0z1v0c1; 000000
|
| 8191 |
|
|
d=000000 -- !
|
| 8192 |
|
|
d=000005 -- ! bicb 000003,000000 -> n0z1v0c1; 000000
|
| 8193 |
|
|
d=000000 -- !
|
| 8194 |
|
|
d=000001 -- ! bicb 000003,000006 -> n0z0v0c1; 000004
|
| 8195 |
|
|
d=000004 -- !
|
| 8196 |
|
|
d=000001 -- ! bicb 000003,000014 -> n0z0v0c1; 000014
|
| 8197 |
|
|
d=000014 -- !
|
| 8198 |
|
|
d=000001 -- ! bicb 000300,000140 -> n0z0v0c1; 000040
|
| 8199 |
|
|
d=000040 -- !
|
| 8200 |
|
|
d=000005 -- ! bicb 000300,000300 -> n0z1v0c1; 000000
|
| 8201 |
|
|
d=000000 -- !
|
| 8202 |
|
|
#--------
|
| 8203 |
|
|
C Exec test 46.14bmrc0: BICB - mem, C=0
|
| 8204 |
|
|
#
|
| 8205 |
|
|
wal 013276 -- setup test instructions:
|
| 8206 |
|
|
bwm 2
|
| 8207 |
|
|
000241 -- ccmov= clc
|
| 8208 |
|
|
141415 -- iut= bicb (r4),(r5)
|
| 8209 |
|
|
wr0 177776 -- r0=177776
|
| 8210 |
|
|
wr1 000006 -- r1=6
|
| 8211 |
|
|
wr2 036000 -- r2=36000
|
| 8212 |
|
|
wr3 037000 -- r3=37000
|
| 8213 |
|
|
wr4 001400 -- r4=1400
|
| 8214 |
|
|
wr5 001402 -- r5=1402
|
| 8215 |
|
|
wsp 001400 -- sp=1400
|
| 8216 |
30 |
wfjm |
cres
|
| 8217 |
2 |
wfjm |
stapc 013270 -- start @ 13270 (2op mem)
|
| 8218 |
|
|
wtgo
|
| 8219 |
|
|
rpc d=013312 -- ! pc=halt
|
| 8220 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8221 |
|
|
wal 037000 -- check result area
|
| 8222 |
|
|
brm 12
|
| 8223 |
|
|
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
|
| 8224 |
|
|
d=000000 -- !
|
| 8225 |
|
|
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
|
| 8226 |
|
|
d=000000 -- !
|
| 8227 |
|
|
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
|
| 8228 |
|
|
d=000004 -- !
|
| 8229 |
|
|
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
|
| 8230 |
|
|
d=000014 -- !
|
| 8231 |
|
|
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
|
| 8232 |
|
|
d=000040 -- !
|
| 8233 |
|
|
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
|
| 8234 |
|
|
d=000000 -- !
|
| 8235 |
|
|
#--------
|
| 8236 |
|
|
C Exec test 46.15brc0: BISB - reg, C=0
|
| 8237 |
|
|
#
|
| 8238 |
|
|
wal 013246 -- setup test instructions:
|
| 8239 |
|
|
bwm 2
|
| 8240 |
|
|
000241 -- ccmov= clc
|
| 8241 |
|
|
150405 -- iut= bisb r4,r5
|
| 8242 |
|
|
wr0 177776 -- r0=177776
|
| 8243 |
|
|
wr1 000006 -- r1=6
|
| 8244 |
|
|
wr2 036000 -- r2=36000
|
| 8245 |
|
|
wr3 037000 -- r3=37000
|
| 8246 |
|
|
wr4 000000 -- r4=0
|
| 8247 |
|
|
wr5 000000 -- r5=0
|
| 8248 |
|
|
wsp 001400 -- sp=1400
|
| 8249 |
30 |
wfjm |
cres
|
| 8250 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 8251 |
|
|
wtgo
|
| 8252 |
|
|
rpc d=013262 -- ! pc=halt
|
| 8253 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8254 |
|
|
wal 037000 -- check result area
|
| 8255 |
|
|
brm 12
|
| 8256 |
|
|
d=000004 -- ! bisb 000000,000000 -> n0z1v0c0; 000000
|
| 8257 |
|
|
d=000000 -- !
|
| 8258 |
|
|
d=000000 -- ! bisb 000003,000000 -> n0z0v0c0; 000003
|
| 8259 |
|
|
d=000003 -- !
|
| 8260 |
|
|
d=000000 -- ! bisb 000003,000006 -> n0z0v0c0; 000007
|
| 8261 |
|
|
d=000007 -- !
|
| 8262 |
|
|
d=000000 -- ! bisb 000003,000014 -> n0z0v0c0; 000017
|
| 8263 |
|
|
d=000017 -- !
|
| 8264 |
|
|
d=000010 -- ! bisb 000300,000140 -> n1z0v0c0; 000340
|
| 8265 |
|
|
d=000340 -- !
|
| 8266 |
|
|
d=000010 -- ! bisb 000300,000300 -> n1z0v0c0; 000300
|
| 8267 |
|
|
d=000300 -- !
|
| 8268 |
|
|
#--------
|
| 8269 |
|
|
C Exec test 46.15brc1: BISB - reg, C=1
|
| 8270 |
|
|
#
|
| 8271 |
|
|
wal 013246 -- setup test instructions:
|
| 8272 |
|
|
bwm 2
|
| 8273 |
|
|
000261 -- ccmov= sec
|
| 8274 |
|
|
150405 -- iut= bisb r4,r5
|
| 8275 |
|
|
wr0 177776 -- r0=177776
|
| 8276 |
|
|
wr1 000006 -- r1=6
|
| 8277 |
|
|
wr2 036000 -- r2=36000
|
| 8278 |
|
|
wr3 037000 -- r3=37000
|
| 8279 |
|
|
wr4 000000 -- r4=0
|
| 8280 |
|
|
wr5 000000 -- r5=0
|
| 8281 |
|
|
wsp 001400 -- sp=1400
|
| 8282 |
30 |
wfjm |
cres
|
| 8283 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 8284 |
|
|
wtgo
|
| 8285 |
|
|
rpc d=013262 -- ! pc=halt
|
| 8286 |
|
|
rr1 d=000000 -- ! r1=0
|
| 8287 |
|
|
wal 037000 -- check result area
|
| 8288 |
|
|
brm 12
|
| 8289 |
|
|
d=000005 -- ! bisb 000000,000000 -> n0z1v0c1; 000000
|
| 8290 |
|
|
d=000000 -- !
|
| 8291 |
|
|
d=000001 -- ! bisb 000003,000000 -> n0z0v0c1; 000003
|
| 8292 |
|
|
d=000003 -- !
|
| 8293 |
|
|
d=000001 -- ! bisb 000003,000006 -> n0z0v0c1; 000007
|
| 8294 |
|
|
d=000007 -- !
|
| 8295 |
|
|
d=000001 -- ! bisb 000003,000014 -> n0z0v0c1; 000017
|
| 8296 |
|
|
d=000017 -- !
|
| 8297 |
|
|
d=000011 -- ! bisb 000300,000140 -> n1z0v0c1; 000340
|
| 8298 |
|
|
d=000340 -- !
|
| 8299 |
|
|
d=000011 -- ! bisb 000300,000300 -> n1z0v0c1; 000300
|
| 8300 |
|
|
d=000300 -- !
|
| 8301 |
|
|
#--------
|
| 8302 |
|
|
C Exec test 46.17br: CMPB - reg
|
| 8303 |
|
|
#
|
| 8304 |
|
|
wal 036000 -- setup test vector: for cmp (b)
|
| 8305 |
|
|
bwm 38
|
| 8306 |
|
|
000000 -- cmpb 000000,000000
|
| 8307 |
|
|
000000 --
|
| 8308 |
|
|
000001 -- cmpb 000001,000000
|
| 8309 |
|
|
000000 --
|
| 8310 |
|
|
000377 -- cmpb 000377,000000
|
| 8311 |
|
|
000000 --
|
| 8312 |
|
|
000000 -- cmpb 000000,000001
|
| 8313 |
|
|
000001 --
|
| 8314 |
|
|
000001 -- cmpb 000001,000001
|
| 8315 |
|
|
000001 --
|
| 8316 |
|
|
000377 -- cmpb 000377,000001
|
| 8317 |
|
|
000001 --
|
| 8318 |
|
|
000176 -- cmpb 000176,000177
|
| 8319 |
|
|
000177 --
|
| 8320 |
|
|
000177 -- cmpb 000177,000177
|
| 8321 |
|
|
000177 --
|
| 8322 |
|
|
000200 -- cmpb 000200,000177
|
| 8323 |
|
|
000177 --
|
| 8324 |
|
|
000001 -- cmpb 000001,000177
|
| 8325 |
|
|
000177 --
|
| 8326 |
|
|
000377 -- cmpb 000377,000177
|
| 8327 |
|
|
000177 --
|
| 8328 |
|
|
000177 -- cmpb 000177,000200
|
| 8329 |
|
|
000200 --
|
| 8330 |
|
|
000200 -- cmpb 000200,000200
|
| 8331 |
|
|
000200 --
|
| 8332 |
|
|
000201 -- cmpb 000201,000200
|
| 8333 |
|
|
000200 --
|
| 8334 |
|
|
000001 -- cmpb 000001,000200
|
| 8335 |
|
|
000200 --
|
| 8336 |
|
|
000377 -- cmpb 000377,000200
|
| 8337 |
|
|
000200 --
|
| 8338 |
|
|
000000 -- cmpb 000000,000377
|
| 8339 |
|
|
000377 --
|
| 8340 |
|
|
000001 -- cmpb 000001,000377
|
| 8341 |
|
|
000377 --
|
| 8342 |
|
|
000377 -- cmpb 000377,000377
|
| 8343 |
|
|
000377 --
|
| 8344 |
|
|
wal 013246 -- setup test instructions:
|
| 8345 |
|
|
bwm 2
|
| 8346 |
|
|
000241 -- ccmov= clc
|
| 8347 |
|
|
120405 -- iut= cmpb r4,r5
|
| 8348 |
|
|
wr0 177776 -- r0=177776
|
| 8349 |
|
|
wr1 000023 -- r1=23 (19.)
|
| 8350 |
|
|
wr2 036000 -- r2=36000
|
| 8351 |
|
|
wr3 037000 -- r3=37000
|
| 8352 |
|
|
wr4 000000 -- r4=0
|
| 8353 |
|
|
wr5 000000 -- r5=0
|
| 8354 |
|
|
wsp 001400 -- sp=1400
|
| 8355 |
30 |
wfjm |
cres
|
| 8356 |
2 |
wfjm |
stapc 013240 -- start @ 13240 (2op reg)
|
| 8357 |
|
|
wtgo
|
| 8358 |
|
|
rpc d=013262 -- ! pc=halt
|
| 8359 |
|
|
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
|
| 8360 |
|
|
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
|
| 8361 |
|
|
brm 38
|
| 8362 |
|
|
d=000004 -- ! cmpb 000000,000000 -> n0z1v0c0; (000000)
|
| 8363 |
|
|
d=000000 -- !
|
| 8364 |
|
|
d=000000 -- ! cmpb 000001,000000 -> n0z0v0c0; (000001)
|
| 8365 |
|
|
d=000000 -- !
|
| 8366 |
|
|
d=000010 -- ! cmpb 000377,000000 -> n1z0v0c0; (000377)
|
| 8367 |
|
|
d=000000 -- !
|
| 8368 |
|
|
d=000011 -- ! cmpb 000000,000001 -> n1z0v0c1; (000377+C)
|
| 8369 |
|
|
d=000001 -- !
|
| 8370 |
|
|
d=000004 -- ! cmpb 000001,000001 -> n0z1v0c0; (000000)
|
| 8371 |
|
|
d=000001 -- !
|
| 8372 |
|
|
d=000010 -- ! cmpb 000377,000001 -> n1z0v0c0; (000376)
|
| 8373 |
|
|
d=000001 -- !
|
| 8374 |
|
|
d=000011 -- ! cmpb 000176,000177 -> n1z0v0c1; (000377+C)
|
| 8375 |
|
|
d=000177 -- !
|
| 8376 |
|
|
d=000004 -- ! cmpb 000177,000177 -> n0z1v0c0; (000000)
|
| 8377 |
|
|
d=000177 -- !
|
| 8378 |
|
|
d=000002 -- ! cmpb 000200,000177 -> n0z0v1c0; (000001)
|
| 8379 |
|
|
d=000177 -- !
|
| 8380 |
|
|
d=000011 -- ! cmpb 000001,000177 -> n1z0v0c1; (000202+C)
|
| 8381 |
|
|
d=000177 -- !
|
| 8382 |
|
|
d=000010 -- ! cmpb 000377,000177 -> n1z0v0c0; (000200)
|
| 8383 |
|
|
d=000177 -- !
|
| 8384 |
|
|
d=000013 -- ! cmpb 000177,000200 -> n1z0v1c1; (000377+C)
|
| 8385 |
|
|
d=000200 -- !
|
| 8386 |
|
|
d=000004 -- ! cmpb 000200,000200 -> n0z1v0c0; (000000)
|
| 8387 |
|
|
d=000200 -- !
|
| 8388 |
|
|
d=000000 -- ! cmpb 000201,000200 -> n0z0v0c0; (000001)
|
| 8389 |
|
|
d=000200 -- !
|
| 8390 |
|
|
d=000013 -- ! cmpb 000001,000200 -> n1z0v1c1; (000201+C)
|
| 8391 |
|
|
d=000200 -- !
|
| 8392 |
|
|
d=000000 -- ! cmpb 000377,000200 -> n0z0v0c0; (000177)
|
| 8393 |
|
|
d=000200 -- !
|
| 8394 |
|
|
d=000001 -- ! cmpb 000000,000377 -> n0z0v0c1; (000001+C)
|
| 8395 |
|
|
d=000377 -- !
|
| 8396 |
|
|
d=000001 -- ! cmpb 000001,000377 -> n0z0v0c1; (000002+C)
|
| 8397 |
|
|
d=000377 -- !
|
| 8398 |
|
|
d=000004 -- ! cmpb 000377,000377 -> n0z1v0c0; (000000)
|
| 8399 |
|
|
d=000377 -- !
|
| 8400 |
|
|
#-----------------------------------------------------------------------------
|
| 8401 |
|
|
C Setup code 47 [base 13400] (pipeline torture tests)
|
| 8402 |
|
|
#
|
| 8403 |
|
|
wal 013400 -- data:
|
| 8404 |
|
|
wmi 000077 -- marker
|
| 8405 |
|
|
wal 013402 -- code 1:
|
| 8406 |
|
|
bwm 13
|
| 8407 |
|
|
016727 -- mov -6(pc),(pc)+ ;
|
| 8408 |
|
|
177772
|
| 8409 |
|
|
000000 -- halt ; will be overwritten
|
| 8410 |
|
|
016737 -- mov -10(pc),@(pc)+ ;
|
| 8411 |
|
|
177770
|
| 8412 |
|
|
013400
|
| 8413 |
|
|
005200 -- inc r0 ;
|
| 8414 |
|
|
#13420
|
| 8415 |
|
|
010317 -- mov r3,(pc) ; will overwrite next instruction
|
| 8416 |
|
|
000000 -- halt ; will be overwritten
|
| 8417 |
|
|
005200 -- inc r0 ;
|
| 8418 |
|
|
010447 -- mov r4,-(pc) ; will overwrite itself
|
| 8419 |
|
|
005200 -- inc r0 ;
|
| 8420 |
|
|
000000 -- halt ;
|
| 8421 |
|
|
#
|
| 8422 |
|
|
wal 013440 -- code 2: (pipeline tester adapted from KDJ11A.MAC)
|
| 8423 |
|
|
bwm 15
|
| 8424 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
| 8425 |
|
|
000240 -- nop
|
| 8426 |
|
|
000111 -- jmp (r1)
|
| 8427 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
| 8428 |
|
|
000240 -- nop
|
| 8429 |
|
|
000111 -- jmp (r1)
|
| 8430 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
| 8431 |
|
|
000240 -- nop
|
| 8432 |
|
|
#13460
|
| 8433 |
|
|
000111 -- jmp (r1)
|
| 8434 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
| 8435 |
|
|
000240 -- nop
|
| 8436 |
|
|
000111 -- jmp (r1)
|
| 8437 |
|
|
000000 -- halt ; should halt here !
|
| 8438 |
|
|
000000 -- halt ;
|
| 8439 |
|
|
000000 -- halt ; should not jmp here !
|
| 8440 |
|
|
#
|
| 8441 |
|
|
C Exec code 47 (pipeline torture tests)
|
| 8442 |
|
|
C Exec test 47.1 (some self-modifying code, use (pc)+, (pc), -(pc)):
|
| 8443 |
|
|
#
|
| 8444 |
|
|
wr0 000000 -- r0=0
|
| 8445 |
|
|
wr1 000000 -- r1=0
|
| 8446 |
|
|
wr2 000000 -- r2=0
|
| 8447 |
|
|
wr3 005201 -- r3= inc r1
|
| 8448 |
|
|
wr4 005202 -- r4= inc r2
|
| 8449 |
30 |
wfjm |
cres
|
| 8450 |
2 |
wfjm |
stapc 013402 -- start @ 13402
|
| 8451 |
|
|
wtgo
|
| 8452 |
|
|
rpc d=013434 -- ! pc
|
| 8453 |
|
|
rr0 d=000003 -- ! r0
|
| 8454 |
|
|
rr1 d=000001 -- ! r1
|
| 8455 |
|
|
rr2 d=000001 -- ! r2
|
| 8456 |
|
|
rr3 d=005201 -- ! r3
|
| 8457 |
|
|
rr4 d=005202 -- ! r4
|
| 8458 |
|
|
#
|
| 8459 |
|
|
wal 013400 -- check data area:
|
| 8460 |
|
|
rmi d=177772 -- ! new marker ; written by mov -10(pc),@(pc)+
|
| 8461 |
|
|
wal 013402 -- check code area:
|
| 8462 |
|
|
brm 13
|
| 8463 |
|
|
d=016727 -- ! mov -6(pc),(pc)+ ;
|
| 8464 |
|
|
d=177772 -- !
|
| 8465 |
|
|
d=000077 -- ! ; written by mov -6(pc),(pc)+
|
| 8466 |
|
|
d=016737 -- ! mov -10(pc),@(pc)+;
|
| 8467 |
|
|
d=177770 -- !
|
| 8468 |
|
|
d=013400 -- !
|
| 8469 |
|
|
d=005200 -- ! inc r0 ;
|
| 8470 |
|
|
#13320
|
| 8471 |
|
|
d=010317 -- ! mov r3,(pc) ;
|
| 8472 |
|
|
d=005201 -- ! inc r1 ; written by mov r3,(pc); executed
|
| 8473 |
|
|
d=005200 -- ! inc r0 ;
|
| 8474 |
|
|
d=005202 -- ! inc r2 ; written by mov r4,-(pc); executed
|
| 8475 |
|
|
d=005200 -- ! inc r0 ;
|
| 8476 |
|
|
d=000000 -- ! halt ;
|
| 8477 |
|
|
#
|
| 8478 |
|
|
C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70)
|
| 8479 |
|
|
#
|
| 8480 |
|
|
wr1 013474 -- r1=13474 (alternate halt)
|
| 8481 |
30 |
wfjm |
cres
|
| 8482 |
2 |
wfjm |
stapc 013440 -- start @ 13440
|
| 8483 |
|
|
wtgo
|
| 8484 |
|
|
rpc d=013472 -- ! pc
|
| 8485 |
|
|
wal 013440 -- check code area:
|
| 8486 |
|
|
brm 13
|
| 8487 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
| 8488 |
|
|
d=000240 -- ! nop
|
| 8489 |
|
|
d=000240 -- ! nop ; written; executed
|
| 8490 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
| 8491 |
|
|
d=000240 -- ! nop
|
| 8492 |
|
|
d=000240 -- ! nop ; written; executed
|
| 8493 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
| 8494 |
|
|
d=000240 -- ! nop
|
| 8495 |
|
|
#13360
|
| 8496 |
|
|
d=000240 -- ! nop ; written; executed
|
| 8497 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
| 8498 |
|
|
d=000240 -- ! nop
|
| 8499 |
|
|
d=000240 -- ! nop ; written; executed
|
| 8500 |
|
|
d=000000 -- ! halt ;
|
| 8501 |
|
|
#-----------------------------------------------------------------------------
|
| 8502 |
|
|
C Setup code 50 [base 13500] (check that all reserved instructions trap to 10)
|
| 8503 |
|
|
#
|
| 8504 |
|
|
wal 013500 -- code (to be single stepped...)
|
| 8505 |
|
|
bwm 17
|
| 8506 |
|
|
000007 -- 000007
|
| 8507 |
|
|
000010 -- 000010-000077
|
| 8508 |
|
|
000077 --
|
| 8509 |
|
|
000210 -- 000210-000227
|
| 8510 |
|
|
000227 --
|
| 8511 |
|
|
007000 -- 007000-007777
|
| 8512 |
|
|
007777 --
|
| 8513 |
|
|
075000 -- 075000-076777
|
| 8514 |
|
|
#13420
|
| 8515 |
|
|
076777 --
|
| 8516 |
|
|
106400 -- 106400-106477
|
| 8517 |
|
|
106477 --
|
| 8518 |
|
|
106700 -- 106700-106777
|
| 8519 |
|
|
106777 --
|
| 8520 |
|
|
107000 -- 107000-107777
|
| 8521 |
|
|
107777 --
|
| 8522 |
|
|
170000 -- 170000-177777 (no FPU)
|
| 8523 |
|
|
#13440
|
| 8524 |
|
|
177777 --
|
| 8525 |
|
|
#
|
| 8526 |
|
|
C Exec code 50 (check that all reserved instructions trap to 10)
|
| 8527 |
|
|
C Test odd address abort
|
| 8528 |
|
|
#
|
| 8529 |
30 |
wfjm |
cres -- console reset
|
| 8530 |
2 |
wfjm |
wps 000000 -- clear psw
|
| 8531 |
|
|
wal 001374 -- clean stack
|
| 8532 |
|
|
bwm 2
|
| 8533 |
|
|
000000 --
|
| 8534 |
|
|
000000 --
|
| 8535 |
|
|
wsp 001400 -- sp=1400
|
| 8536 |
|
|
wpc 013500 -- pc=13500
|
| 8537 |
|
|
step -- step (000007): trap 10 [[s:2]]
|
| 8538 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8539 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8540 |
|
|
#
|
| 8541 |
|
|
wsp 001400 -- sp=1400
|
| 8542 |
|
|
wpc 013502 -- pc=13502
|
| 8543 |
|
|
step -- step (000010): trap 10 [[s:2]]
|
| 8544 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8545 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8546 |
|
|
#
|
| 8547 |
|
|
wsp 001400 -- sp=1400
|
| 8548 |
|
|
wpc 013504 -- pc=13504
|
| 8549 |
|
|
step -- step (000077): trap 10 [[s:2]]
|
| 8550 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8551 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8552 |
|
|
#
|
| 8553 |
|
|
wsp 001400 -- sp=1400
|
| 8554 |
|
|
wpc 013506 -- pc=13506
|
| 8555 |
|
|
step -- step (000210): trap 10 [[s:2]]
|
| 8556 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8557 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8558 |
|
|
#
|
| 8559 |
|
|
wsp 001400 -- sp=1400
|
| 8560 |
|
|
wpc 013510 -- pc=13510
|
| 8561 |
|
|
step -- step (000227): trap 10 [[s:2]]
|
| 8562 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8563 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8564 |
|
|
#
|
| 8565 |
|
|
wsp 001400 -- sp=1400
|
| 8566 |
|
|
wpc 013512 -- pc=13512
|
| 8567 |
|
|
step -- step (007000): trap 10 [[s:2]]
|
| 8568 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8569 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8570 |
|
|
#
|
| 8571 |
|
|
wsp 001400 -- sp=1400
|
| 8572 |
|
|
wpc 013514 -- pc=13514
|
| 8573 |
|
|
step -- step (007777): trap 10 [[s:2]]
|
| 8574 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8575 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8576 |
|
|
#
|
| 8577 |
|
|
wsp 001400 -- sp=1400
|
| 8578 |
|
|
wpc 013516 -- pc=13516
|
| 8579 |
|
|
step -- step (075000): trap 10 [[s:2]]
|
| 8580 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8581 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8582 |
|
|
#
|
| 8583 |
|
|
wsp 001400 -- sp=1400
|
| 8584 |
|
|
wpc 013520 -- pc=13520
|
| 8585 |
|
|
step -- step (076777): trap 10 [[s:2]]
|
| 8586 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8587 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8588 |
|
|
#
|
| 8589 |
|
|
wsp 001400 -- sp=1400
|
| 8590 |
|
|
wpc 013522 -- pc=13522
|
| 8591 |
|
|
step -- step (106400): trap 10 [[s:2]]
|
| 8592 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8593 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8594 |
|
|
#
|
| 8595 |
|
|
wsp 001400 -- sp=1400
|
| 8596 |
|
|
wpc 013524 -- pc=13524
|
| 8597 |
|
|
step -- step (106477): trap 10 [[s:2]]
|
| 8598 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8599 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8600 |
|
|
#
|
| 8601 |
|
|
wsp 001400 -- sp=1400
|
| 8602 |
|
|
wpc 013526 -- pc=13526
|
| 8603 |
|
|
step -- step (106700): trap 10 [[s:2]]
|
| 8604 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8605 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8606 |
|
|
#
|
| 8607 |
|
|
wsp 001400 -- sp=1400
|
| 8608 |
|
|
wpc 013530 -- pc=13530
|
| 8609 |
|
|
step -- step (106777): trap 10 [[s:2]]
|
| 8610 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8611 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8612 |
|
|
#
|
| 8613 |
|
|
wsp 001400 -- sp=1400
|
| 8614 |
|
|
wpc 013532 -- pc=13532
|
| 8615 |
|
|
step -- step (107000): trap 10 [[s:2]]
|
| 8616 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8617 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8618 |
|
|
#
|
| 8619 |
|
|
wsp 001400 -- sp=1400
|
| 8620 |
|
|
wpc 013534 -- pc=13534
|
| 8621 |
|
|
step -- step (107777): trap 10 [[s:2]]
|
| 8622 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8623 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8624 |
|
|
#
|
| 8625 |
|
|
wsp 001400 -- sp=1400
|
| 8626 |
|
|
wpc 013536 -- pc=13536
|
| 8627 |
|
|
step -- step (170000): trap 10 [[s:2]]
|
| 8628 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8629 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8630 |
|
|
#
|
| 8631 |
|
|
wsp 001400 -- sp=1400
|
| 8632 |
|
|
wpc 013540 -- pc=13540
|
| 8633 |
|
|
step -- step (177777): trap 10 [[s:2]]
|
| 8634 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
| 8635 |
|
|
rsp d=001374 -- ! sp=1374
|
| 8636 |
|
|
#-----------------------------------------------------------------------------
|
| 8637 |
|
|
#
|
| 8638 |
|
|
C Verify trap catchers integrity
|
| 8639 |
|
|
#
|
| 8640 |
|
|
wal 000004 -- vectors: 4...34 (trap catcher)
|
| 8641 |
|
|
brm 14
|
| 8642 |
|
|
d=000006 -- ! PC:06 ; vector 4
|
| 8643 |
|
|
d=000000 -- ! PS:0
|
| 8644 |
|
|
d=000012 -- ! PC:12 ; vector 10
|
| 8645 |
|
|
d=000000 -- ! PS:0
|
| 8646 |
|
|
d=000016 -- ! PC:16 ; vector 14 (T bit; BPT)
|
| 8647 |
|
|
d=000000 -- ! PS:0
|
| 8648 |
|
|
d=000022 -- ! PC:22 ; vector 20 (IOT)
|
| 8649 |
|
|
d=000000 -- ! PS:0
|
| 8650 |
|
|
d=000026 -- ! PC:26 ; vector 24 (Power fail, not used)
|
| 8651 |
|
|
d=000000 -- ! PS:0
|
| 8652 |
|
|
d=000032 -- ! PC:32 ; vector 30 (EMT)
|
| 8653 |
|
|
d=000000 -- ! PS:0
|
| 8654 |
|
|
d=000036 -- ! PC:36 ; vector 34 (TRAP)
|
| 8655 |
|
|
d=000000 -- ! PS:0
|
| 8656 |
|
|
wal 000240 -- vectors: 240,244,250 (trap catcher)
|
| 8657 |
|
|
brm 6
|
| 8658 |
|
|
d=000242 -- ! PC:242 ; vector 240 (PIRQ)
|
| 8659 |
|
|
d=000000 -- ! PS:0
|
| 8660 |
|
|
d=000246 -- ! PC:246 ; vector 244 (FPU)
|
| 8661 |
|
|
d=000000 -- ! PS:0
|
| 8662 |
|
|
d=000252 -- ! PC:252 ; vector 250 (MMU)
|
| 8663 |
|
|
d=000000 -- ! PS:0
|
| 8664 |
|
|
#
|
| 8665 |
|
|
C Verify setup MMU
|
| 8666 |
|
|
# to avoid seeing AIB bits:
|
| 8667 |
|
|
# 1. check ARs; 2. re-write ARs to clear AIBs in DRs; 3. check DRs
|
| 8668 |
|
|
#
|
| 8669 |
|
|
wal 172340 -- kernel I space AR
|
| 8670 |
|
|
brm 8
|
| 8671 |
|
|
d=000000 -- ! 0
|
| 8672 |
|
|
d=000200 -- ! 200 020000 base
|
| 8673 |
|
|
d=000400 -- ! 400 040000 base
|
| 8674 |
|
|
d=000600 -- ! 600 060000 base
|
| 8675 |
|
|
d=001000 -- ! 1000 100000 base
|
| 8676 |
|
|
d=001200 -- ! 1200 120000 base
|
| 8677 |
|
|
d=001400 -- ! 1400 140000 base
|
| 8678 |
|
|
d=177600 -- !176000 (map to I/O page)
|
| 8679 |
|
|
#
|
| 8680 |
|
|
wal 172340 -- kernel I space AR
|
| 8681 |
|
|
bwm 8
|
| 8682 |
|
|
000000 -- 0
|
| 8683 |
|
|
000200 -- 200 020000 base
|
| 8684 |
|
|
000400 -- 400 040000 base
|
| 8685 |
|
|
000600 -- 600 060000 base
|
| 8686 |
|
|
001000 -- 1000 100000 base
|
| 8687 |
|
|
001200 -- 1200 120000 base
|
| 8688 |
|
|
001400 -- 1400 140000 base
|
| 8689 |
|
|
177600 -- 176000 (map to I/O page)
|
| 8690 |
|
|
#
|
| 8691 |
|
|
wal 172300 -- kernel I space DR
|
| 8692 |
|
|
brm 8
|
| 8693 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8694 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8695 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8696 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8697 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8698 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8699 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8700 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
| 8701 |
|
|
#
|
| 8702 |
|
|
wal 000000 -- last cmd shouldn't be 21 or 23 ...
|
