OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.74/] [tools/] [asm-11/] [lib/] [tcode_std_base.mac] - Blame information for rev 38

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 34 wfjm
; $Id: tcode_std_base.mac 710 2015-08-31 06:19:56Z mueller $
2
; Copyright 2015- by Walter F.J. Mueller 
3
; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
4
;
5
; Default tcode base code for simple tests
6
;
7
        .include        |lib/tcode_std_start.mac|
8
;
9
        clr     @pdreg          ; clear display reg
10
        jmp     loop1
11
;
12
; IOT handler
13
;   called at end of each test
14
;   increments tstno and updates display register
15
;
16
vh.iot: inc     tstno           ; bump test number
17
                                ; setup display reg
18
        movb    tstno,swdreg    ;    low byte: test number
19
        movb    runno,swdreg+1  ;   high byte: pass number
20
        mov     swdreg,@pdreg   ; write display reg (is noop when sw dreg used)
21
        rtt
22
;
23
loop:   bit     #bit00,@psreg   ; test 'loop bit'
24
        bne     1$
25
        jmp     stop
26
 
27
1$:     reset                   ; re-reset CPU for each pass
28
        mov     #stack,sp       ; re-init  SP
29
        clr     tstno           ; reset test counter
30
        inc     runno           ; bump  pass counter
31
;
32
        .include        |lib/vec_cpucatch_reset.mac|
33
        .include        |lib/vec_devcatch_reset.mac|
34
;
35
loop1:
36
        mov     #vh.iot,v..iot  ; setup IOT trap handler
37
        mov     #cp.pr7,v..iot+2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.