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[/] [w11/] [tags/] [w11a_V0.74/] [tools/] [asm-11/] [lib/] [vec_devcatch.mac] - Blame information for rev 38

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1 34 wfjm
; $Id: vec_devcatch.mac 710 2015-08-31 06:19:56Z mueller $
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; Copyright 2015- by Walter F.J. Mueller 
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; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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;
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; vector catcher for device interrupts (subset used by w11)
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;
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;   w11 device summary from ibdr_maxisys.vhd:
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;
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;   ibbase  vec  pri  slot attn  sror device name
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;   177560  060    4  7  7    1  3/2  DL11-RX  1st
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;           064    4  6  6    ^       DL11-TX  1st
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;   177550  070    4  3  3   10  4/1  PC11/PTR
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;           074    4  2  2    ^       PC11/PTP
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;   177546  100    6 14 15    -  1/3  KW11-L
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;   172540  104    7    17    -  1/1  KW11-P
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;   174510  120    5    14    9  1/4  DEUNA
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;   174400  160    5 12 12    5  2/2  RL11
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;   177514  200    4  1  1    8  4/2  LP11
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;   177400  220    5 11 11    4  2/3  RK11
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;   172520  224    5 10 10    7  2/4  TM11
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;   176700  254    5 13 13    6  2/1  RHRP
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;   177500  260    6 15 16    -  1/2  IIST
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;   176500  300    4  5  5    2  3/3  DL11-RX  2nd
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;           304    4  4  4    ^       DL11-TX  2nd
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;   160100  310?   5  9  9    3  3/1  DZ11-RX
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;           314?   5  8  8    ^       DZ11-TX
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;
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        . = 000060
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v..dlr: .word   v..dlr+2        ; vec  60 (DL11-RX  1st)
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        .word   0
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v..dlt: .word   v..dlt+2        ; vec  64 (DL11-TX  1st)
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        .word   0
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;
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v..ptr: .word   v..ptr+2        ; vec  70 (PC11/PTR)
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        .word   0
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v..ptp: .word   v..ptp+2        ; vec  74 (PC11/PTP)
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        .word   0
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;
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        . = 000100
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v..kwl: .word   v..kwl+2        ; vec 100 (KW11-L)
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        .word   0
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v..kwp: .word   v..kwp+2        ; vec 104 (KW11-P)
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        .word   0
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;
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        . = 000120
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v..deu: .word   v..deu+2        ; vec 120 (DEUNA)
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        .word   0
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;
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        . = 000160
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v..rl:  .word   v..rl+2         ; vec 120 (RL11)
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        .word   0
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;
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; Note on vector 200
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;   MAINDECs use 200 also as default start address. This vector catcher
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;   might therefore be overwritten later by startup code of test programs.
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;
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        . = 000200
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v..lp:  .word   v..lp+2         ; vec 200 (LP11)
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        .word   0
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;
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        . = 000220
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v..rk:  .word   v..rk+2         ; vec 220 (RK11)
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        .word   0
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v..tm:  .word   v..tm+2         ; vec 224 (TM11)
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        .word   0
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;
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        . = 000254
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v..rp:  .word   v..rp+2         ; vec 254 (RHRP)
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        .word   0
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v..iis: .word   v..iis+2        ; vec 250 (IIST)
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        .word   0
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;
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        . = 000300
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v..d2r: .word   v..d2r+2        ; vec 300 (DL11-RX  2nd)
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        .word   0
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v..d2t: .word   v..d2t+2        ; vec 304 (DL11-TX  2nd)
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        .word   0
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v..dzr: .word   v..dzr+2        ; vec 310 (DZ11-RX)
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        .word   0
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v..dzt: .word   v..dzt+2        ; vec 314 (DZ11-TX)
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        .word   0
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;

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