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# $Id: test_w11a_div.tcl 704 2015-07-25 14:18:03Z mueller $
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#
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# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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#
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# Revision History:
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# Date Rev Version Comment
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# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
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# 2014-07-20 570 1.0.2 add rw11::div_show_test; test late div quit cases
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# 2014-07-12 569 1.0.1 move sxt16/32 to rutil
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# 2014-07-11 568 1.0 Initial version
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# 2014-06-29 566 0.1 First draft
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#
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# Test div instruction
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#
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namespace eval rw11 {
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#
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# div_simh: calculate expected division result as pdp11 simh does it -------
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#
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# this pdp11 div emulation adopted from pdp11_cpu.c (git head 2014-06-09)
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proc div_simh {ddi dri} {
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set src2 $dri
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set src $ddi
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set qd [expr ($ddi>>16) & 0xffff]; # w11a default for V=1 bailouts
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set rd [expr $ddi & 0xffff]; # "
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set n [expr {($ddi<0) ^ ($dri<0)}]; # "
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set z 0; # "
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# quit if divident larger than possible 16 bit signed products
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if {$src > 1073774591 || $src < -1073741823} {
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return [list $qd $rd $n $z 1 0]
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}
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# quit if divisor zero
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if {$src2 == 0} {
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return [list $qd $rd $n $z 1 1]
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}
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if {$src2 & 0x8000} {
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set src2 [expr $src2 | ~ 077777]
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}
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if {$src & 0x80000000} {
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set src [expr $src | ~ 017777777777]
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}
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# Tcl "/" uses 'round down' sematics, while C (and PDP11) 'round to 0'
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# ddi dri Tcl C/C++
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# 34 5 q= 6 r= 4 q= 6 r= 4
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# 34 -5 q= 7 r=-1 q=-6 r= 4
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# -34 5 q=-7 r= 1 q=-6 r=-4
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# -34 -5 q= 6 r=-4 q= 6 r=-4
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# Tcl --> r same sign as divisor
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# C --> r same sign as divident
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# so add correction step to always get C/C++/PDP11 divide semantics
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#
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set q [expr $src / $src2]
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set r [expr ($src - ($src2 * $q))]
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if {$r!=0 && (($src<0) ^ ($r<0))} { # divident and remainder diff sign
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set r [expr $r - $src2]
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set q [expr $q + (($q<0)?1:-1)]
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}
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if {($q > 32767) || ($q < -32768)} {
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return [list $qd $rd $n $z 1 0]
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}
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set n [expr {$q < 0}]
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set z [expr {$q == 0}]
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return [list $q $r $n $z 0 0]
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}
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#
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# div_testd3: test division ddh,ddl,,dr + expected result ------------------
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#
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proc div_testd3 {cpu symName ddh ddl dr q r n z v c} {
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upvar 1 $symName sym
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set nzvc [expr {($n<<3) | ($z<<2) | ($v<<1) | $c}]
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set dr16 [expr {$dr & 0xffff}]
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set q16 [expr {$q & 0xffff}]
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set r16 [expr {$r & 0xffff}]
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# use rw11::div_show_test to enable generation of divtst files
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if {[info exists rw11::div_show_test] && $rw11::div_show_test} {
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set ddi [expr (($ddh&0xffff)<<16) + ($ddl&0xffff)]
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set ddi [rutil::sxt32 $ddi]
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set dri [rutil::sxt16 $dr16]
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set qi [rutil::sxt16 $q16]
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set ri [rutil::sxt16 $r16]
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puts [format "%06o %06o %06o : %d%d%d%d %06o %06o # %11d/%6d:%6d,%6d" \
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$ddh $ddl $dr16 $n $z $v $c $q16 $r16 $ddi $dri $qi $ri ]
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}
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rw11::asmrun $cpu sym r0 $ddh r1 $ddl r2 $dr16
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rw11::asmwait $cpu sym
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if {!$v && !$c} { # test q and r only when V=0 C=0 expected
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lappend treglist r0 $q16 r1 $r16
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}
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lappend treglist r3 $nzvc
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set errcnt [rw11::asmtreg $cpu {*}$treglist]
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if {$errcnt} {
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puts [format \
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"div FAIL: dd=%06o,%06o dr=%06o exp: q=%06o r=%06o nzvc=%d%d%d%d" \
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$ddh $ddl $dr16 $q16 $r16 $n $z $v $c]
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}
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return $errcnt
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}
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#
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# div_testd2: test division dd,dr + expected result ------------------------
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#
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proc div_testd2 {cpu symName dd dr q r n z v c} {
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upvar 1 $symName sym
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set ddh [expr {($dd>>16) & 0xffff}]
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set ddl [expr { $dd & 0xffff}]
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return [div_testd3 $cpu sym $ddh $ddl $dr $q $r $n $z $v $c]
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}
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#
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# div_testdqr: test division, give divisor, quotient and remainder ---------
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#
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proc div_testdqr {cpu symName dri qi ri} {
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upvar 1 $symName sym
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set dri [rutil::sxt16 $dri]
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set qi [rutil::sxt16 $qi]
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set ri [rutil::sxt16 $ri]
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set ddi [expr {$dri*$qi + $ri}]
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set simhres [div_simh $ddi $dri]
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set q [lindex $simhres 0]
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set r [lindex $simhres 1]
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set n [lindex $simhres 2]
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set z [lindex $simhres 3]
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set v [lindex $simhres 4]
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set c [lindex $simhres 5]
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return [div_testd2 $cpu sym $ddi $dri $q $r $n $z $v $c]
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}
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}
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# ----------------------------------------------------------------------------
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rlc log "test_div: test div instruction"
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$cpu ldasm -lst lst -sym sym {
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. = 1000
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stack:
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start: div r2,r0
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mov @#177776,r3
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bic #177760,r3
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halt
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stop:
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}
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rlc log " test basics (via testd2)"
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# dd dr q r n z v c
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rlc log " dr>0"
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rw11::div_testd2 $cpu sym 0 3 0 0 0 1 0 0
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rw11::div_testd2 $cpu sym 1 3 0 1 0 1 0 0
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rw11::div_testd2 $cpu sym 2 3 0 2 0 1 0 0
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rw11::div_testd2 $cpu sym 3 3 1 0 0 0 0 0
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rw11::div_testd2 $cpu sym 4 3 1 1 0 0 0 0
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rw11::div_testd2 $cpu sym -1 3 0 -1 0 1 0 0
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rw11::div_testd2 $cpu sym -2 3 0 -2 0 1 0 0
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rw11::div_testd2 $cpu sym -3 3 -1 0 1 0 0 0
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rw11::div_testd2 $cpu sym -4 3 -1 -1 1 0 0 0
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rlc log " dr<0"
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rw11::div_testd2 $cpu sym 0 -3 0 0 0 1 0 0
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rw11::div_testd2 $cpu sym 1 -3 0 1 0 1 0 0
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rw11::div_testd2 $cpu sym 2 -3 0 2 0 1 0 0
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rw11::div_testd2 $cpu sym 3 -3 -1 0 1 0 0 0
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rw11::div_testd2 $cpu sym 4 -3 -1 1 1 0 0 0
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rw11::div_testd2 $cpu sym -1 -3 0 -1 0 1 0 0
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rw11::div_testd2 $cpu sym -2 -3 0 -2 0 1 0 0
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rw11::div_testd2 $cpu sym -3 -3 1 0 0 0 0 0
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rw11::div_testd2 $cpu sym -4 -3 1 -1 0 0 0 0
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rlc log " dr==0"
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rw11::div_testd2 $cpu sym 0 0 0 0 0 1 1 1
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rw11::div_testd2 $cpu sym 1 0 0 0 0 1 1 1
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rw11::div_testd2 $cpu sym -1 0 0 0 0 1 1 1
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rlc log " test 4 quadrant basics (via testd2)"
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# dd dr q r n z v c
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rw11::div_testd2 $cpu sym 34 5 6 4 0 0 0 0
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rw11::div_testd2 $cpu sym 34 -5 -6 4 1 0 0 0
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rw11::div_testd2 $cpu sym -34 5 -6 -4 1 0 0 0
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rw11::div_testd2 $cpu sym -34 -5 6 -4 0 0 0 0
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rlc log " test 4 quadrant basics (via testdqr)"
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# dr q r
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rw11::div_testdqr $cpu sym 5 6 4;
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rw11::div_testdqr $cpu sym -5 -6 4;
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rw11::div_testdqr $cpu sym 5 -6 -4;
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rw11::div_testdqr $cpu sym -5 6 -4;
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rlc log " test q=100000 boundary cases (q = max neg value)"
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rlc log " case dd>0, dr<0 -- factor 21846"
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# dr q r
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rw11::div_testdqr $cpu sym -21846 0100000 0; # BAD-R4
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rw11::div_testdqr $cpu sym -21846 0100000 1; # BAD-R4
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rw11::div_testdqr $cpu sym -21846 0100000 21844; # BAD-R4
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rw11::div_testdqr $cpu sym -21846 0100000 21845; # BAD-R4
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rw11::div_testdqr $cpu sym -21846 0100000 21846; # v=1
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rw11::div_testdqr $cpu sym -21846 0100000 21847; # v=1
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rlc log " case dd<0, dr>0 -- factor 21846"
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rw11::div_testdqr $cpu sym 21846 0100000 0; # BAD-R4
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rw11::div_testdqr $cpu sym 21846 0100000 -1; # BAD-R4
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rw11::div_testdqr $cpu sym 21846 0100000 -21844; # BAD-R4
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rw11::div_testdqr $cpu sym 21846 0100000 -21845; # BAD-R4
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rw11::div_testdqr $cpu sym 21846 0100000 -21846; # v=1
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rw11::div_testdqr $cpu sym 21846 0100000 -21847; # v=1
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rlc log " case dd>0, dr<0 -- factor 21847"
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rw11::div_testdqr $cpu sym -21847 0100000 0; # BAD-R4
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rw11::div_testdqr $cpu sym -21847 0100000 1; # BAD-R4
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rw11::div_testdqr $cpu sym -21847 0100000 21845; # BAD-R4
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rw11::div_testdqr $cpu sym -21847 0100000 21846; # BAD-R4
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rw11::div_testdqr $cpu sym -21847 0100000 21847; # v=1
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rw11::div_testdqr $cpu sym -21847 0100000 21848; # v=1
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rlc log " case dd<0, dr>0 -- factor 21847"
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rw11::div_testdqr $cpu sym 21847 0100000 0; # BAD-R4
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rw11::div_testdqr $cpu sym 21847 0100000 -1; # BAD-R4
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rw11::div_testdqr $cpu sym 21847 0100000 -21845; # BAD-R4
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rw11::div_testdqr $cpu sym 21847 0100000 -21846; # BAD-R4
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rw11::div_testdqr $cpu sym 21847 0100000 -21847; # v=1
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rw11::div_testdqr $cpu sym 21847 0100000 -21848; # v=1
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#
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#
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rlc log " test q=077777 boundary cases (q = max pos value)"
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rlc log " case dd>0, dr>0 -- factor 21846"
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rw11::div_testdqr $cpu sym 21846 0077777 0; #
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rw11::div_testdqr $cpu sym 21846 0077777 1; #
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rw11::div_testdqr $cpu sym 21846 0077777 21844; #
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rw11::div_testdqr $cpu sym 21846 0077777 21845; #
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rw11::div_testdqr $cpu sym 21846 0077777 21846; # v=1
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rw11::div_testdqr $cpu sym 21846 0077777 21847; # v=1
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rlc log " case dd<0, dr<0 -- factor 21846"
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rw11::div_testdqr $cpu sym -21846 0077777 0; #
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rw11::div_testdqr $cpu sym -21846 0077777 -1; #
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rw11::div_testdqr $cpu sym -21846 0077777 -21844; #
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rw11::div_testdqr $cpu sym -21846 0077777 -21845; #
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rw11::div_testdqr $cpu sym -21846 0077777 -21846; # v=1
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rw11::div_testdqr $cpu sym -21846 0077777 -21847; # v=1
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rlc log " case dd>0, dr>0 -- factor 21847"
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rw11::div_testdqr $cpu sym 21847 0077777 0; #
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rw11::div_testdqr $cpu sym 21847 0077777 1; #
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rw11::div_testdqr $cpu sym 21847 0077777 21845; #
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rw11::div_testdqr $cpu sym 21847 0077777 21846; #
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rw11::div_testdqr $cpu sym 21847 0077777 21847; # v=1
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rw11::div_testdqr $cpu sym 21847 0077777 21848; # v=1
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rlc log " case dd<0, dr<0 -- factor 21847"
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rw11::div_testdqr $cpu sym -21847 0077777 0; #
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rw11::div_testdqr $cpu sym -21847 0077777 -1; #
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rw11::div_testdqr $cpu sym -21847 0077777 -21845; #
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rw11::div_testdqr $cpu sym -21847 0077777 -21846; #
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rw11::div_testdqr $cpu sym -21847 0077777 -21846; # v=1
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rw11::div_testdqr $cpu sym -21847 0077777 -21847; # v=1
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#
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#
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rlc log " test dr=100000 boundary cases (dr = max neg value)"
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rlc log " case dd<0, q>0"
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rw11::div_testdqr $cpu sym 0100000 1 0; #
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rw11::div_testdqr $cpu sym 0100000 1 -1; #
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rw11::div_testdqr $cpu sym 0100000 1 -32767; #
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rw11::div_testdqr $cpu sym 0100000 2 0; # BAD-R4
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rw11::div_testdqr $cpu sym 0100000 2 -1; #
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rw11::div_testdqr $cpu sym 0100000 2 -32767; #
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rw11::div_testdqr $cpu sym 0100000 3 0; #
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rw11::div_testdqr $cpu sym 0100000 3 -1; #
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rw11::div_testdqr $cpu sym 0100000 3 -32767; #
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rw11::div_testdqr $cpu sym 0100000 4 0; # BAD-R4
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rw11::div_testdqr $cpu sym 0100000 4 -1; #
|
| 279 |
|
|
rw11::div_testdqr $cpu sym 0100000 4 -32767; #
|
| 280 |
|
|
rw11::div_testdqr $cpu sym 0100000 6 0; # BAD-R4
|
| 281 |
|
|
rw11::div_testdqr $cpu sym 0100000 32762 0; # BAD-R4
|
| 282 |
|
|
rw11::div_testdqr $cpu sym 0100000 32764 0; # BAD-R4
|
| 283 |
|
|
rw11::div_testdqr $cpu sym 0100000 32765 0; #
|
| 284 |
|
|
rw11::div_testdqr $cpu sym 0100000 32766 0; # BAD-R4
|
| 285 |
|
|
rw11::div_testdqr $cpu sym 0100000 32766 -1; #
|
| 286 |
|
|
rw11::div_testdqr $cpu sym 0100000 32766 -32767; #
|
| 287 |
|
|
rw11::div_testdqr $cpu sym 0100000 32767 0; #
|
| 288 |
|
|
rw11::div_testdqr $cpu sym 0100000 32767 -1; #
|
| 289 |
|
|
rw11::div_testdqr $cpu sym 0100000 32767 -32767; #
|
| 290 |
|
|
rlc log " case dd>0, q<0"
|
| 291 |
|
|
rw11::div_testdqr $cpu sym 0100000 -1 0; #
|
| 292 |
|
|
rw11::div_testdqr $cpu sym 0100000 -1 1; #
|
| 293 |
|
|
rw11::div_testdqr $cpu sym 0100000 -1 32767; #
|
| 294 |
|
|
rw11::div_testdqr $cpu sym 0100000 -2 0; #
|
| 295 |
|
|
rw11::div_testdqr $cpu sym 0100000 -2 1; #
|
| 296 |
|
|
rw11::div_testdqr $cpu sym 0100000 -2 32767; #
|
| 297 |
|
|
rw11::div_testdqr $cpu sym 0100000 -32767 0; #
|
| 298 |
|
|
rw11::div_testdqr $cpu sym 0100000 -32767 1; #
|
| 299 |
|
|
rw11::div_testdqr $cpu sym 0100000 -32767 32767; #
|
| 300 |
|
|
rw11::div_testdqr $cpu sym 0100000 -32768 0; # BAD-R4
|
| 301 |
|
|
rw11::div_testdqr $cpu sym 0100000 -32768 1; # BAD-R4
|
| 302 |
|
|
rw11::div_testdqr $cpu sym 0100000 -32768 32767; # BAD-R4
|
| 303 |
|
|
#
|
| 304 |
|
|
#
|
| 305 |
|
|
rlc log " test dr=077777 boundary cases (dr = max pos value)"
|
| 306 |
|
|
rlc log " case dd>0, q>0"
|
| 307 |
|
|
rw11::div_testdqr $cpu sym 077777 1 0; #
|
| 308 |
|
|
rw11::div_testdqr $cpu sym 077777 1 1; #
|
| 309 |
|
|
rw11::div_testdqr $cpu sym 077777 1 32766; #
|
| 310 |
|
|
rw11::div_testdqr $cpu sym 077777 2 0; #
|
| 311 |
|
|
rw11::div_testdqr $cpu sym 077777 2 1; #
|
| 312 |
|
|
rw11::div_testdqr $cpu sym 077777 2 32766; #
|
| 313 |
|
|
rw11::div_testdqr $cpu sym 077777 32766 0; #
|
| 314 |
|
|
rw11::div_testdqr $cpu sym 077777 32766 1; #
|
| 315 |
|
|
rw11::div_testdqr $cpu sym 077777 32766 32766; #
|
| 316 |
|
|
rw11::div_testdqr $cpu sym 077777 32767 0; #
|
| 317 |
|
|
rw11::div_testdqr $cpu sym 077777 32767 1; #
|
| 318 |
|
|
rw11::div_testdqr $cpu sym 077777 32767 32766; #
|
| 319 |
|
|
rlc log " case dd<0, q<0"
|
| 320 |
|
|
rw11::div_testdqr $cpu sym 077777 -1 0; #
|
| 321 |
|
|
rw11::div_testdqr $cpu sym 077777 -1 -1; #
|
| 322 |
|
|
rw11::div_testdqr $cpu sym 077777 -1 -32766; #
|
| 323 |
|
|
rw11::div_testdqr $cpu sym 077777 -2 0; #
|
| 324 |
|
|
rw11::div_testdqr $cpu sym 077777 -2 -1; #
|
| 325 |
|
|
rw11::div_testdqr $cpu sym 077777 -2 -32766; #
|
| 326 |
|
|
rw11::div_testdqr $cpu sym 077777 -32767 0; #
|
| 327 |
|
|
rw11::div_testdqr $cpu sym 077777 -32767 -1; #
|
| 328 |
|
|
rw11::div_testdqr $cpu sym 077777 -32767 -32766; #
|
| 329 |
|
|
rw11::div_testdqr $cpu sym 077777 -32768 0; # BAD-R4
|
| 330 |
|
|
rw11::div_testdqr $cpu sym 077777 -32768 -1; # BAD-R4
|
| 331 |
|
|
rw11::div_testdqr $cpu sym 077777 -32768 -32766; # BAD-R4
|
| 332 |
|
|
#
|
| 333 |
|
|
#
|
| 334 |
|
|
rlc log " test dd max cases"
|
| 335 |
|
|
rlc log " case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591"
|
| 336 |
|
|
rw11::div_testdqr $cpu sym -32768 -32768 -1; #
|
| 337 |
|
|
rw11::div_testdqr $cpu sym -32768 -32768 0; # BAD-R4
|
| 338 |
|
|
rw11::div_testdqr $cpu sym -32768 -32768 1; # BAD-R4
|
| 339 |
|
|
rw11::div_testdqr $cpu sym -32768 -32768 32766; # BAD-R4
|
| 340 |
|
|
rw11::div_testdqr $cpu sym -32768 -32768 32767; # c.c BAD-R4
|
| 341 |
|
|
rw11::div_testdqr $cpu sym -32768 -32768 32768; # v=1
|
| 342 |
|
|
rw11::div_testdqr $cpu sym -32768 -32768 32769; # v=1
|
| 343 |
|
|
rlc log " case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055"
|
| 344 |
|
|
rw11::div_testdqr $cpu sym 32767 32767 -1; #
|
| 345 |
|
|
rw11::div_testdqr $cpu sym 32767 32767 0; #
|
| 346 |
|
|
rw11::div_testdqr $cpu sym 32767 32767 1; #
|
| 347 |
|
|
rw11::div_testdqr $cpu sym 32767 32767 32765; #
|
| 348 |
|
|
rw11::div_testdqr $cpu sym 32767 32767 32766; # c.c
|
| 349 |
|
|
rw11::div_testdqr $cpu sym 32767 32767 32767; # v=1
|
| 350 |
|
|
rw11::div_testdqr $cpu sym 32767 32767 32768; # v=1
|
| 351 |
|
|
rlc log " case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822"
|
| 352 |
|
|
rw11::div_testdqr $cpu sym 32767 -32768 1; #
|
| 353 |
|
|
rw11::div_testdqr $cpu sym 32767 -32768 0; # BAD-R4
|
| 354 |
|
|
rw11::div_testdqr $cpu sym 32767 -32768 -1; # BAD-R4
|
| 355 |
|
|
rw11::div_testdqr $cpu sym 32767 -32768 -32765; # BAD-R4
|
| 356 |
|
|
rw11::div_testdqr $cpu sym 32767 -32768 -32766; # c.c BAD-R4
|
| 357 |
|
|
rw11::div_testdqr $cpu sym 32767 -32768 -32767; # v=1
|
| 358 |
|
|
rw11::div_testdqr $cpu sym 32767 -32768 -32768; # v=1
|
| 359 |
|
|
rlc log " case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823"
|
| 360 |
|
|
rw11::div_testdqr $cpu sym -32768 32767 1; #
|
| 361 |
|
|
rw11::div_testdqr $cpu sym -32768 32767 0; #
|
| 362 |
|
|
rw11::div_testdqr $cpu sym -32768 32767 -1; #
|
| 363 |
|
|
rw11::div_testdqr $cpu sym -32768 32767 -32766; #
|
| 364 |
|
|
rw11::div_testdqr $cpu sym -32768 32767 -32767; # c.c
|
| 365 |
|
|
rw11::div_testdqr $cpu sym -32768 32767 -32768; # v=1
|
| 366 |
|
|
rw11::div_testdqr $cpu sym -32768 32767 -32769; # v=1
|
| 367 |
|
|
#
|
| 368 |
|
|
#
|
| 369 |
|
|
rlc log " test late div quit cases in 2 quadrant algorithm"
|
| 370 |
|
|
# dd dr q r n z v c
|
| 371 |
|
|
rw11::div_testd2 $cpu sym -32767 -1 32767 0 0 0 0 0; #
|
| 372 |
|
|
rw11::div_testd2 $cpu sym -32768 -1 0 0 0 0 1 0; #
|
| 373 |
|
|
rw11::div_testd2 $cpu sym -32769 -1 0 0 0 0 1 0; #
|
| 374 |
|
|
#
|
| 375 |
|
|
rw11::div_testd2 $cpu sym -65534 -2 32767 0 0 0 0 0; #
|
| 376 |
|
|
rw11::div_testd2 $cpu sym -65535 -2 32767 -1 0 0 0 0; #
|
| 377 |
|
|
rw11::div_testd2 $cpu sym -65536 -2 0 0 0 0 1 0; #
|
| 378 |
|
|
rw11::div_testd2 $cpu sym -65537 -2 0 0 0 0 1 0; #
|
| 379 |
|
|
#
|
| 380 |
|
|
#
|
| 381 |
|
|
rlc log " test big divident overflow cases"
|
| 382 |
|
|
# dd dr q r n z v c
|
| 383 |
|
|
rw11::div_testd2 $cpu sym 0x7fffffff 1 0 0 0 0 1 0; #
|
| 384 |
|
|
rw11::div_testd2 $cpu sym 0x7fffffff 2 0 0 0 0 1 0; #
|
| 385 |
|
|
rw11::div_testd2 $cpu sym 0x7fffffff -1 0 0 1 0 1 0; #
|
| 386 |
|
|
rw11::div_testd2 $cpu sym 0x7fffffff -2 0 0 1 0 1 0; #
|
| 387 |
|
|
rw11::div_testd2 $cpu sym 0x80000000 1 0 0 1 0 1 0; #
|
| 388 |
|
|
rw11::div_testd2 $cpu sym 0x80000000 2 0 0 1 0 1 0; #
|
| 389 |
|
|
rw11::div_testd2 $cpu sym 0x80000000 -1 0 0 0 0 1 0; #
|
| 390 |
|
|
rw11::div_testd2 $cpu sym 0x80000000 -2 0 0 0 0 1 0; #
|
