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# $Id: test_regs.tcl 785 2016-07-10 12:22:41Z mueller $
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#
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# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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#
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-07-10 785 1.1 add memory test (touch evenly distributed addr)
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# 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat)
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#
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package provide tst_sram 1.0
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package require rutiltpp
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package require rutil
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package require rlink
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namespace eval tst_sram {
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#
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# test_regs: Test registers: mdi*,mdo*,maddr*,mcmd,mblk,sblk*
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# and saddr,slim,sblk*
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#
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proc test_regs {} {
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#
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set errcnt 0
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rlc errcnt -clear
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#
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rlc log "tst_sram::test_regs ---------------------------------------------"
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rlc log " init: reset via init, clear sfail ect"
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rlc exec -init sr.mdih 0x0003; # reset MEM,SEQ
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#
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#-------------------------------------------------------------------------
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rlc log " test 1a: test mdi* ,maddr*"
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rlc exec \
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-wreg sr.mdih 0x5555 \
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-wreg sr.mdil 0xaaaa \
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-wreg sr.maddrh 0x0001 \
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-wreg sr.maddrl 0xcccc \
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-rreg sr.mdih -edata 0x5555 \
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-rreg sr.mdil -edata 0xaaaa \
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-rreg sr.maddrh -edata 0x0001 \
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-rreg sr.maddrl -edata 0xcccc
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#
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#-------------------------------------------------------------------------
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rlc log " test 1b: test maddrh range"
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set maddrh_max [expr {[iswide] ? 0x3f : 0x03}]
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rlc exec \
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-wreg sr.maddrh 0xffff \
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-rreg sr.maddrh -edata $maddrh_max
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#
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#-------------------------------------------------------------------------
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rlc log " test 2: test direct memory write/read via mcmd"
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# write mem(0) = 0xdeadbeaf; mem(1)=a5a55a5a
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rlc exec \
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-wreg sr.maddrh 0x0000 \
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-wreg sr.maddrl 0x0000 \
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-wreg sr.mdih 0xdead \
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-wreg sr.mdil 0xbeaf \
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-wreg sr.mcmd [regbld tst_sram::MCMD we {be 0xf}] \
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-wreg sr.maddrl 0x0001 \
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-wreg sr.mdih 0xa5a5 \
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-wreg sr.mdil 0x5a5a \
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-wreg sr.mcmd [regbld tst_sram::MCMD we {be 0xf}]
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# read back
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rlc exec \
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-wreg sr.maddrl 0x0000 \
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-wreg sr.mcmd [regbld tst_sram::MCMD {be 0xf}] \
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-rreg sr.mdoh -edata 0xdead \
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-rreg sr.mdol -edata 0xbeaf \
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-wreg sr.maddrl 0x0001 \
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-wreg sr.mcmd [regbld tst_sram::MCMD {be 0xf}] \
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-rreg sr.mdoh -edata 0xa5a5 \
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-rreg sr.mdol -edata 0x5a5a
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# check that mdi* unchanged (value from last write)
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rlc exec \
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-rreg sr.mdih -edata 0xa5a5 \
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-rreg sr.mdil -edata 0x5a5a
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# verify that mcmd write only
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rlc exec -rreg sr.mcmd -estaterr; # expect err on read
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#
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#-------------------------------------------------------------------------
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rlc log " test 3: test block write/read via mblk"
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# write 8 longwords, check maddrl incremented
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rlc exec \
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-wreg sr.maddrh 0x0000 \
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-wreg sr.maddrl 0x0010 \
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-wblk sr.mblk {0x3020 0x1000 \
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0x3121 0x1101 \
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0x3222 0x1202 \
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0x3323 0x1303 \
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0x3424 0x1404 \
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0x3525 0x1505 \
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0x3626 0x1606 \
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0x3727 0x1707} \
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-rreg sr.maddrh -edata 0x0000 \
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-rreg sr.maddrl -edata 0x0018
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# read 8 longwords, check maddrl incremented
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rlc exec \
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-wreg sr.maddrh 0x0000 \
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-wreg sr.maddrl 0x0010 \
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-rblk sr.mblk 16 -edata {0x3020 0x1000 \
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0x3121 0x1101 \
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0x3222 0x1202 \
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0x3323 0x1303 \
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0x3424 0x1404 \
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0x3525 0x1505 \
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0x3626 0x1606 \
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0x3727 0x1707} \
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-rreg sr.maddrh -edata 0x0000 \
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-rreg sr.maddrl -edata 0x0018
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#
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#-------------------------------------------------------------------------
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rlc log " test 4: mcmd: ld,inc and be functionality"
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# use memory as setup by previous test
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# overwrite bytes 12(0001)=42, 13(0010)=53, 14(0100)=64, 15(1000)=75
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rlc exec \
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-wreg sr.maddrh 0x0003 \
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-wreg sr.maddrl 0x0012 \
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-wreg sr.mdih 0xffff \
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-wreg sr.mdil 0xff42 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0x1} {addrh 0x0}] \
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-wreg sr.mdil 0x53ff \
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-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x2} ] \
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-wreg sr.mdih 0xff64 \
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-wreg sr.mdil 0xffff \
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-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x4} ] \
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-wreg sr.mdih 0x75ff \
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-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x8} ]
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# check load maddrh and increment of maddrl; read back and check
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rlc exec \
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-rreg sr.maddrh -edata 0x0000 \
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-rreg sr.maddrl -edata 0x0016 \
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-wreg sr.maddrl 0x0010 \
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-rblk sr.mblk 16 -edata {0x3020 0x1000 \
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0x3121 0x1101 \
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0x3222 0x1242 \
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0x3323 0x5303 \
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0x3464 0x1404 \
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0x7525 0x1505 \
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0x3626 0x1606 \
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0x3727 0x1707}
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#
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#-------------------------------------------------------------------------
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rlc log " test 5: test saddr,slim,sblk,sblkc,sblkd"
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# write/read saddr/slim
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rlc exec \
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-wreg sr.slim 0x0123 \
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-wreg sr.saddr 0x0345 \
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-rreg sr.slim -edata 0x0123 \
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-rreg sr.saddr -edata 0x0345
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# sblk write of 8 lines, check saddr incremented
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rlc exec \
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-wreg sr.saddr 0x0000 \
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-wblk sr.sblk {0x0300 0x0200 0x0100 0x0000 \
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0x0301 0x0201 0x0101 0x0001 \
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0x0302 0x0202 0x0102 0x0002 \
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0x0303 0x0203 0x0103 0x0003 \
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0x0304 0x0204 0x0104 0x0004 \
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0x0305 0x0205 0x0105 0x0005 \
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0x0306 0x0206 0x0106 0x0006 \
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0x0307 0x0207 0x0107 0x0007 } \
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-rreg sr.saddr -edata 0x0008
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# sblk read back
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rlc exec \
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-wreg sr.saddr 0x0000 \
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-rblk sr.sblk 32 -edata {0x0300 0x0200 0x0100 0x0000 \
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0x0301 0x0201 0x0101 0x0001 \
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0x0302 0x0202 0x0102 0x0002 \
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0x0303 0x0203 0x0103 0x0003 \
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0x0304 0x0204 0x0104 0x0004 \
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0x0305 0x0205 0x0105 0x0005 \
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0x0306 0x0206 0x0106 0x0006 \
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0x0307 0x0207 0x0107 0x0007 } \
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-rreg sr.saddr -edata 0x0008
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# sblkc (over-)write of 4 lines (1-4)
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rlc exec \
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-wreg sr.saddr 0x0001 \
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-wblk sr.sblkc {0x1301 0x1201 \
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0x1302 0x1202 \
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0x1303 0x1203 \
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0x1304 0x1204 } \
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-rreg sr.saddr -edata 0x0005
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# sblkd (over-)write of 4 lines (3-6)
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rlc exec \
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-wreg sr.saddr 0x0003 \
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-wblk sr.sblkd {0x2103 0x2003 \
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0x2104 0x2004 \
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0x2105 0x2005 \
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0x2106 0x2006 } \
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-rreg sr.saddr -edata 0x0007
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# sblk read back of all 8 lines, verify c and d updates
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rlc exec \
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-wreg sr.saddr 0x0000 \
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-rblk sr.sblk 32 -edata {0x0300 0x0200 0x0100 0x0000 \
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0x1301 0x1201 0x0101 0x0001 \
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0x1302 0x1202 0x0102 0x0002 \
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0x1303 0x1203 0x2103 0x2003 \
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0x1304 0x1204 0x2104 0x2004 \
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0x0305 0x0205 0x2105 0x2005 \
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0x0306 0x0206 0x2106 0x2006 \
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0x0307 0x0207 0x0107 0x0007} \
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-rreg sr.saddr -edata 0x0008
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# sblkc read back of all 8 lines
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rlc exec \
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-wreg sr.saddr 0x0000 \
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-rblk sr.sblkc 16 -edata {0x0300 0x0200 \
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0x1301 0x1201 \
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0x1302 0x1202 \
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0x1303 0x1203 \
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0x1304 0x1204 \
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0x0305 0x0205 \
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0x0306 0x0206 \
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0x0307 0x0207} \
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-rreg sr.saddr -edata 0x0008
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# sblkd read back of all 8 lines
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rlc exec \
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-wreg sr.saddr 0x0000 \
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-rblk sr.sblkd 16 -edata {0x0100 0x0000 \
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0x0101 0x0001 \
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0x0102 0x0002 \
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0x2103 0x2003 \
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0x2104 0x2004 \
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0x2105 0x2005 \
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0x2106 0x2006 \
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0x0107 0x0007} \
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-rreg sr.saddr -edata 0x0008
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#
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#-------------------------------------------------------------------------
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rlc log " test 5: test sstat bits"
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set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
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rlc exec \
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-wreg sr.sstat 0 \
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-rreg sr.sstat -edata 0 $sm \
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-wreg sr.sstat [regbld tst_sram::SSTAT veri ] \
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-rreg sr.sstat -edata [regbld tst_sram::SSTAT veri ] $sm \
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-wreg sr.sstat [regbld tst_sram::SSTAT xora ] \
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-rreg sr.sstat -edata [regbld tst_sram::SSTAT xora ] $sm \
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-wreg sr.sstat [regbld tst_sram::SSTAT xord ] \
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-rreg sr.sstat -edata [regbld tst_sram::SSTAT xord ] $sm \
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-wreg sr.sstat [regbld tst_sram::SSTAT loop ] \
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-rreg sr.sstat -edata [regbld tst_sram::SSTAT loop ] $sm \
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-wreg sr.sstat [regbld tst_sram::SSTAT wloop] \
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-rreg sr.sstat -edata [regbld tst_sram::SSTAT wloop] $sm \
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-wreg sr.sstat [regbld tst_sram::SSTAT wswap] \
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-rreg sr.sstat -edata [regbld tst_sram::SSTAT wswap] $sm
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#
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#-------------------------------------------------------------------------
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rlc log " test 6: test memory (touch 5(+5) evenly spaced addresses)"
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# writes
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# 18bit: 0x000000 0x010001 0x020002 0x030003 0x03ffff
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rlc exec \
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-wreg sr.mdih 0x5500 \
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-wreg sr.mdil 0xaa00 \
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-wreg sr.maddrl 0x0000 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x00}] \
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-wreg sr.mdih 0x5501 \
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-wreg sr.mdil 0xaa01 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x01}] \
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-wreg sr.mdih 0x5502 \
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-wreg sr.mdil 0xaa02 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x02}] \
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-wreg sr.mdih 0x5503 \
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-wreg sr.mdil 0xaa03 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x03}] \
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-rreg sr.maddrl -edata 0x0004 \
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-wreg sr.mdih 0x5504 \
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-wreg sr.mdil 0xaa04 \
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-wreg sr.maddrl 0xffff \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x03}]
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# 22bit: 0x040000 0x100001 0x200002 0x300003 0x3fffff
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if {[iswide]} {
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rlc exec \
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-wreg sr.mdih 0xa500 \
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-wreg sr.mdil 0x5a00 \
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-wreg sr.maddrl 0x0000 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x04}] \
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-wreg sr.mdih 0x5a01 \
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-wreg sr.mdil 0x5a01 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x10}] \
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-wreg sr.mdih 0x5a02 \
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-wreg sr.mdil 0x5a02 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x20}] \
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-wreg sr.mdih 0x5a03 \
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-wreg sr.mdil 0x5a03 \
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-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x30}] \
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-rreg sr.maddrl -edata 0x0004 \
|
295 |
|
|
-wreg sr.mdih 0x5a04 \
|
296 |
|
|
-wreg sr.mdil 0x5a04 \
|
297 |
|
|
-wreg sr.maddrl 0xffff \
|
298 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x3f}]
|
299 |
|
|
}
|
300 |
|
|
# reads
|
301 |
|
|
rlc exec \
|
302 |
|
|
-wreg sr.maddrl 0x0000 \
|
303 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x00}] \
|
304 |
|
|
-rreg sr.mdoh -edata 0x5500 \
|
305 |
|
|
-rreg sr.mdol -edata 0xaa00 \
|
306 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x01}] \
|
307 |
|
|
-rreg sr.mdoh -edata 0x5501 \
|
308 |
|
|
-rreg sr.mdol -edata 0xaa01 \
|
309 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x02}] \
|
310 |
|
|
-rreg sr.mdoh -edata 0x5502 \
|
311 |
|
|
-rreg sr.mdol -edata 0xaa02 \
|
312 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x03}] \
|
313 |
|
|
-rreg sr.mdoh -edata 0x5503 \
|
314 |
|
|
-rreg sr.mdol -edata 0xaa03 \
|
315 |
|
|
-rreg sr.maddrl -edata 0x0004 \
|
316 |
|
|
-wreg sr.maddrl 0xffff \
|
317 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x03}] \
|
318 |
|
|
-rreg sr.mdoh -edata 0x5504 \
|
319 |
|
|
-rreg sr.mdol -edata 0xaa04
|
320 |
|
|
if {[iswide]} {
|
321 |
|
|
rlc exec \
|
322 |
|
|
-wreg sr.maddrl 0x0000 \
|
323 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x04}] \
|
324 |
|
|
-rreg sr.mdoh -edata 0xa500 \
|
325 |
|
|
-rreg sr.mdol -edata 0x5a00 \
|
326 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x10}] \
|
327 |
|
|
-rreg sr.mdoh -edata 0x5a01 \
|
328 |
|
|
-rreg sr.mdol -edata 0x5a01 \
|
329 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x20}] \
|
330 |
|
|
-rreg sr.mdoh -edata 0x5a02 \
|
331 |
|
|
-rreg sr.mdol -edata 0x5a02 \
|
332 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x30}] \
|
333 |
|
|
-rreg sr.mdoh -edata 0x5a03 \
|
334 |
|
|
-rreg sr.mdol -edata 0x5a03 \
|
335 |
|
|
-rreg sr.maddrl -edata 0x0004 \
|
336 |
|
|
-wreg sr.maddrl 0xffff \
|
337 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x3f}] \
|
338 |
|
|
-rreg sr.mdoh -edata 0x5a04 \
|
339 |
|
|
-rreg sr.mdol -edata 0x5a04
|
340 |
|
|
}
|
341 |
|
|
#
|
342 |
|
|
#-------------------------------------------------------------------------
|
343 |
|
|
incr errcnt [rlc errcnt -clear]
|
344 |
|
|
return $errcnt
|
345 |
|
|
}
|
346 |
|
|
}
|