| 1 |
37 |
wfjm |
# $Id: test_regs.tcl 785 2016-07-10 12:22:41Z mueller $
|
| 2 |
|
|
#
|
| 3 |
|
|
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
| 4 |
|
|
#
|
| 5 |
|
|
# This program is free software; you may redistribute and/or modify it under
|
| 6 |
|
|
# the terms of the GNU General Public License as published by the Free
|
| 7 |
|
|
# Software Foundation, either version 2, or at your option any later version.
|
| 8 |
|
|
#
|
| 9 |
|
|
# This program is distributed in the hope that it will be useful, but
|
| 10 |
|
|
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
| 11 |
|
|
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 12 |
|
|
# for complete details.
|
| 13 |
|
|
#
|
| 14 |
|
|
# Revision History:
|
| 15 |
|
|
# Date Rev Version Comment
|
| 16 |
|
|
# 2016-07-10 785 1.1 add memory test (touch evenly distributed addr)
|
| 17 |
|
|
# 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat)
|
| 18 |
|
|
#
|
| 19 |
|
|
|
| 20 |
|
|
package provide tst_sram 1.0
|
| 21 |
|
|
|
| 22 |
|
|
package require rutiltpp
|
| 23 |
|
|
package require rutil
|
| 24 |
|
|
package require rlink
|
| 25 |
|
|
|
| 26 |
|
|
namespace eval tst_sram {
|
| 27 |
|
|
#
|
| 28 |
|
|
# test_regs: Test registers: mdi*,mdo*,maddr*,mcmd,mblk,sblk*
|
| 29 |
|
|
# and saddr,slim,sblk*
|
| 30 |
|
|
#
|
| 31 |
|
|
proc test_regs {} {
|
| 32 |
|
|
#
|
| 33 |
|
|
set errcnt 0
|
| 34 |
|
|
rlc errcnt -clear
|
| 35 |
|
|
#
|
| 36 |
|
|
rlc log "tst_sram::test_regs ---------------------------------------------"
|
| 37 |
|
|
rlc log " init: reset via init, clear sfail ect"
|
| 38 |
|
|
rlc exec -init sr.mdih 0x0003; # reset MEM,SEQ
|
| 39 |
|
|
#
|
| 40 |
|
|
#-------------------------------------------------------------------------
|
| 41 |
|
|
rlc log " test 1a: test mdi* ,maddr*"
|
| 42 |
|
|
rlc exec \
|
| 43 |
|
|
-wreg sr.mdih 0x5555 \
|
| 44 |
|
|
-wreg sr.mdil 0xaaaa \
|
| 45 |
|
|
-wreg sr.maddrh 0x0001 \
|
| 46 |
|
|
-wreg sr.maddrl 0xcccc \
|
| 47 |
|
|
-rreg sr.mdih -edata 0x5555 \
|
| 48 |
|
|
-rreg sr.mdil -edata 0xaaaa \
|
| 49 |
|
|
-rreg sr.maddrh -edata 0x0001 \
|
| 50 |
|
|
-rreg sr.maddrl -edata 0xcccc
|
| 51 |
|
|
#
|
| 52 |
|
|
#-------------------------------------------------------------------------
|
| 53 |
|
|
rlc log " test 1b: test maddrh range"
|
| 54 |
|
|
set maddrh_max [expr {[iswide] ? 0x3f : 0x03}]
|
| 55 |
|
|
rlc exec \
|
| 56 |
|
|
-wreg sr.maddrh 0xffff \
|
| 57 |
|
|
-rreg sr.maddrh -edata $maddrh_max
|
| 58 |
|
|
#
|
| 59 |
|
|
#-------------------------------------------------------------------------
|
| 60 |
|
|
rlc log " test 2: test direct memory write/read via mcmd"
|
| 61 |
|
|
# write mem(0) = 0xdeadbeaf; mem(1)=a5a55a5a
|
| 62 |
|
|
rlc exec \
|
| 63 |
|
|
-wreg sr.maddrh 0x0000 \
|
| 64 |
|
|
-wreg sr.maddrl 0x0000 \
|
| 65 |
|
|
-wreg sr.mdih 0xdead \
|
| 66 |
|
|
-wreg sr.mdil 0xbeaf \
|
| 67 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD we {be 0xf}] \
|
| 68 |
|
|
-wreg sr.maddrl 0x0001 \
|
| 69 |
|
|
-wreg sr.mdih 0xa5a5 \
|
| 70 |
|
|
-wreg sr.mdil 0x5a5a \
|
| 71 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD we {be 0xf}]
|
| 72 |
|
|
# read back
|
| 73 |
|
|
rlc exec \
|
| 74 |
|
|
-wreg sr.maddrl 0x0000 \
|
| 75 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD {be 0xf}] \
|
| 76 |
|
|
-rreg sr.mdoh -edata 0xdead \
|
| 77 |
|
|
-rreg sr.mdol -edata 0xbeaf \
|
| 78 |
|
|
-wreg sr.maddrl 0x0001 \
|
| 79 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD {be 0xf}] \
|
| 80 |
|
|
-rreg sr.mdoh -edata 0xa5a5 \
|
| 81 |
|
|
-rreg sr.mdol -edata 0x5a5a
|
| 82 |
|
|
# check that mdi* unchanged (value from last write)
|
| 83 |
|
|
rlc exec \
|
| 84 |
|
|
-rreg sr.mdih -edata 0xa5a5 \
|
| 85 |
|
|
-rreg sr.mdil -edata 0x5a5a
|
| 86 |
|
|
# verify that mcmd write only
|
| 87 |
|
|
rlc exec -rreg sr.mcmd -estaterr; # expect err on read
|
| 88 |
|
|
#
|
| 89 |
|
|
#-------------------------------------------------------------------------
|
| 90 |
|
|
rlc log " test 3: test block write/read via mblk"
|
| 91 |
|
|
# write 8 longwords, check maddrl incremented
|
| 92 |
|
|
rlc exec \
|
| 93 |
|
|
-wreg sr.maddrh 0x0000 \
|
| 94 |
|
|
-wreg sr.maddrl 0x0010 \
|
| 95 |
|
|
-wblk sr.mblk {0x3020 0x1000 \
|
| 96 |
|
|
0x3121 0x1101 \
|
| 97 |
|
|
0x3222 0x1202 \
|
| 98 |
|
|
0x3323 0x1303 \
|
| 99 |
|
|
0x3424 0x1404 \
|
| 100 |
|
|
0x3525 0x1505 \
|
| 101 |
|
|
0x3626 0x1606 \
|
| 102 |
|
|
0x3727 0x1707} \
|
| 103 |
|
|
-rreg sr.maddrh -edata 0x0000 \
|
| 104 |
|
|
-rreg sr.maddrl -edata 0x0018
|
| 105 |
|
|
# read 8 longwords, check maddrl incremented
|
| 106 |
|
|
rlc exec \
|
| 107 |
|
|
-wreg sr.maddrh 0x0000 \
|
| 108 |
|
|
-wreg sr.maddrl 0x0010 \
|
| 109 |
|
|
-rblk sr.mblk 16 -edata {0x3020 0x1000 \
|
| 110 |
|
|
0x3121 0x1101 \
|
| 111 |
|
|
0x3222 0x1202 \
|
| 112 |
|
|
0x3323 0x1303 \
|
| 113 |
|
|
0x3424 0x1404 \
|
| 114 |
|
|
0x3525 0x1505 \
|
| 115 |
|
|
0x3626 0x1606 \
|
| 116 |
|
|
0x3727 0x1707} \
|
| 117 |
|
|
-rreg sr.maddrh -edata 0x0000 \
|
| 118 |
|
|
-rreg sr.maddrl -edata 0x0018
|
| 119 |
|
|
#
|
| 120 |
|
|
#-------------------------------------------------------------------------
|
| 121 |
|
|
rlc log " test 4: mcmd: ld,inc and be functionality"
|
| 122 |
|
|
# use memory as setup by previous test
|
| 123 |
|
|
# overwrite bytes 12(0001)=42, 13(0010)=53, 14(0100)=64, 15(1000)=75
|
| 124 |
|
|
rlc exec \
|
| 125 |
|
|
-wreg sr.maddrh 0x0003 \
|
| 126 |
|
|
-wreg sr.maddrl 0x0012 \
|
| 127 |
|
|
-wreg sr.mdih 0xffff \
|
| 128 |
|
|
-wreg sr.mdil 0xff42 \
|
| 129 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0x1} {addrh 0x0}] \
|
| 130 |
|
|
-wreg sr.mdil 0x53ff \
|
| 131 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x2} ] \
|
| 132 |
|
|
-wreg sr.mdih 0xff64 \
|
| 133 |
|
|
-wreg sr.mdil 0xffff \
|
| 134 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x4} ] \
|
| 135 |
|
|
-wreg sr.mdih 0x75ff \
|
| 136 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x8} ]
|
| 137 |
|
|
# check load maddrh and increment of maddrl; read back and check
|
| 138 |
|
|
rlc exec \
|
| 139 |
|
|
-rreg sr.maddrh -edata 0x0000 \
|
| 140 |
|
|
-rreg sr.maddrl -edata 0x0016 \
|
| 141 |
|
|
-wreg sr.maddrl 0x0010 \
|
| 142 |
|
|
-rblk sr.mblk 16 -edata {0x3020 0x1000 \
|
| 143 |
|
|
0x3121 0x1101 \
|
| 144 |
|
|
0x3222 0x1242 \
|
| 145 |
|
|
0x3323 0x5303 \
|
| 146 |
|
|
0x3464 0x1404 \
|
| 147 |
|
|
0x7525 0x1505 \
|
| 148 |
|
|
0x3626 0x1606 \
|
| 149 |
|
|
0x3727 0x1707}
|
| 150 |
|
|
#
|
| 151 |
|
|
#-------------------------------------------------------------------------
|
| 152 |
|
|
rlc log " test 5: test saddr,slim,sblk,sblkc,sblkd"
|
| 153 |
|
|
# write/read saddr/slim
|
| 154 |
|
|
rlc exec \
|
| 155 |
|
|
-wreg sr.slim 0x0123 \
|
| 156 |
|
|
-wreg sr.saddr 0x0345 \
|
| 157 |
|
|
-rreg sr.slim -edata 0x0123 \
|
| 158 |
|
|
-rreg sr.saddr -edata 0x0345
|
| 159 |
|
|
# sblk write of 8 lines, check saddr incremented
|
| 160 |
|
|
rlc exec \
|
| 161 |
|
|
-wreg sr.saddr 0x0000 \
|
| 162 |
|
|
-wblk sr.sblk {0x0300 0x0200 0x0100 0x0000 \
|
| 163 |
|
|
0x0301 0x0201 0x0101 0x0001 \
|
| 164 |
|
|
0x0302 0x0202 0x0102 0x0002 \
|
| 165 |
|
|
0x0303 0x0203 0x0103 0x0003 \
|
| 166 |
|
|
0x0304 0x0204 0x0104 0x0004 \
|
| 167 |
|
|
0x0305 0x0205 0x0105 0x0005 \
|
| 168 |
|
|
0x0306 0x0206 0x0106 0x0006 \
|
| 169 |
|
|
0x0307 0x0207 0x0107 0x0007 } \
|
| 170 |
|
|
-rreg sr.saddr -edata 0x0008
|
| 171 |
|
|
# sblk read back
|
| 172 |
|
|
rlc exec \
|
| 173 |
|
|
-wreg sr.saddr 0x0000 \
|
| 174 |
|
|
-rblk sr.sblk 32 -edata {0x0300 0x0200 0x0100 0x0000 \
|
| 175 |
|
|
0x0301 0x0201 0x0101 0x0001 \
|
| 176 |
|
|
0x0302 0x0202 0x0102 0x0002 \
|
| 177 |
|
|
0x0303 0x0203 0x0103 0x0003 \
|
| 178 |
|
|
0x0304 0x0204 0x0104 0x0004 \
|
| 179 |
|
|
0x0305 0x0205 0x0105 0x0005 \
|
| 180 |
|
|
0x0306 0x0206 0x0106 0x0006 \
|
| 181 |
|
|
0x0307 0x0207 0x0107 0x0007 } \
|
| 182 |
|
|
-rreg sr.saddr -edata 0x0008
|
| 183 |
|
|
# sblkc (over-)write of 4 lines (1-4)
|
| 184 |
|
|
rlc exec \
|
| 185 |
|
|
-wreg sr.saddr 0x0001 \
|
| 186 |
|
|
-wblk sr.sblkc {0x1301 0x1201 \
|
| 187 |
|
|
0x1302 0x1202 \
|
| 188 |
|
|
0x1303 0x1203 \
|
| 189 |
|
|
0x1304 0x1204 } \
|
| 190 |
|
|
-rreg sr.saddr -edata 0x0005
|
| 191 |
|
|
# sblkd (over-)write of 4 lines (3-6)
|
| 192 |
|
|
rlc exec \
|
| 193 |
|
|
-wreg sr.saddr 0x0003 \
|
| 194 |
|
|
-wblk sr.sblkd {0x2103 0x2003 \
|
| 195 |
|
|
0x2104 0x2004 \
|
| 196 |
|
|
0x2105 0x2005 \
|
| 197 |
|
|
0x2106 0x2006 } \
|
| 198 |
|
|
-rreg sr.saddr -edata 0x0007
|
| 199 |
|
|
# sblk read back of all 8 lines, verify c and d updates
|
| 200 |
|
|
rlc exec \
|
| 201 |
|
|
-wreg sr.saddr 0x0000 \
|
| 202 |
|
|
-rblk sr.sblk 32 -edata {0x0300 0x0200 0x0100 0x0000 \
|
| 203 |
|
|
0x1301 0x1201 0x0101 0x0001 \
|
| 204 |
|
|
0x1302 0x1202 0x0102 0x0002 \
|
| 205 |
|
|
0x1303 0x1203 0x2103 0x2003 \
|
| 206 |
|
|
0x1304 0x1204 0x2104 0x2004 \
|
| 207 |
|
|
0x0305 0x0205 0x2105 0x2005 \
|
| 208 |
|
|
0x0306 0x0206 0x2106 0x2006 \
|
| 209 |
|
|
0x0307 0x0207 0x0107 0x0007} \
|
| 210 |
|
|
-rreg sr.saddr -edata 0x0008
|
| 211 |
|
|
# sblkc read back of all 8 lines
|
| 212 |
|
|
rlc exec \
|
| 213 |
|
|
-wreg sr.saddr 0x0000 \
|
| 214 |
|
|
-rblk sr.sblkc 16 -edata {0x0300 0x0200 \
|
| 215 |
|
|
0x1301 0x1201 \
|
| 216 |
|
|
0x1302 0x1202 \
|
| 217 |
|
|
0x1303 0x1203 \
|
| 218 |
|
|
0x1304 0x1204 \
|
| 219 |
|
|
0x0305 0x0205 \
|
| 220 |
|
|
0x0306 0x0206 \
|
| 221 |
|
|
0x0307 0x0207} \
|
| 222 |
|
|
-rreg sr.saddr -edata 0x0008
|
| 223 |
|
|
# sblkd read back of all 8 lines
|
| 224 |
|
|
rlc exec \
|
| 225 |
|
|
-wreg sr.saddr 0x0000 \
|
| 226 |
|
|
-rblk sr.sblkd 16 -edata {0x0100 0x0000 \
|
| 227 |
|
|
0x0101 0x0001 \
|
| 228 |
|
|
0x0102 0x0002 \
|
| 229 |
|
|
0x2103 0x2003 \
|
| 230 |
|
|
0x2104 0x2004 \
|
| 231 |
|
|
0x2105 0x2005 \
|
| 232 |
|
|
0x2106 0x2006 \
|
| 233 |
|
|
0x0107 0x0007} \
|
| 234 |
|
|
-rreg sr.saddr -edata 0x0008
|
| 235 |
|
|
#
|
| 236 |
|
|
#-------------------------------------------------------------------------
|
| 237 |
|
|
rlc log " test 5: test sstat bits"
|
| 238 |
|
|
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
|
| 239 |
|
|
rlc exec \
|
| 240 |
|
|
-wreg sr.sstat 0 \
|
| 241 |
|
|
-rreg sr.sstat -edata 0 $sm \
|
| 242 |
|
|
-wreg sr.sstat [regbld tst_sram::SSTAT veri ] \
|
| 243 |
|
|
-rreg sr.sstat -edata [regbld tst_sram::SSTAT veri ] $sm \
|
| 244 |
|
|
-wreg sr.sstat [regbld tst_sram::SSTAT xora ] \
|
| 245 |
|
|
-rreg sr.sstat -edata [regbld tst_sram::SSTAT xora ] $sm \
|
| 246 |
|
|
-wreg sr.sstat [regbld tst_sram::SSTAT xord ] \
|
| 247 |
|
|
-rreg sr.sstat -edata [regbld tst_sram::SSTAT xord ] $sm \
|
| 248 |
|
|
-wreg sr.sstat [regbld tst_sram::SSTAT loop ] \
|
| 249 |
|
|
-rreg sr.sstat -edata [regbld tst_sram::SSTAT loop ] $sm \
|
| 250 |
|
|
-wreg sr.sstat [regbld tst_sram::SSTAT wloop] \
|
| 251 |
|
|
-rreg sr.sstat -edata [regbld tst_sram::SSTAT wloop] $sm \
|
| 252 |
|
|
-wreg sr.sstat [regbld tst_sram::SSTAT wswap] \
|
| 253 |
|
|
-rreg sr.sstat -edata [regbld tst_sram::SSTAT wswap] $sm
|
| 254 |
|
|
#
|
| 255 |
|
|
#-------------------------------------------------------------------------
|
| 256 |
|
|
rlc log " test 6: test memory (touch 5(+5) evenly spaced addresses)"
|
| 257 |
|
|
# writes
|
| 258 |
|
|
# 18bit: 0x000000 0x010001 0x020002 0x030003 0x03ffff
|
| 259 |
|
|
rlc exec \
|
| 260 |
|
|
-wreg sr.mdih 0x5500 \
|
| 261 |
|
|
-wreg sr.mdil 0xaa00 \
|
| 262 |
|
|
-wreg sr.maddrl 0x0000 \
|
| 263 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x00}] \
|
| 264 |
|
|
-wreg sr.mdih 0x5501 \
|
| 265 |
|
|
-wreg sr.mdil 0xaa01 \
|
| 266 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x01}] \
|
| 267 |
|
|
-wreg sr.mdih 0x5502 \
|
| 268 |
|
|
-wreg sr.mdil 0xaa02 \
|
| 269 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x02}] \
|
| 270 |
|
|
-wreg sr.mdih 0x5503 \
|
| 271 |
|
|
-wreg sr.mdil 0xaa03 \
|
| 272 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x03}] \
|
| 273 |
|
|
-rreg sr.maddrl -edata 0x0004 \
|
| 274 |
|
|
-wreg sr.mdih 0x5504 \
|
| 275 |
|
|
-wreg sr.mdil 0xaa04 \
|
| 276 |
|
|
-wreg sr.maddrl 0xffff \
|
| 277 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x03}]
|
| 278 |
|
|
# 22bit: 0x040000 0x100001 0x200002 0x300003 0x3fffff
|
| 279 |
|
|
if {[iswide]} {
|
| 280 |
|
|
rlc exec \
|
| 281 |
|
|
-wreg sr.mdih 0xa500 \
|
| 282 |
|
|
-wreg sr.mdil 0x5a00 \
|
| 283 |
|
|
-wreg sr.maddrl 0x0000 \
|
| 284 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x04}] \
|
| 285 |
|
|
-wreg sr.mdih 0x5a01 \
|
| 286 |
|
|
-wreg sr.mdil 0x5a01 \
|
| 287 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x10}] \
|
| 288 |
|
|
-wreg sr.mdih 0x5a02 \
|
| 289 |
|
|
-wreg sr.mdil 0x5a02 \
|
| 290 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x20}] \
|
| 291 |
|
|
-wreg sr.mdih 0x5a03 \
|
| 292 |
|
|
-wreg sr.mdil 0x5a03 \
|
| 293 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x30}] \
|
| 294 |
|
|
-rreg sr.maddrl -edata 0x0004 \
|
| 295 |
|
|
-wreg sr.mdih 0x5a04 \
|
| 296 |
|
|
-wreg sr.mdil 0x5a04 \
|
| 297 |
|
|
-wreg sr.maddrl 0xffff \
|
| 298 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x3f}]
|
| 299 |
|
|
}
|
| 300 |
|
|
# reads
|
| 301 |
|
|
rlc exec \
|
| 302 |
|
|
-wreg sr.maddrl 0x0000 \
|
| 303 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x00}] \
|
| 304 |
|
|
-rreg sr.mdoh -edata 0x5500 \
|
| 305 |
|
|
-rreg sr.mdol -edata 0xaa00 \
|
| 306 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x01}] \
|
| 307 |
|
|
-rreg sr.mdoh -edata 0x5501 \
|
| 308 |
|
|
-rreg sr.mdol -edata 0xaa01 \
|
| 309 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x02}] \
|
| 310 |
|
|
-rreg sr.mdoh -edata 0x5502 \
|
| 311 |
|
|
-rreg sr.mdol -edata 0xaa02 \
|
| 312 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x03}] \
|
| 313 |
|
|
-rreg sr.mdoh -edata 0x5503 \
|
| 314 |
|
|
-rreg sr.mdol -edata 0xaa03 \
|
| 315 |
|
|
-rreg sr.maddrl -edata 0x0004 \
|
| 316 |
|
|
-wreg sr.maddrl 0xffff \
|
| 317 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x03}] \
|
| 318 |
|
|
-rreg sr.mdoh -edata 0x5504 \
|
| 319 |
|
|
-rreg sr.mdol -edata 0xaa04
|
| 320 |
|
|
if {[iswide]} {
|
| 321 |
|
|
rlc exec \
|
| 322 |
|
|
-wreg sr.maddrl 0x0000 \
|
| 323 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x04}] \
|
| 324 |
|
|
-rreg sr.mdoh -edata 0xa500 \
|
| 325 |
|
|
-rreg sr.mdol -edata 0x5a00 \
|
| 326 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x10}] \
|
| 327 |
|
|
-rreg sr.mdoh -edata 0x5a01 \
|
| 328 |
|
|
-rreg sr.mdol -edata 0x5a01 \
|
| 329 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x20}] \
|
| 330 |
|
|
-rreg sr.mdoh -edata 0x5a02 \
|
| 331 |
|
|
-rreg sr.mdol -edata 0x5a02 \
|
| 332 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x30}] \
|
| 333 |
|
|
-rreg sr.mdoh -edata 0x5a03 \
|
| 334 |
|
|
-rreg sr.mdol -edata 0x5a03 \
|
| 335 |
|
|
-rreg sr.maddrl -edata 0x0004 \
|
| 336 |
|
|
-wreg sr.maddrl 0xffff \
|
| 337 |
|
|
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x3f}] \
|
| 338 |
|
|
-rreg sr.mdoh -edata 0x5a04 \
|
| 339 |
|
|
-rreg sr.mdol -edata 0x5a04
|
| 340 |
|
|
}
|
| 341 |
|
|
#
|
| 342 |
|
|
#-------------------------------------------------------------------------
|
| 343 |
|
|
incr errcnt [rlc errcnt -clear]
|
| 344 |
|
|
return $errcnt
|
| 345 |
|
|
}
|
| 346 |
|
|
}
|
