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# $Id: viv_tools_build.tcl 809 2016-09-18 19:49:14Z mueller $
#
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date         Rev Version  Comment
# 2016-09-18   809   1.2.1  keep hierarchy for synthesis only runs 
# 2016-05-22   767   1.2    cleaner setup handling; use explore flows
#                           add 2016.1 specific setups
# 2016-04-02   758   1.1.5  remove USR_ACCESS setup, must be done in xdc
# 2016-03-26   752   1.1.4  more steps supported: prj,opt,pla
# 2016-03-25   751   1.1.3  suppress some messages
# 2016-03-19   748   1.1.2  set bitstream USR_ACCESS to TIMESTAMP
# 2016-02-28   738   1.1.1  add 2015.4 specific setups
# 2015-02-21   649   1.1    add 2014.4 specific setups
# 2015-02-14   646   1.0    Initial version
#
 
#
# --------------------------------------------------------------------
#
proc rvtb_trace_cmd {cmd} {
  puts "# $cmd"
  eval $cmd
  return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_locate_setup_file {stem} {
  set name "${stem}_setup.tcl"
  if {[file readable $name]} {return $name}
  set name "$../{stem}_setup.tcl"
  if {[file readable $name]} {return $name}
  return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_mv_file {src dst} {
  if {[file readable $src]} {
    exec mv $src $dst
  } else {
    puts "rvtb_mv_file-W: file '$src' not existing"
  }
  return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_rm_file {src} {
  exec rm -f $src
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_cp_file {src dst} {
  if {[file readable $src]} {
    exec cp -p $src $dst
  } else {
    puts "rvtb_cp_file-W: file '$src' not existing"
  }
  return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_build_check {step} {
  return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_version_is {val} {
  set vers [version -short]
  return [expr {$vers eq $val}]
}
#
# --------------------------------------------------------------------
#
proc rvtb_version_min {val} {
  set vers [version -short]
  return [expr {[string compare $vers $val] >= 0}]
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_version_max {val} {
  set vers [version -short]
  return [expr {[string compare $vers $val] <= 0}]
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_version_in {min max} {
  set vers [version -short]
  return [expr {[string compare $vers $min] >= 0 && \
                [string compare $vers $max] <= 0}]
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_default_build {stem step} {
  # supported step values
  #   prj   setup project
  #   syn   run synthesis
  #   opt   run synthesis + implementation up to step opt_design
  #   pla   run synthesis + implementation up to step place_design
  #   imp   run synthesis + implementation (but not bit file generation)
  #   bit   Synthesize + Implement + generate bit file
 
  if {![regexp -- {^(prj|syn|opt|pla|imp|bit)$} $step]} {
    error "bad step name $step"
  }
 
  # general setups (prior to project creation) ------------------
  # version dependent setups 
  if {[rvtb_version_is "2014.4"]} {
    # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
    # set here to avoid messages during create_project
    set_msg_config -suppress -id {Board 49-26}
  }
 
  # read setup
  set setup_file [rvtb_locate_setup_file $stem]
  if {$setup_file ne ""} {source  -notrace $setup_file}
 
  # Create project ----------------------------------------------
  rvtb_trace_cmd "create_project project_mflow ./project_mflow"
 
  # Setup project properties -------------------------------
  set obj [get_projects project_mflow]
  set_property "default_lib"         "xil_defaultlib"    $obj
  set_property "part"                $::rvtb_part        $obj
  set_property "simulator_language"  "Mixed"             $obj
  set_property "target_language"     "VHDL"              $obj
 
  # general setups -----------------------------------------
  #   suppress message which don't convey useful information
  set_msg_config -suppress -id {DRC 23-20};       # DSP48 output pilelining
  set_msg_config -suppress -id {Project 1-120};   # WebTalk mandatory
  set_msg_config -suppress -id {Common 17-186};   # WebTalk info send
 
  # Setup list of extra synthesis options (for later rodinMoreOptions)
  set synth_more_opts {}
 
  # version independent setups -----------------------------
 
  # setup synthesis strategy and options --------------
  set_property strategy Flow_PerfOptimized_high [get_runs synth_1]
  # for synthesis only: keep hierarchy for easier debug
  if {$step eq "syn"} {
    set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none \
                 [get_runs synth_1]
  }
  # FSM recognition threshold (default is 5)
  # see http://www.xilinx.com/support/answers/58574.html
  lappend synth_more_opts {rt::set_parameter minFsmStates 3}
 
  # setup implementation strategy and options ---------
  set_property strategy Performance_Explore [get_runs impl_1]
 
  # version dependent setups -------------------------------
  if {[rvtb_version_is "2014.4"]} {
    # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
    # repeated here because create_project apparently clears msg_config
    set_msg_config -suppress -id {Board 49-26}
  }
 
  if {[rvtb_version_is "2015.4"]} {
    # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html
    lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false}
  }
 
  if {[rvtb_version_min "2016.1"]} {
    # enable vhdl asserts via global option (after 2016.1)
    set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
  }
 
  # now setup extra synthesis options
  #   see http://www.xilinx.com/support/answers/58248.html
  #   -> since used via 'set_param' it's a parameter
  #   -> only last definition counts
  #   -> use ';' separated list
  #   -> these options are **NOT** preserved in project file !!
  if {[llength $synth_more_opts]} {
    puts "# extra synthesis options:"
    foreach opt $synth_more_opts { puts "#   $opt"}
    set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "]
  }
 
  # Setup filesets
  set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"]
  eval $vbom_prj
  update_compile_order -fileset sources_1
 
  if {$step eq "prj"} {
    puts "rvtb_default_build-I: new project setup for ${stem}"
    return ""
  }
 
  # some handy variables
  set path_runs "project_mflow/project_mflow.runs"
  set path_syn1 "${path_runs}/synth_1"
  set path_imp1 "${path_runs}/impl_1"
 
  # build: synthesize ------------------------------------------------
  puts "# current rodinMoreOptions:"
  puts [get_param synth.elaboration.rodinMoreOptions]
 
  rvtb_trace_cmd "launch_runs synth_1"
  rvtb_trace_cmd "wait_on_run synth_1"
 
  rvtb_mv_file "$path_syn1/runme.log"  "${stem}_syn.log"
 
  rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt"
  rvtb_cp_file "$path_syn1/${stem}.dcp"                   "${stem}_syn.dcp"
 
  if {$step eq "syn"} {return [rvtb_build_check $step]}
 
  # build: implement -------------------------------------------------
  set launch_opt ""
  if {$step eq "opt"} {set launch_opt "-to_step opt_design"}
  if {$step eq "pla"} {set launch_opt "-to_step place_design"}
 
  rvtb_trace_cmd "launch_runs ${launch_opt} impl_1"
  rvtb_trace_cmd "wait_on_run impl_1"
 
  rvtb_cp_file "$path_imp1/runme.log"  "${stem}_imp.log"
 
  rvtb_cp_file "$path_imp1/${stem}_opt.dcp"           "${stem}_opt.dcp"
  rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt"     "${stem}_opt_drc.rpt"
 
  if {$step eq "opt"} {
    rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp"
    report_utilization               -file "${stem}_opt_util.rpt"
    report_utilization -hierarchical -file "${stem}_opt_util_h.rpt"
    return [rvtb_build_check $step]
  }
 
  rvtb_cp_file "$path_imp1/${stem}_placed.dcp"        "${stem}_pla.dcp"
  rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt"     "${stem}_pla_io.rpt"
  rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \
                                                      "${stem}_pla_util.rpt"
  rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \
                                                      "${stem}_pla_clk_set.rpt"
 
  if {$step eq "pla"} {
    return [rvtb_build_check $step]
  }
 
  rvtb_cp_file "$path_imp1/${stem}_routed.dcp"        "${stem}_rou.dcp"
  rvtb_cp_file "$path_imp1/${stem}_route_status.rpt"  "${stem}_rou_sta.rpt"
  rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt"    "${stem}_rou_drc.rpt"
  rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \
                                                      "${stem}_rou_tim.rpt"
  rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt"  "${stem}_rou_pwr.rpt"
  rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \
                                                      "${stem}_rou_clk_util.rpt"
 
  # additional reports
  rvtb_trace_cmd "open_run impl_1"
  report_utilization               -file "${stem}_rou_util.rpt"
  report_utilization -hierarchical -file "${stem}_rou_util_h.rpt"
  report_datasheet                 -file "${stem}_rou_ds.rpt"
  report_cdc                       -file "${stem}_rou_cdc.rpt"
  report_clock_interaction -delay_type min_max  -significant_digits 3 \
                                   -file "${stem}_rou_clk_int.rpt"
  if {[get_property SSN_REPORT [get_property PART [current_project]]]} {
    report_ssn -format TXT         -file "${stem}_rou_ssn.rpt"
  }
 
  if {$step eq "imp"} {return [rvtb_build_check $step]}
 
  # build: bitstream -------------------------------------------------
  # check for critical warnings, e.g.
  #   [Timing 38-282] The design failed to meet the timing requirements.
  # in that case abort build
 
  rvtb_rm_file "./${stem}.bit"
 
  if {[get_msg_config -severity {critical warning} -count]} {
    puts "rvtb_default_build-E: abort due to critical warnings seen before"
    puts "rvtb_default_build-E: no bitfile generated"
    return [rvtb_build_check $step]
  }
 
  rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream"
  rvtb_trace_cmd "wait_on_run impl_1"
 
  rvtb_mv_file "$path_imp1/runme.log"     "${stem}_bit.log"
  rvtb_mv_file "$path_imp1/${stem}.bit"   "."
 
  return [rvtb_build_check $step]
}

Line No.	Rev	Author	Line
1	37	wfjm	`# $Id: viv_tools_build.tcl 809 2016-09-18 19:49:14Z mueller $`
2	29	wfjm	`#`
3	36	wfjm	`# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4	29	wfjm	`# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory`
5			`#`
6			`# Revision History:`
7			`# Date Rev Version Comment`
8	37	wfjm	`# 2016-09-18 809 1.2.1 keep hierarchy for synthesis only runs`
9	36	wfjm	`# 2016-05-22 767 1.2 cleaner setup handling; use explore flows`
10			`# add 2016.1 specific setups`
11			`# 2016-04-02 758 1.1.5 remove USR_ACCESS setup, must be done in xdc`
12			`# 2016-03-26 752 1.1.4 more steps supported: prj,opt,pla`
13			`# 2016-03-25 751 1.1.3 suppress some messages`
14			`# 2016-03-19 748 1.1.2 set bitstream USR_ACCESS to TIMESTAMP`
15			`# 2016-02-28 738 1.1.1 add 2015.4 specific setups`
16	29	wfjm	`# 2015-02-21 649 1.1 add 2014.4 specific setups`
17			`# 2015-02-14 646 1.0 Initial version`
18			`#`
19
20			`#`
21			`# --------------------------------------------------------------------`
22			`#`
23			`proc rvtb_trace_cmd {cmd} {`
24			`puts "# $cmd"`
25			`eval $cmd`
26			`return ""`
27			`}`
28
29			`#`
30			`# --------------------------------------------------------------------`
31			`#`
32			`proc rvtb_locate_setup_file {stem} {`
33			`set name "${stem}_setup.tcl"`
34			`if {[file readable $name]} {return $name}`
35			`set name "$../{stem}_setup.tcl"`
36			`if {[file readable $name]} {return $name}`
37			`return ""`
38			`}`
39
40			`#`
41			`# --------------------------------------------------------------------`
42			`#`
43			`proc rvtb_mv_file {src dst} {`
44			`if {[file readable $src]} {`
45			`exec mv $src $dst`
46			`} else {`
47			`puts "rvtb_mv_file-W: file '$src' not existing"`
48			`}`
49			`return ""`
50			`}`
51
52			`#`
53			`# --------------------------------------------------------------------`
54			`#`
55	36	wfjm	`proc rvtb_rm_file {src} {`
56			`exec rm -f $src`
57			`}`
58
59			`#`
60			`# --------------------------------------------------------------------`
61			`#`
62	29	wfjm	`proc rvtb_cp_file {src dst} {`
63			`if {[file readable $src]} {`
64			`exec cp -p $src $dst`
65			`} else {`
66			`puts "rvtb_cp_file-W: file '$src' not existing"`
67			`}`
68			`return ""`
69			`}`
70
71			`#`
72			`# --------------------------------------------------------------------`
73			`#`
74			`proc rvtb_build_check {step} {`
75			`return ""`
76			`}`
77
78			`#`
79			`# --------------------------------------------------------------------`
80			`#`
81	36	wfjm	`proc rvtb_version_is {val} {`
82			`set vers [version -short]`
83			`return [expr {$vers eq $val}]`
84			`}`
85			`#`
86			`# --------------------------------------------------------------------`
87			`#`
88			`proc rvtb_version_min {val} {`
89			`set vers [version -short]`
90			`return [expr {[string compare $vers $val] >= 0}]`
91			`}`
92
93			`#`
94			`# --------------------------------------------------------------------`
95			`#`
96			`proc rvtb_version_max {val} {`
97			`set vers [version -short]`
98			`return [expr {[string compare $vers $val] <= 0}]`
99			`}`
100
101			`#`
102			`# --------------------------------------------------------------------`
103			`#`
104			`proc rvtb_version_in {min max} {`
105			`set vers [version -short]`
106			`return [expr {[string compare $vers $min] >= 0 && \`
107			`[string compare $vers $max] <= 0}]`
108			`}`
109
110			`#`
111			`# --------------------------------------------------------------------`
112			`#`
113	29	wfjm	`proc rvtb_default_build {stem step} {`
114	36	wfjm	`# supported step values`
115			`# prj setup project`
116			`# syn run synthesis`
117			`# opt run synthesis + implementation up to step opt_design`
118			`# pla run synthesis + implementation up to step place_design`
119			`# imp run synthesis + implementation (but not bit file generation)`
120			`# bit Synthesize + Implement + generate bit file`
121
122			`if {![regexp -- {^(prj\|syn\|opt\|pla\|imp\|bit)$} $step]} {`
123			`error "bad step name $step"`
124	29	wfjm	`}`
125
126	36	wfjm	`# general setups (prior to project creation) ------------------`
127			`# version dependent setups`
128			`if {[rvtb_version_is "2014.4"]} {`
129			`# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages`
130			`# set here to avoid messages during create_project`
131			`set_msg_config -suppress -id {Board 49-26}`
132			`}`
133
134	29	wfjm	`# read setup`
135			`set setup_file [rvtb_locate_setup_file $stem]`
136			`if {$setup_file ne ""} {source -notrace $setup_file}`
137
138	36	wfjm	`# Create project ----------------------------------------------`
139	29	wfjm	`rvtb_trace_cmd "create_project project_mflow ./project_mflow"`
140
141	36	wfjm	`# Setup project properties -------------------------------`
142	29	wfjm	`set obj [get_projects project_mflow]`
143			`set_property "default_lib" "xil_defaultlib" $obj`
144			`set_property "part" $::rvtb_part $obj`
145			`set_property "simulator_language" "Mixed" $obj`
146			`set_property "target_language" "VHDL" $obj`
147
148	36	wfjm	`# general setups -----------------------------------------`
149			`# suppress message which don't convey useful information`
150			`set_msg_config -suppress -id {DRC 23-20}; # DSP48 output pilelining`
151			`set_msg_config -suppress -id {Project 1-120}; # WebTalk mandatory`
152			`set_msg_config -suppress -id {Common 17-186}; # WebTalk info send`
153
154			`# Setup list of extra synthesis options (for later rodinMoreOptions)`
155			`set synth_more_opts {}`
156
157			`# version independent setups -----------------------------`
158
159	37	wfjm	`# setup synthesis strategy and options --------------`
160	36	wfjm	`set_property strategy Flow_PerfOptimized_high [get_runs synth_1]`
161	37	wfjm	`# for synthesis only: keep hierarchy for easier debug`
162			`if {$step eq "syn"} {`
163			`set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none \`
164			`[get_runs synth_1]`
165			`}`
166	36	wfjm	`# FSM recognition threshold (default is 5)`
167			`# see http://www.xilinx.com/support/answers/58574.html`
168			`lappend synth_more_opts {rt::set_parameter minFsmStates 3}`
169
170	37	wfjm	`# setup implementation strategy and options ---------`
171			`set_property strategy Performance_Explore [get_runs impl_1]`
172
173	36	wfjm	`# version dependent setups -------------------------------`
174			`if {[rvtb_version_is "2014.4"]} {`
175			`# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages`
176			`# repeated here because create_project apparently clears msg_config`
177			`set_msg_config -suppress -id {Board 49-26}`
178	29	wfjm	`}`
179
180	36	wfjm	`if {[rvtb_version_is "2015.4"]} {`
181			`# enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html`
182			`lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false}`
183			`}`
184
185			`if {[rvtb_version_min "2016.1"]} {`
186			`# enable vhdl asserts via global option (after 2016.1)`
187			`set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]`
188			`}`
189
190			`# now setup extra synthesis options`
191			`# see http://www.xilinx.com/support/answers/58248.html`
192			`# -> since used via 'set_param' it's a parameter`
193			`# -> only last definition counts`
194			`# -> use ';' separated list`
195			`# -> these options are NOT preserved in project file !!`
196			`if {[llength $synth_more_opts]} {`
197			`puts "# extra synthesis options:"`
198			`foreach opt $synth_more_opts { puts "# $opt"}`
199			`set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "]`
200			`}`
201
202	29	wfjm	`# Setup filesets`
203			`set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"]`
204			`eval $vbom_prj`
205			`update_compile_order -fileset sources_1`
206
207	36	wfjm	`if {$step eq "prj"} {`
208			`puts "rvtb_default_build-I: new project setup for ${stem}"`
209			`return ""`
210			`}`
211
212	29	wfjm	`# some handy variables`
213			`set path_runs "project_mflow/project_mflow.runs"`
214			`set path_syn1 "${path_runs}/synth_1"`
215			`set path_imp1 "${path_runs}/impl_1"`
216
217	36	wfjm	`# build: synthesize ------------------------------------------------`
218			`puts "# current rodinMoreOptions:"`
219			`puts [get_param synth.elaboration.rodinMoreOptions]`
220
221	29	wfjm	`rvtb_trace_cmd "launch_runs synth_1"`
222			`rvtb_trace_cmd "wait_on_run synth_1"`
223
224			`rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log"`
225
226			`rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt"`
227	36	wfjm	`rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp"`
228	29	wfjm
229			`if {$step eq "syn"} {return [rvtb_build_check $step]}`
230
231	36	wfjm	`# build: implement -------------------------------------------------`
232			`set launch_opt ""`
233			`if {$step eq "opt"} {set launch_opt "-to_step opt_design"}`
234			`if {$step eq "pla"} {set launch_opt "-to_step place_design"}`
235
236			`rvtb_trace_cmd "launch_runs ${launch_opt} impl_1"`
237	29	wfjm	`rvtb_trace_cmd "wait_on_run impl_1"`
238
239			`rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log"`
240
241	36	wfjm	`rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp"`
242			`rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt"`
243
244			`if {$step eq "opt"} {`
245			`rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp"`
246			`report_utilization -file "${stem}_opt_util.rpt"`
247			`report_utilization -hierarchical -file "${stem}_opt_util_h.rpt"`
248			`return [rvtb_build_check $step]`
249			`}`
250
251			`rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp"`
252			`rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt"`
253			`rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \`
254			`"${stem}_pla_util.rpt"`
255			`rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \`
256			`"${stem}_pla_clk_set.rpt"`
257
258			`if {$step eq "pla"} {`
259			`return [rvtb_build_check $step]`
260			`}`
261
262			`rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp"`
263	29	wfjm	`rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt"`
264			`rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt"`
265			`rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \`
266			`"${stem}_rou_tim.rpt"`
267			`rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt"`
268	36	wfjm	`rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \`
269			`"${stem}_rou_clk_util.rpt"`
270	29	wfjm
271			`# additional reports`
272			`rvtb_trace_cmd "open_run impl_1"`
273	36	wfjm	`report_utilization -file "${stem}_rou_util.rpt"`
274	29	wfjm	`report_utilization -hierarchical -file "${stem}_rou_util_h.rpt"`
275	36	wfjm	`report_datasheet -file "${stem}_rou_ds.rpt"`
276			`report_cdc -file "${stem}_rou_cdc.rpt"`
277			`report_clock_interaction -delay_type min_max -significant_digits 3 \`
278			`-file "${stem}_rou_clk_int.rpt"`
279			`if {[get_property SSN_REPORT [get_property PART [current_project]]]} {`
280			`report_ssn -format TXT -file "${stem}_rou_ssn.rpt"`
281			`}`
282	29	wfjm
283			`if {$step eq "imp"} {return [rvtb_build_check $step]}`
284
285	36	wfjm	`# build: bitstream -------------------------------------------------`
286			`# check for critical warnings, e.g.`
287			`# [Timing 38-282] The design failed to meet the timing requirements.`
288			`# in that case abort build`
289
290			`rvtb_rm_file "./${stem}.bit"`
291
292			`if {[get_msg_config -severity {critical warning} -count]} {`
293			`puts "rvtb_default_build-E: abort due to critical warnings seen before"`
294			`puts "rvtb_default_build-E: no bitfile generated"`
295			`return [rvtb_build_check $step]`
296			`}`
297
298	29	wfjm	`rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream"`
299			`rvtb_trace_cmd "wait_on_run impl_1"`
300
301	36	wfjm	`rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log"`
302			`rvtb_mv_file "$path_imp1/${stem}.bit" "."`
303	29	wfjm
304			`return [rvtb_build_check $step]`
305			`}`

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[/] [w11/] [tags/] [w11a_V0.74/] [tools/] [vivado/] [viv_tools_build.tcl] - Blame information for rev 38