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markom |
Host command: /shared/tools/ncsim/tools/verilog/bin/verilog.exe
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Command arguments:
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timescale.v
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watchdog.v
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watchdog_defines.v
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VERILOG-XL 3.30.p001 log file created Sep 12, 2002 12:04:24
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VERILOG-XL 3.30.p001 Sep 12, 2002 12:04:24
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Copyright (c) 1995 Cadence Design Systems, Inc. All Rights Reserved.
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Unpublished -- rights reserved under the copyright laws of the United States.
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Copyright (c) 1995 UNIX Systems Laboratories, Inc. Reproduced with Permission.
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THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
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AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR
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REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
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CADENCE DESIGN SYSTEMS, INC.
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RESTRICTED RIGHTS LEGEND
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Use, duplication, or disclosure by the Government is subject to
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restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
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Technical Data and Computer Software clause at DFARS 252.227-7013 or
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subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
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Rights at 48 CFR 52.227-19, as applicable.
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Cadence Design Systems, Inc.
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555 River Oaks Parkway
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San Jose, California 95134
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For technical assistance please contact the Cadence Response Center at
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1-877-CDS-4911 or send email to support@cadence.com
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For more information on Cadence's Verilog-XL product line send email to
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talkv@cadence.com
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Compiling source file "timescale.v"
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Compiling source file "watchdog.v"
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Compiling included source file "timescale.v"
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Continuing compilation of source file "watchdog.v"
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Compiling included source file "watchdog_defines.v"
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Continuing compilation of source file "watchdog.v"
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Compiling source file "watchdog_defines.v"
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Highest level modules:
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watchdog
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CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in simulation
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End of VERILOG-XL 3.30.p001 Sep 12, 2002 12:04:24
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