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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant Watchdog timer ////
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//// ////
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//// ////
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//// Author: Marko Mlinar ////
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//// markom@opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Marko Mlinar ////
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//// markom@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/*
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Watchdog time functionality
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===========================
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Watchdog timer has only one wishbone address, holding current counter
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value. Countdown timer decreases its contents by 1 each wishbone clock.
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When 0 is reached, interrupt is asserted. Interrupt is deasserted upon
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next read/write to watchdog timer register.
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If contents of the watchdog timer are -1 (e.g. 32'hffff_ffff), counter is
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stopped.
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Timer can start counting at wisbone reset, if `WDT_INITIAL != -1.
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For typical watchdog timer configuration wb_int_o signal should cause
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system reset.
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*/
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`include "timescale.v"
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`include "watchdog_defines.v"
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module watchdog(
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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wb_int_o);
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parameter Tp = 1;
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// wishbone signals
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input wb_clk_i; // master clock input
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input wb_rst_i; // synchronous active high reset
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input [`WDT_WIDTH - 1:0] wb_dat_i; // databus input
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output [`WDT_WIDTH - 1:0] wb_dat_o; // databus output
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reg [`WDT_WIDTH - 1:0] wb_dat_o;
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input wb_we_i; // write enable input
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input wb_stb_i; // stobe/core select signal
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input wb_cyc_i; // valid bus cycle input
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output wb_ack_o; // bus cycle acknowledge output
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output wb_int_o; // interrupt request signal output
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reg wb_int_o; // interrupt request signal output
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reg stb;
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reg we;
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reg [`WDT_WIDTH - 1:0] dat_ir;
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assign wb_ack_o = stb;
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/* sample input signals */
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always @(posedge wb_rst_i or posedge wb_clk_i)
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if (wb_rst_i) begin
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stb <= #Tp 1'b0;
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we <= #Tp 1'b0;
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dat_ir <= #Tp `WDT_WIDTH'h0;
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end else begin
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stb <= #Tp wb_stb_i && wb_cyc_i;
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we <= #Tp wb_we_i;
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dat_ir <= #Tp wb_dat_i;
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end
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/* Counter */
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always @(posedge wb_rst_i or posedge wb_clk_i)
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if (wb_rst_i) wb_dat_o <= #Tp `WDT_INITIAL;
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else if (stb && we) wb_dat_o <= #Tp dat_ir;
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else if (~&wb_dat_o) wb_dat_o <= #Tp wb_dat_o - `WDT_WIDTH'h1;
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/* Interrupt */
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always @(posedge wb_rst_i or posedge wb_clk_i)
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if (wb_rst_i) wb_int_o <= #Tp 1'b0;
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else if (stb) wb_int_o <= #Tp 1'b0;
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else if (~|wb_dat_o) wb_int_o <= #Tp 1'b1;
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endmodule
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