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[/] [wb2axi4/] [trunk/] [rtl/] [async_fifo.sv] - Blame information for rev 2

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module async_fifo
// *************************** Ports ********************************
(
     rdclk_RESET_N  ,
     wrclk_RESET_N  ,
       fifo_rd_clk  ,
       fifo_wr_clk  ,
             rd_en  ,
             wr_en  ,
           fifo_rd  ,
           fifo_wr  ,
        fifo_wdata  ,
        fifo_rdata  ,
        fifo_empty  ,
         fifo_full  ,
        fifo_level  ,
           SRAM_IF
);
 
// ************************ Parameters ******************************
   parameter FIFO_DEPTH_W   =  10 ;
   parameter FIFO_W         =  64 ;
 
   parameter SRAM_DATA_W    =  64 ;
   parameter SRAM_ADDR_W    =  14 ;
 
   parameter SRAM_UNUSED_ADDR_W    =  4 ;
 
// ********************* Local Parameters  **************************
 
// ********************** Inputs/Outputs ****************************
   input wire                     rdclk_RESET_N  ;
   input wire                     wrclk_RESET_N  ;
   input wire                       fifo_rd_clk  ;
   input wire                       fifo_wr_clk  ;
   input wire                             rd_en  ;
   input wire                             wr_en  ;
   input wire                           fifo_rd  ;
   input wire                           fifo_wr  ;
   input wire  [FIFO_W-1:0]          fifo_wdata  ;
   output wire [FIFO_W-1:0]          fifo_rdata  ;
   output reg                        fifo_empty  ;
   output reg                         fifo_full  ;
   output reg [FIFO_DEPTH_W:0]       fifo_level  ;
   sram_if.initiator                     SRAM_IF ;
 
// **************************  Wires  *******************************
   wire                            next_fifo_full;
   wire                           next_fifo_empty;
   wire [FIFO_DEPTH_W:0]          next_fifo_level;
   wire [FIFO_DEPTH_W:0]              next_wr_ptr;
   wire [FIFO_DEPTH_W:0]              next_rd_ptr;
   wire [FIFO_DEPTH_W:0]         next_gray_wr_ptr;
   wire [FIFO_DEPTH_W:0]         next_gray_rd_ptr;
   wire [FIFO_DEPTH_W:0]        sync_wr_ptr_rdclk;
   wire [FIFO_DEPTH_W:0]   sync_gray_wr_ptr_rdclk;
   wire [FIFO_DEPTH_W:0]   sync_gray_rd_ptr_wrclk;
 
// **************************  Regs   *******************************
   reg [FIFO_DEPTH_W:0]             wr_ptr;
   reg [FIFO_DEPTH_W:0]             rd_ptr;
   reg [FIFO_DEPTH_W:0]        gray_wr_ptr;
   reg [FIFO_DEPTH_W:0]        gray_rd_ptr;
 
// ******************** SRAM_IF control *****************************
   assign SRAM_IF.rd_l = ~fifo_rd;
   assign SRAM_IF.wr_l = ~(fifo_wr & ~fifo_full);
   assign SRAM_IF.rd_address = {  {SRAM_UNUSED_ADDR_W{1'b0}}, rd_ptr[FIFO_DEPTH_W-1:0] }; // rd_ptr in positions (64b words each)
   assign SRAM_IF.wr_address = { {SRAM_UNUSED_ADDR_W{1'b0}}, wr_ptr[FIFO_DEPTH_W-1:0] }; // wr_ptr in positions (64b words each)
   assign SRAM_IF.wdata = fifo_wdata;
   assign fifo_rdata = SRAM_IF.rdata;
 
// ********************* Write pointer  *****************************
   always_ff @(posedge fifo_wr_clk or negedge wrclk_RESET_N)
     begin
        if (!wrclk_RESET_N) begin
           wr_ptr <= 0;
           gray_wr_ptr <= 0;
        end
        else if (wr_en) begin
           wr_ptr <= next_wr_ptr;
           gray_wr_ptr <= next_gray_wr_ptr;
        end
     end
 
   assign next_wr_ptr = wr_ptr + (fifo_wr & ~fifo_full);
   bin2gray #(.DATA_W(FIFO_DEPTH_W+1)) I_BIN2GRAY (
      .bin  (      next_wr_ptr ),
      .gray ( next_gray_wr_ptr )
   );
 
// ******************* Read pointer resync  *************************
   sync_doble_ff #(.DATA_W(FIFO_DEPTH_W+1)) I_SYNC_RD (
     .CLK              (                 fifo_wr_clk ),
     .RESET_N          (               wrclk_RESET_N ),
     .DIN              (                 gray_rd_ptr ),
     .DOUT             (      sync_gray_rd_ptr_wrclk )
   );
 
// *********************** FIFO full  *******************************
   assign next_fifo_full = (next_gray_wr_ptr == { ~sync_gray_rd_ptr_wrclk[FIFO_DEPTH_W:FIFO_DEPTH_W-1], sync_gray_rd_ptr_wrclk[FIFO_DEPTH_W-2:0] });
 
   always_ff @(posedge fifo_wr_clk or negedge wrclk_RESET_N)
     begin
        if (!wrclk_RESET_N) fifo_full <= 0;
        else if (wr_en) fifo_full <= next_fifo_full;
     end
 
// ********************** Read pointer  *****************************
   always_ff @(posedge fifo_rd_clk or negedge rdclk_RESET_N)
     begin
        if (!rdclk_RESET_N) begin
           rd_ptr <= 0;
           gray_rd_ptr <= 0;
        end
        else if (rd_en) begin
           rd_ptr <= next_rd_ptr;
           gray_rd_ptr <= next_gray_rd_ptr;
        end
     end
 
   assign next_rd_ptr = rd_ptr + (fifo_rd & ~fifo_empty);
   bin2gray #(.DATA_W(FIFO_DEPTH_W+1)) I_BIN2GRAY_RD (
      .bin  (      next_rd_ptr ),
      .gray ( next_gray_rd_ptr )
   );
 
// ***************xt_**** Write pointer resync  *************************
   sync_doble_ff #(.DATA_W(FIFO_DEPTH_W+1)) I_SYNC_WR (
     .CLK              (                 fifo_rd_clk ),
     .RESET_N          (               rdclk_RESET_N ),
     .DIN              (                 gray_wr_ptr ),
     .DOUT             (      sync_gray_wr_ptr_rdclk )
   );
 
// ********************  FIFO empty, level  ***************************
   assign next_fifo_empty = (next_gray_rd_ptr == sync_gray_wr_ptr_rdclk );
 
   gray2bin #(.DATA_W(FIFO_DEPTH_W+1)) I_GRAY2BIN_WR (
      .gray (      sync_gray_wr_ptr_rdclk ),
      .bin (            sync_wr_ptr_rdclk )
   );
   assign next_fifo_level = sync_wr_ptr_rdclk - next_rd_ptr;
 
   always_ff @(posedge fifo_rd_clk or negedge rdclk_RESET_N)
     begin
        if (!rdclk_RESET_N) begin
           fifo_empty <= 1;
           fifo_level <= 0;
        end
        else if (rd_en) begin
           fifo_empty <= next_fifo_empty;
           fifo_level <= next_fifo_level;
        end
     end
 
endmodule

Line No.	Rev	Author	Line
1	2	alzhang	`module async_fifo`
2			`// ************************* Ports ******************************`
3			`(`
4			`rdclk_RESET_N ,`
5			`wrclk_RESET_N ,`
6			`fifo_rd_clk ,`
7			`fifo_wr_clk ,`
8			`rd_en ,`
9			`wr_en ,`
10			`fifo_rd ,`
11			`fifo_wr ,`
12			`fifo_wdata ,`
13			`fifo_rdata ,`
14			`fifo_empty ,`
15			`fifo_full ,`
16			`fifo_level ,`
17			`SRAM_IF`
18			`);`
19
20			`// ********************** Parameters ****************************`
21			`parameter FIFO_DEPTH_W = 10 ;`
22			`parameter FIFO_W = 64 ;`
23
24			`parameter SRAM_DATA_W = 64 ;`
25			`parameter SRAM_ADDR_W = 14 ;`
26
27			`parameter SRAM_UNUSED_ADDR_W = 4 ;`
28
29			`// ******************* Local Parameters ************************`
30
31			`// ******************** Inputs/Outputs **************************`
32			`input wire rdclk_RESET_N ;`
33			`input wire wrclk_RESET_N ;`
34			`input wire fifo_rd_clk ;`
35			`input wire fifo_wr_clk ;`
36			`input wire rd_en ;`
37			`input wire wr_en ;`
38			`input wire fifo_rd ;`
39			`input wire fifo_wr ;`
40			`input wire [FIFO_W-1:0] fifo_wdata ;`
41			`output wire [FIFO_W-1:0] fifo_rdata ;`
42			`output reg fifo_empty ;`
43			`output reg fifo_full ;`
44			`output reg [FIFO_DEPTH_W:0] fifo_level ;`
45			`sram_if.initiator SRAM_IF ;`
46
47			`// ************************ Wires *****************************`
48			`wire next_fifo_full;`
49			`wire next_fifo_empty;`
50			`wire [FIFO_DEPTH_W:0] next_fifo_level;`
51			`wire [FIFO_DEPTH_W:0] next_wr_ptr;`
52			`wire [FIFO_DEPTH_W:0] next_rd_ptr;`
53			`wire [FIFO_DEPTH_W:0] next_gray_wr_ptr;`
54			`wire [FIFO_DEPTH_W:0] next_gray_rd_ptr;`
55			`wire [FIFO_DEPTH_W:0] sync_wr_ptr_rdclk;`
56			`wire [FIFO_DEPTH_W:0] sync_gray_wr_ptr_rdclk;`
57			`wire [FIFO_DEPTH_W:0] sync_gray_rd_ptr_wrclk;`
58
59			`// ************************ Regs *****************************`
60			`reg [FIFO_DEPTH_W:0] wr_ptr;`
61			`reg [FIFO_DEPTH_W:0] rd_ptr;`
62			`reg [FIFO_DEPTH_W:0] gray_wr_ptr;`
63			`reg [FIFO_DEPTH_W:0] gray_rd_ptr;`
64
65			`// ****************** SRAM_IF control ***************************`
66			`assign SRAM_IF.rd_l = ~fifo_rd;`
67			`assign SRAM_IF.wr_l = ~(fifo_wr & ~fifo_full);`
68			`assign SRAM_IF.rd_address = { {SRAM_UNUSED_ADDR_W{1'b0}}, rd_ptr[FIFO_DEPTH_W-1:0] }; // rd_ptr in positions (64b words each)`
69			`assign SRAM_IF.wr_address = { {SRAM_UNUSED_ADDR_W{1'b0}}, wr_ptr[FIFO_DEPTH_W-1:0] }; // wr_ptr in positions (64b words each)`
70			`assign SRAM_IF.wdata = fifo_wdata;`
71			`assign fifo_rdata = SRAM_IF.rdata;`
72
73			`// ******************* Write pointer ***************************`
74			`always_ff @(posedge fifo_wr_clk or negedge wrclk_RESET_N)`
75			`begin`
76			`if (!wrclk_RESET_N) begin`
77			`wr_ptr <= 0;`
78			`gray_wr_ptr <= 0;`
79			`end`
80			`else if (wr_en) begin`
81			`wr_ptr <= next_wr_ptr;`
82			`gray_wr_ptr <= next_gray_wr_ptr;`
83			`end`
84			`end`
85
86			`assign next_wr_ptr = wr_ptr + (fifo_wr & ~fifo_full);`
87			`bin2gray #(.DATA_W(FIFO_DEPTH_W+1)) I_BIN2GRAY (`
88			`.bin ( next_wr_ptr ),`
89			`.gray ( next_gray_wr_ptr )`
90			`);`
91
92			`// ***************** Read pointer resync ***********************`
93			`sync_doble_ff #(.DATA_W(FIFO_DEPTH_W+1)) I_SYNC_RD (`
94			`.CLK ( fifo_wr_clk ),`
95			`.RESET_N ( wrclk_RESET_N ),`
96			`.DIN ( gray_rd_ptr ),`
97			`.DOUT ( sync_gray_rd_ptr_wrclk )`
98			`);`
99
100			`// ********************* FIFO full *****************************`
101			`assign next_fifo_full = (next_gray_wr_ptr == { ~sync_gray_rd_ptr_wrclk[FIFO_DEPTH_W:FIFO_DEPTH_W-1], sync_gray_rd_ptr_wrclk[FIFO_DEPTH_W-2:0] });`
102
103			`always_ff @(posedge fifo_wr_clk or negedge wrclk_RESET_N)`
104			`begin`
105			`if (!wrclk_RESET_N) fifo_full <= 0;`
106			`else if (wr_en) fifo_full <= next_fifo_full;`
107			`end`
108
109			`// ******************** Read pointer ***************************`
110			`always_ff @(posedge fifo_rd_clk or negedge rdclk_RESET_N)`
111			`begin`
112			`if (!rdclk_RESET_N) begin`
113			`rd_ptr <= 0;`
114			`gray_rd_ptr <= 0;`
115			`end`
116			`else if (rd_en) begin`
117			`rd_ptr <= next_rd_ptr;`
118			`gray_rd_ptr <= next_gray_rd_ptr;`
119			`end`
120			`end`
121
122			`assign next_rd_ptr = rd_ptr + (fifo_rd & ~fifo_empty);`
123			`bin2gray #(.DATA_W(FIFO_DEPTH_W+1)) I_BIN2GRAY_RD (`
124			`.bin ( next_rd_ptr ),`
125			`.gray ( next_gray_rd_ptr )`
126			`);`
127
128			`// *************xt_ Write pointer resync ***********************`
129			`sync_doble_ff #(.DATA_W(FIFO_DEPTH_W+1)) I_SYNC_WR (`
130			`.CLK ( fifo_rd_clk ),`
131			`.RESET_N ( rdclk_RESET_N ),`
132			`.DIN ( gray_wr_ptr ),`
133			`.DOUT ( sync_gray_wr_ptr_rdclk )`
134			`);`
135
136			`// ****************** FIFO empty, level *************************`
137			`assign next_fifo_empty = (next_gray_rd_ptr == sync_gray_wr_ptr_rdclk );`
138
139			`gray2bin #(.DATA_W(FIFO_DEPTH_W+1)) I_GRAY2BIN_WR (`
140			`.gray ( sync_gray_wr_ptr_rdclk ),`
141			`.bin ( sync_wr_ptr_rdclk )`
142			`);`
143			`assign next_fifo_level = sync_wr_ptr_rdclk - next_rd_ptr;`
144
145			`always_ff @(posedge fifo_rd_clk or negedge rdclk_RESET_N)`
146			`begin`
147			`if (!rdclk_RESET_N) begin`
148			`fifo_empty <= 1;`
149			`fifo_level <= 0;`
150			`end`
151			`else if (rd_en) begin`
152			`fifo_empty <= next_fifo_empty;`
153			`fifo_level <= next_fifo_level;`
154			`end`
155			`end`
156
157			`endmodule`

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[/] [wb2axi4/] [trunk/] [rtl/] [async_fifo.sv] - Blame information for rev 2