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[/] [wb2axi4/] [trunk/] [rtl/] [bin2gray.sv] - Blame information for rev 2

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1 2 alzhang 
module bin2gray (
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// *************************** Ports ********************************
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      bin,
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     gray
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 );
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// ************************ Parameters ******************************
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  parameter DATA_W   = 32  ;
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// ********************** Inputs/Outputs ****************************
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  input wire  [DATA_W-1:0] bin  ;
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  output wire [DATA_W-1:0] gray ;
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  assign gray = {1'b0, bin[DATA_W-1:1] } ^ bin;
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endmodule // bin2gray
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