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[/] [wb2axi4/] [trunk/] [rtl/] [gray2bin.sv] - Blame information for rev 3

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1 3 alzhang 
module gray2bin (
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// *************************** Ports ********************************
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     gray ,
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      bin
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 );
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// ************************ Parameters ******************************
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  parameter DATA_W   = 32  ;
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// ********************** Inputs/Outputs ****************************
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  input wire  [DATA_W-1:0] gray ;
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  output wire [DATA_W-1:0] bin  ;
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  genvar                   i ;
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  generate
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       for (i=0; i
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          assign bin[i] = ^(gray >> i);
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       end
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  endgenerate
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endmodule // gray2bin

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