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[/] [wb2axi4/] [trunk/] [rtl/] [sync_single_ff.sv] - Blame information for rev 2

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1 2 alzhang
module sync_single_ff (
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// *************************** Ports ********************************
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        DIN ,
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       DOUT ,
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        CLK ,
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    RESET_N
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 );
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// ************************ Parameters ******************************
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  parameter DATA_W   = 32  ;
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// ********************** Inputs/Outputs ****************************
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  input wire  [DATA_W-1:0]  DIN ;
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  output reg  [DATA_W-1:0] DOUT ;
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  input                     CLK ;
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  input                 RESET_N ;
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// **************************  Regs  ********************************
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  always @(posedge CLK or negedge RESET_N)
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    begin
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       if (!RESET_N) {DOUT } <= 0;
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       else {DOUT} <= { DIN};
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    end
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endmodule // sync_single_ff
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//*****************************************************************************
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