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[/] [wb2axi4/] [trunk/] [rtl/] [wb_egress.sv] - Blame information for rev 2

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Line No. Rev Author Line
1 2 alzhang 
//Author     : Alex Zhang (cgzhangwei@gmail.com)
2 
//Date       : 03-11-2015
3 
//Description: Now support the classic WB protocol.
4 
//             Change the ACK_I meaing to improve the efficiency.
5 
//TODO       : 4 beat wrapper or 8 beat wrapper is not supported yet.
6 
 
7 
module wb_egress(
8 
wb_clk,
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wb_resetn,
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ENABLE,
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WB_TX_IF,
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fifo_adr_rdata,
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fifo_adr_rd,
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fifo_adr_empty,
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fifo_dat_rdata,
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fifo_dat_rd,
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fifo_dat_empty,
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);
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20 
parameter  WB_ADR_W      = 32;
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parameter  WB_DAT_W      = 32;
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parameter  WB_TGA_W      = 8;
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parameter  WB_TGD_W      = 8;
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parameter  WB_TGC_W      = 4;
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parameter  WB_SEL_W      = 4;
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parameter  WB_CTI_W      = 3;
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parameter  WB_BTE_W      = 2;
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parameter  AXI_ID_W      = 3;
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parameter  AXI_ADDR_W    = 32;
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parameter  AXI_LEN_W     = 4;
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parameter  AXI_SIZE_W    = 3;
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parameter  AXI_BURST_W   = 2;
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parameter  AXI_LOCK_W    = 2;
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parameter  AXI_CACHE_W   = 4;
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parameter  AXI_PROT_W    = 3;
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parameter  AXI_DATA_W    = 32;
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parameter  AXI_STRB_W    = 4;
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parameter  FIFO_ADR_W    = AXI_ID_W + AXI_ADDR_W + AXI_LEN_W + AXI_SIZE_W + AXI_BURST_W + AXI_LOCK_W + AXI_CACHE_W + AXI_PROT_W +1 ;
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parameter  FIFO_DAT_W    = AXI_ID_W + AXI_DATA_W + AXI_STRB_W + 2;
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parameter  ST_W          = 2 ;
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parameter  ST_IDLE       = 2'b00,
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           ST_READ_ADDR  = 2'b01,
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           ST_WAIT_DATA  = 2'b10,
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           ST_READ_DATA  = 2'b11;
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parameter  WB_W          = 2;
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parameter  WB_IDLE       = 2'b00,
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           WB_FIRST_DATA = 2'b01,
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           WB_NEXT_DATA  = 2'b10;
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50 
input  wire                          wb_clk;
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input  wire                          wb_resetn;
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input  wire                          ENABLE;
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wb_if.master                         WB_TX_IF;
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input  wire [FIFO_ADR_W-1:0]         fifo_adr_rdata;
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output wire                          fifo_adr_rd;
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input  wire                          fifo_adr_empty;
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input  wire [FIFO_DAT_W-1:0]         fifo_dat_rdata;
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output wire                          fifo_dat_rd;
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input  wire                          fifo_dat_empty;
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61 
 
62 
reg  [ST_W-1:0]        state;
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reg  [ST_W-1:0]        next_state;
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reg                    inc_dat_ptr;
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reg  [4:0]             data_count;
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wire                   allow_adr_rd;
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wire                   fifo_adr_rd;
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wire                   fifo_adr_rd_q;
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wire                   fifo_dat_rd;
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reg  [AXI_ID_W   -1:0] axi_id    ;
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reg  [AXI_ADDR_W -1:0] axi_addr  ;
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reg  [AXI_LEN_W  -1:0] axi_len   ;
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reg  [AXI_SIZE_W -1:0] axi_size  ;
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reg  [AXI_BURST_W-1:0] axi_burst ;
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reg  [AXI_LOCK_W -1:0] axi_lock  ;
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reg  [AXI_CACHE_W-1:0] axi_cache ;
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reg  [AXI_PROT_W -1:0] axi_prot  ;
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reg                    wr_req    ;
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reg  [AXI_ID_W   -1:0] axi_wid   ;
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reg  [AXI_DATA_W -1:0] axi_wdata ;
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reg  [AXI_STRB_W -1:0] axi_wstrb ;
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reg                    axi_wlast ;
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reg                    axi_wvalid;
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reg                    wb_we_o ;
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reg  [WB_ADR_W-1:0]    wb_adr_o;
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reg  [WB_TGA_W-1:0]    wb_tga_o;
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reg  [WB_ADR_W-1:0]    wb_adr_tmp;
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reg  [WB_BTE_W-1:0]    wb_bte_o;
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reg                    wb_cyc_o;
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reg  [WB_TGC_W-1:0]    wb_tgc_o;
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reg  [WB_CTI_W-1:0]    wb_cti_o;
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reg  [WB_STB_W-1:0]    wb_stb_o;
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reg  [WB_DAT_W-1:0]    wb_dat_o;
94 
reg  [WB_TGD_W-1:0]    wb_tgd_o;
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reg  [WB_SEL_W-1:0]    wb_sel_o;
96 
 
97 
 
98 
assign allow_adr_rd = wb_cs == WB_IDLE;
99 
always_comb begin
100 
  next_state = state;
101 
  inc_dat_ptr  = 0; //int- internal
102 
  case (state)
103 
    ST_IDLE : begin
104 
      if (!fifo_adr_empty&allow_adr_rd) begin
105 
        next_state = ST_READ_ADDR;
106 
      end else begin
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        next_state = ST_IDLE;
108 
      end
109 
    end
110 
    ST_READ_ADDR : begin
111 
      next_state = ST_WAIT_DATA;
112 
    end
113 
    ST_WAIT_DATA : begin
114 
      if (WB_TX_IF.ACK_I & !fifo_dat_empty) begin
115 
        next_state = ST_READ_DATA;
116 
      end else begin
117 
        next_state = ST_WAIT_DATA;
118 
      end
119 
    end
120 
    ST_READ_DATA : begin
121 
      if (data_count>0 & WB_TX_IF.ACK_I) begin
122 
        next_state = ST_READ_DATA;
123 
        inc_dat_ptr = 1;
124 
      end else if (data_count>0) begin
125 
        next_state = ST_WAIT_DATA;
126 
        inc_dat_ptr = 0;
127 
      end
128 
        next_state = ST_IDLE;
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        inc_dat_ptr = 0;
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      end
131 
    end
132 
  endcase
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end
134 
 
135 
assign fifo_adr_rd = state == ST_READ_ADDR;
136 
assign fifo_dat_rd = inc_dat_ptr;
137 
 
138 
sync_single_ff #(.DATA_W(1)) adr_rd_ff (
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  .DIN    ( fifo_adr_rd   ),
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  .DOUT   ( fifo_adr_rd_q ),
141 
  .CLK    ( wb_clk        ),
142 
  .RESET_N( wb_resetn     )
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)
144 
always @(posedge wb_clk or negedge wb_resetn)
145 
  if (~wb_resetn) begin
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    state <= ST_IDLE;
147 
    data_count <= 0 ;
148 
  end else begin
149 
    state <= next_state;
150 
    data_count <= state==ST_READ_ADDR ? axi_len   + 1 :
151 
                  state==ST_READ_DATA ? data_count -1 : data_count ;
152 
  end
153 
 
154 
//AXI3 only accept the alignment input of 4Byte-aligned data.i.e. awaddr[1:0]==0
155 
 
156 
 
157 
always @(posedge wb_clk or negedge wb_resetn)
158 
  if (~wb_resetn) begin
159 
    axi_id     <= 0;
160 
    axi_addr   <= 0;
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    axi_len    <= 0;
162 
    axi_size   <= 0;
163 
    axi_burst  <= 0;
164 
    axi_lock   <= 0;
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    axi_cache  <= 0;
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    axi_prot   <= 0;
167 
    wr_req     <= 0;
168 
    axi_wid    <= 0;
169 
    axi_wdata  <= 0;
170 
    axi_wstrb  <= 0;
171 
    axi_wlast  <= 0;
172 
    axi_wvalid <= 0;
173 
  end else begin
174 
    if ( fifo_adr_rd )
175 
      {axi_id, axi_addr, axi_len, axi_size, axi_burst, axi_lock, axi_cache, axi_prot, wr_req}<= fifo_adr_rdata;
176 
    if ( fifo_dat_rd )
177 
      {axi_wid, axi_wdata, axi_wstrb, axi_wlast, axi_wvalid}<= fifo_dat_rdata;
178 
  end
179 
 
180 
always @(posedge wb_clk or negedge wb_resetn) begin
181 
  if (~wb_resetn) begin
182 
    wb_cs <= WB_IDLE;
183 
  end else begin
184 
    wb_cs <= wb_ns;
185 
  end
186 
end
187 
///Wishbone master output
188 
always @(*) begin
189 
  wb_ns = wb_cs;
190 
  case (wb_cs)
191 
    WB_IDLE : begin
192 
      if (fifo_data_rd) begin
193 
        wb_ns = WB_FIRST_DATA;
194 
      end  else begin
195 
        wb_ns = WB_IDLE;
196 
      end
197 
    end
198 
    WB_FIRST_DATA : begin
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      if (axi_wlast & WB_TX_IF.ACK_I)
200 
        wb_ns = WB_IDLE;
201 
      else if (~axi_wlast & WB_TX_IF.ACK_I)
202 
        wb_ns = WB_NEXT_DATA;
203 
      else
204 
        wb_ns = WB_FIRST_DATA;
205 
    end
206 
 
207 
    WB_NEXT_DATA : begin
208 
      if (axi_wlast & WB_TX_IF.ACK_I)
209 
        wb_ns = WB_IDLE;
210 
      else
211 
        wb_ns = WB_NEXT_DATA;
212 
    end
213 
  endcase
214 
end
215 
 
216 
 
217 
always @(posedge wb_clk or negedge wb_resetn) begin
218 
  if (~wb_resetn) begin
219 
        wb_we_o  <= 0;
220 
        wb_adr_o <= 0;
221 
        wb_tga_o <= 0;
222 
 
223 
        wb_adr_tmp <= 0;
224 
        wb_bte_o <= 0;
225 
        wb_cyc_o <= 0;
226 
        wb_tgc_o <= 0;
227 
        wb_cti_o <= 0;
228 
        wb_stb_o <= 0;
229 
 
230 
        wb_dat_o <= 0;
231 
        wb_tgd_o <= 0;
232 
        wb_sel_o <= 0;
233 
  end else begin
234 
    case (wb_cs)
235 
      WB_IDLE : begin
236 
        wb_we_o  <= 0;
237 
        wb_adr_o <= 0;
238 
        wb_tga_o <= 0;
239 
 
240 
        wb_bte_o <= 0;
241 
        wb_cyc_o <= 0;
242 
        wb_tgc_o <= 0;
243 
        wb_cti_o <= 0;
244 
        wb_stb_o <= 0;
245 
 
246 
        wb_dat_o <= 0;
247 
        wb_tgd_o <= 0;
248 
        wb_sel_o <= 0;
249 
      end
250 
      WB_FIRST_DATA : begin
251 
        wb_we_o  <= wr_req;
252 
        wb_adr_o <= axi_addr;
253 
        wb_adr_tmp <= axi_addr;
254 
        wb_len_tmp <= axi_len-1;
255 
        wb_tga_o <= axi_id;
256 
 
257 
        wb_bte_o <= 2'b00; //burst
258 
        wb_cyc_o <= 1;
259 
        wb_tgc_o <= {axi_prot, axi_cache, axi_lock, axi_len};
260 
        wb_cti_o <= axi_wlast ? 3'b111 : 3'b000;
261 
        wb_stb_o <= 1;
262 
 
263 
        wb_dat_o <= axi_wdata;
264 
        wb_tgd_o <= axi_wid;
265 
        wb_sel_o <= axi_wstrb;
266 
      end
267 
      WB_NEXT_DATA : begin
268 
        wb_we_o  <= wr_req;
269 
        wb_adr_o <= wb_adr_tmp + 4'b100;
270 
        wb_adr_tmp <= wb_adr_tmp +4'b100;
271 
        wb_len_tmp <= wb_len_tmp -1 ;
272 
        wb_tga_o <= axi_id;
273 
 
274 
        wb_bte_o <= 2'b00; //burst
275 
        wb_cyc_o <= 1;
276 
        wb_tgc_o <= {axi_prot, axi_cache, axi_lock, wb_len_tmp };
277 
        wb_cti_o <= axi_wlast ? 3'b111 : 3'b000;
278 
        wb_stb_o <= 1;
279 
 
280 
        wb_dat_o <= axi_wdata;
281 
        wb_tgd_o <= axi_wid;
282 
        wb_sel_o <= axi_wstrb;
283 
      end
284 
    endcase
285 
  end
286 
end
287 
 
288 
assign WB_TX_IF.ADR_O = wb_adr_o;
289 
assign WB_TX_IF.WE_O  = wb_we_o;
290 
assign WB_TX_IF.TGA_O = wb_tga_o;
291 
assign WB_TX_IF.BTE_O = wb_bte_o;
292 
assign WB_TX_IF.CYC_O = wb_cyc_o;
293 
assign WB_TX_IF.TGC_O = wb_tgc_o;
294 
assign WB_TX_IF.CTI_O = wb_cti_o;
295 
assign WB_TX_IF.STB_O = wb_stb_o;
296 
assign WB_TX_IF.DAT_O = wb_dat_o;
297 
assign WB_TX_IF.TGD_O = wb_tgd_o;
298 
assign WB_TX_IF.SEL_O = wb_sel_o;
299 
 
300 
endmodule

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