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https://opencores.org/ocsvn/wb2axi4/wb2axi4/trunk
[/] [wb2axi4/] [trunk/] [verif/] [Makefile] - Blame information for rev 3
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3 |
alzhang |
VCS=/proj/cadtools/bin/vcs
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TGT=simv
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VERICOM=/proj/cadtools/bin/vericom
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VERDI=/proj/cadtools/bin/verdi
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TAB_FILE=/proj/cadsim/simtools/simtools2.linux/pli64_rh4/dummytbv.tab
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PLI_FILE=/proj/cadsim/simtools/simtools2.linux/pli64_rh4/dummytbv_vcs.a
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VERDI_TAB=/proj/caeeda/NOVAS/VERDI/201403-3/share/PLI/VCS/LINUX/verdi.tab
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VERDI_PLI=/proj/caeeda/NOVAS/VERDI/201403-3/share/PLI/VCS/LINUX/pli.a
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SIM_DIR= $(PROJ_TOP)/output/
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SRCFILE = src.vlist
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FLAGS= +lint=TFIPC-L -P $(VERDI_TAB) $(VERDI_PLI) -unit_timescale=1ps/1ps
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all:simv
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setup:
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mkdir -p $(SIM_DIR)
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cd $(SIM_DIR); ln -fs $(PROJ_TOP)/verif/* .
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$(TGT):$(SRCFILE)
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rm out -rf
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mkdir out
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$(VCS) -sverilog $(FLAGS) +define+DUMPFSDB -f $(SRCFILE) -sgq short
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run: $(TGT)
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/proj/caeeda/SYNOPSYS/bin/simv -sgq normal
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run_verdi:
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$(VERDI) -f src.vlist -top tb -ssf $(SIM_DIR)/test_wb2axi.fsdb -sgq normal
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clean:
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rm simv; rm csrc -rf; rm *.daidir -rf; rm out -rf; rm verdiLog -rf; rm vcs.log; rm novas.*; rm ucli.key
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