OpenCores
URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [bench/] [cpp/] [aximemsim.h] - Blame information for rev 16

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    aximemsim.h
4
//
5
// Project:     Pipelined Wishbone to AXI converter
6
//
7
// Purpose:     To attempt to emulate how the MIG responds to AXI requests.
8
//              Of course, this is written with no knowledge of how MIG actually
9
//      responds, just a touch of knowledge regarding how a DDR3 memory works,
10
//      so ... your mileage might vary.
11
//
12
// Creator:     Dan Gisselquist, Ph.D.
13
//              Gisselquist Technology, LLC
14
//
15
////////////////////////////////////////////////////////////////////////////////
16
//
17 16 dgisselq
// Copyright (C) 2016-2018, Gisselquist Technology, LLC
18 8 dgisselq
//
19 16 dgisselq
// This file is part of the pipelined Wishbone to AXI converter project, a
20
// project that contains multiple bus bridging designs and formal bus property
21
// sets.
22 8 dgisselq
//
23 16 dgisselq
// The bus bridge designs and property sets are free RTL designs: you can
24
// redistribute them and/or modify any of them under the terms of the GNU
25
// Lesser General Public License as published by the Free Software Foundation,
26
// either version 3 of the License, or (at your option) any later version.
27 8 dgisselq
//
28 16 dgisselq
// The bus bridge designs and property sets are distributed in the hope that
29
// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
30
// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
31
// GNU Lesser General Public License for more details.
32
//
33
// You should have received a copy of the GNU Lesser General Public License
34
// along with these designs.  (It's in the $(ROOT)/doc directory.  Run make
35
// with no target there if the PDF file isn't present.)  If not, see
36 8 dgisselq
// <http://www.gnu.org/licenses/> for a copy.
37
//
38 16 dgisselq
// License:     LGPL, v3, as defined and found on www.gnu.org,
39
//              http://www.gnu.org/licenses/lgpl.html
40 8 dgisselq
//
41
////////////////////////////////////////////////////////////////////////////////
42
//
43
//
44
#ifndef AXIMEMSIM_H
45
#define AXIMEMSIM_H
46
 
47
typedef struct {
48
        unsigned        addr;
49
        int             id, len, size, burst, lock, cache, prot, qos;
50
        bool            ready, valid;
51
} AXI_AWBUS;
52
 
53
typedef struct {
54
        unsigned        addr;
55
        int             id, len, size, burst, lock, cache, prot, qos;
56
        bool            ready, valid;
57
} AXI_ARBUS;
58
 
59
typedef struct {
60
        int             strb;
61
        unsigned        data[4];        // 128 bits
62
        int             ready, valid, last;
63
} AXI_WBUS;
64
 
65
typedef struct {
66
        int             id, resp;
67
        int             ready, valid;
68
} AXI_WRESP;
69
 
70
typedef struct {
71
        int             id, resp;
72
        unsigned        data[4];        // 128 bits
73
        int             ready, valid, last;
74
} AXI_RDATA;
75
 
76
typedef struct  {
77
        AXI_AWBUS       aw;
78
        AXI_ARBUS       ar;
79
        AXI_WBUS        w;
80
        AXI_WRESP       b;
81
        AXI_RDATA       r;
82
} AXIBUS;
83
 
84
class   AXIMEMSIM {
85
        unsigned        *m_mem;
86
public:
87
        AXIMEMSIM(unsigned abits);
88
        void    apply(AXIBUS &bus);
89
};
90
 
91
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.