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[/] [wb2axip/] [trunk/] [bench/] [formal/] [axim2wbsp.ys] - Blame information for rev 16

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Line No. Rev Author Line
1 10 dgisselq
read_verilog -D AXIM2WBSP -formal ../../rtl/axim2wbsp.v
2
read_verilog -D AXIM2WBSP -formal ../../rtl/aximwr2wbsp.v
3
read_verilog -D AXIM2WBSP -formal ../../rtl/aximrd2wbsp.v
4
read_verilog -D AXIM2WBSP -formal ../../rtl/wbarbiter.v
5
read_verilog -D AXIM2WBSP -formal fwb_master.v
6
read_verilog -D AXIM2WBSP -formal fwb_slave.v
7
read_verilog -D AXIM2WBSP -formal faxi_slave.v
8 16 dgisselq
read_verilog -D AXIM2WBSP -formal f_order.v
9 10 dgisselq
prep -top axim2wbsp -nordff
10
write_smt2 -wires axim2wbsp.smt2

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