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dgisselq |
`default_nettype none // Added to the raw demo
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`timescale 1 ns / 1 ps
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//
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module xlnxdemo #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Width of S_AXI data bus
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parameter integer C_S_AXI_DATA_WIDTH = 32,
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// Width of S_AXI address bus
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parameter integer C_S_AXI_ADDR_WIDTH = 7
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)
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(
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// Users to add ports here
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// User ports ends
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// Do not modify the ports beyond this line
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// Global Clock Signal
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input wire S_AXI_ACLK,
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// Global Reset Signal. This Signal is Active LOW
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input wire S_AXI_ARESETN,
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// Write address (issued by master, acceped by Slave)
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
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// Write channel Protection type. This signal indicates the
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// privilege and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_AWPROT,
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// Write address valid. This signal indicates that the master signaling
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// valid write address and control information.
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input wire S_AXI_AWVALID,
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// Write address ready. This signal indicates that the slave is ready
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// to accept an address and associated control signals.
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output wire S_AXI_AWREADY,
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// Write data (issued by master, acceped by Slave)
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input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
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// Write strobes. This signal indicates which byte lanes hold
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// valid data. There is one write strobe bit for each eight
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// bits of the write data bus.
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input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
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// Write valid. This signal indicates that valid write
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// data and strobes are available.
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input wire S_AXI_WVALID,
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// Write ready. This signal indicates that the slave
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// can accept the write data.
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output wire S_AXI_WREADY,
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// Write response. This signal indicates the status
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// of the write transaction.
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output wire [1 : 0] S_AXI_BRESP,
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// Write response valid. This signal indicates that the channel
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// is signaling a valid write response.
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output wire S_AXI_BVALID,
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// Response ready. This signal indicates that the master
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// can accept a write response.
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input wire S_AXI_BREADY,
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// Read address (issued by master, acceped by Slave)
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether the
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// transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_ARPROT,
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// Read address valid. This signal indicates that the channel
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// is signaling valid read address and control information.
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input wire S_AXI_ARVALID,
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// Read address ready. This signal indicates that the slave is
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// ready to accept an address and associated control signals.
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output wire S_AXI_ARREADY,
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// Read data (issued by slave)
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output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
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// Read response. This signal indicates the status of the
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// read transfer.
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output wire [1 : 0] S_AXI_RRESP,
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// Read valid. This signal indicates that the channel is
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// signaling the required read data.
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output wire S_AXI_RVALID,
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// Read ready. This signal indicates that the master can
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// accept the read data and response information.
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input wire S_AXI_RREADY
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);
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// AXI4LITE signals
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg axi_awready;
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reg axi_wready;
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reg [1 : 0] axi_bresp;
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reg axi_bvalid;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg axi_arready;
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reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
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reg [1 : 0] axi_rresp;
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reg axi_rvalid;
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// Example-specific design signals
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// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
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// ADDR_LSB is used for addressing 32/64 bit registers/memories
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// ADDR_LSB = 2 for 32 bits (n downto 2)
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// ADDR_LSB = 3 for 64 bits (n downto 3)
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localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
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localparam integer OPT_MEM_ADDR_BITS = 4;
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//----------------------------------------------
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//-- Signals for user logic register space example
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//------------------------------------------------
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//-- Number of Slave Registers 32
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
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wire slv_reg_rden;
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wire slv_reg_wren;
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reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
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integer byte_index;
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// I/O Connections assignments
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assign S_AXI_AWREADY = axi_awready;
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assign S_AXI_WREADY = axi_wready;
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assign S_AXI_BRESP = axi_bresp;
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assign S_AXI_BVALID = axi_bvalid;
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assign S_AXI_ARREADY = axi_arready;
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assign S_AXI_RDATA = axi_rdata;
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assign S_AXI_RRESP = axi_rresp;
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assign S_AXI_RVALID = axi_rvalid;
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// Implement axi_awready generation
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// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
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// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
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// de-asserted when reset is low.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_awready <= 1'b0;
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end
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else
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begin
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if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
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begin
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// slave is ready to accept write address when
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// there is a valid write address and write data
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// on the write address and data bus. This design
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// expects no outstanding transactions.
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axi_awready <= 1'b1;
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end
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else
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begin
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axi_awready <= 1'b0;
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end
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end
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end
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// Implement axi_awaddr latching
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// This process is used to latch the address when both
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// S_AXI_AWVALID and S_AXI_WVALID are valid.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_awaddr <= 0;
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end
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else
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begin
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if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
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begin
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// Write Address latching
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axi_awaddr <= S_AXI_AWADDR;
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end
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end
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end
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// Implement axi_wready generation
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// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
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// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
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// de-asserted when reset is low.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_wready <= 1'b0;
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end
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else
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begin
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if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
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begin
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// slave is ready to accept write data when
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// there is a valid write address and write data
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// on the write address and data bus. This design
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// expects no outstanding transactions.
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axi_wready <= 1'b1;
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end
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else
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begin
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axi_wready <= 1'b0;
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end
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end
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end
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// Implement memory mapped register select and write logic generation
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// The write data is accepted and written to memory mapped registers when
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// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
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// select byte enables of slave registers while writing.
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// These registers are cleared when reset (active low) is applied.
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// Slave register write enable is asserted when valid address and data are available
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// and the slave is ready to accept the write address and write data.
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assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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slv_reg0 <= 0;
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slv_reg1 <= 0;
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slv_reg2 <= 0;
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slv_reg3 <= 0;
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slv_reg4 <= 0;
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slv_reg5 <= 0;
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slv_reg6 <= 0;
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slv_reg7 <= 0;
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slv_reg8 <= 0;
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slv_reg9 <= 0;
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slv_reg10 <= 0;
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slv_reg11 <= 0;
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slv_reg12 <= 0;
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slv_reg13 <= 0;
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slv_reg14 <= 0;
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slv_reg15 <= 0;
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slv_reg16 <= 0;
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slv_reg17 <= 0;
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slv_reg18 <= 0;
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slv_reg19 <= 0;
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slv_reg20 <= 0;
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slv_reg21 <= 0;
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slv_reg22 <= 0;
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slv_reg23 <= 0;
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slv_reg24 <= 0;
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slv_reg25 <= 0;
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slv_reg26 <= 0;
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slv_reg27 <= 0;
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slv_reg28 <= 0;
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slv_reg29 <= 0;
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slv_reg30 <= 0;
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slv_reg31 <= 0;
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end
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else begin
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if (slv_reg_wren)
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begin
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| 279 |
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case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
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| 280 |
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5'h00:
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| 281 |
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for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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| 282 |
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if ( S_AXI_WSTRB[byte_index] == 1 ) begin
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| 283 |
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// Respective byte enables are asserted as per write strobes
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// Slave register 0
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slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
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end
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5'h01:
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for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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| 289 |
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if ( S_AXI_WSTRB[byte_index] == 1 ) begin
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| 290 |
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// Respective byte enables are asserted as per write strobes
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| 291 |
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// Slave register 1
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slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
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end
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5'h02:
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for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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| 296 |
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if ( S_AXI_WSTRB[byte_index] == 1 ) begin
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// Respective byte enables are asserted as per write strobes
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// Slave register 2
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| 299 |
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slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
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end
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5'h03:
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|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 303 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 304 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 305 |
|
|
// Slave register 3
|
| 306 |
|
|
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 307 |
|
|
end
|
| 308 |
|
|
5'h04:
|
| 309 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 310 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 311 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 312 |
|
|
// Slave register 4
|
| 313 |
|
|
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 314 |
|
|
end
|
| 315 |
|
|
5'h05:
|
| 316 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 317 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 318 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 319 |
|
|
// Slave register 5
|
| 320 |
|
|
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 321 |
|
|
end
|
| 322 |
|
|
5'h06:
|
| 323 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 324 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 325 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 326 |
|
|
// Slave register 6
|
| 327 |
|
|
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 328 |
|
|
end
|
| 329 |
|
|
5'h07:
|
| 330 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 331 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 332 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 333 |
|
|
// Slave register 7
|
| 334 |
|
|
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 335 |
|
|
end
|
| 336 |
|
|
5'h08:
|
| 337 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 338 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 339 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 340 |
|
|
// Slave register 8
|
| 341 |
|
|
slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 342 |
|
|
end
|
| 343 |
|
|
5'h09:
|
| 344 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 345 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 346 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 347 |
|
|
// Slave register 9
|
| 348 |
|
|
slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 349 |
|
|
end
|
| 350 |
|
|
5'h0A:
|
| 351 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 352 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 353 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 354 |
|
|
// Slave register 10
|
| 355 |
|
|
slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 356 |
|
|
end
|
| 357 |
|
|
5'h0B:
|
| 358 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 359 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 360 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 361 |
|
|
// Slave register 11
|
| 362 |
|
|
slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 363 |
|
|
end
|
| 364 |
|
|
5'h0C:
|
| 365 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 366 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 367 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 368 |
|
|
// Slave register 12
|
| 369 |
|
|
slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 370 |
|
|
end
|
| 371 |
|
|
5'h0D:
|
| 372 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 373 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 374 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 375 |
|
|
// Slave register 13
|
| 376 |
|
|
slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 377 |
|
|
end
|
| 378 |
|
|
5'h0E:
|
| 379 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 380 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 381 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 382 |
|
|
// Slave register 14
|
| 383 |
|
|
slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 384 |
|
|
end
|
| 385 |
|
|
5'h0F:
|
| 386 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 387 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 388 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 389 |
|
|
// Slave register 15
|
| 390 |
|
|
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 391 |
|
|
end
|
| 392 |
|
|
5'h10:
|
| 393 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 394 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 395 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 396 |
|
|
// Slave register 16
|
| 397 |
|
|
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 398 |
|
|
end
|
| 399 |
|
|
5'h11:
|
| 400 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 401 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 402 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 403 |
|
|
// Slave register 17
|
| 404 |
|
|
slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 405 |
|
|
end
|
| 406 |
|
|
5'h12:
|
| 407 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 408 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 409 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 410 |
|
|
// Slave register 18
|
| 411 |
|
|
slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 412 |
|
|
end
|
| 413 |
|
|
5'h13:
|
| 414 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 415 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 416 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 417 |
|
|
// Slave register 19
|
| 418 |
|
|
slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 419 |
|
|
end
|
| 420 |
|
|
5'h14:
|
| 421 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 422 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 423 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 424 |
|
|
// Slave register 20
|
| 425 |
|
|
slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 426 |
|
|
end
|
| 427 |
|
|
5'h15:
|
| 428 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 429 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 430 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 431 |
|
|
// Slave register 21
|
| 432 |
|
|
slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 433 |
|
|
end
|
| 434 |
|
|
5'h16:
|
| 435 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 436 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 437 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 438 |
|
|
// Slave register 22
|
| 439 |
|
|
slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 440 |
|
|
end
|
| 441 |
|
|
5'h17:
|
| 442 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 443 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 444 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 445 |
|
|
// Slave register 23
|
| 446 |
|
|
slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 447 |
|
|
end
|
| 448 |
|
|
5'h18:
|
| 449 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 450 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 451 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 452 |
|
|
// Slave register 24
|
| 453 |
|
|
slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 454 |
|
|
end
|
| 455 |
|
|
5'h19:
|
| 456 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 457 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 458 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 459 |
|
|
// Slave register 25
|
| 460 |
|
|
slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 461 |
|
|
end
|
| 462 |
|
|
5'h1A:
|
| 463 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 464 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 465 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 466 |
|
|
// Slave register 26
|
| 467 |
|
|
slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 468 |
|
|
end
|
| 469 |
|
|
5'h1B:
|
| 470 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 471 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 472 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 473 |
|
|
// Slave register 27
|
| 474 |
|
|
slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 475 |
|
|
end
|
| 476 |
|
|
5'h1C:
|
| 477 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 478 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 479 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 480 |
|
|
// Slave register 28
|
| 481 |
|
|
slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 482 |
|
|
end
|
| 483 |
|
|
5'h1D:
|
| 484 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 485 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 486 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 487 |
|
|
// Slave register 29
|
| 488 |
|
|
slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 489 |
|
|
end
|
| 490 |
|
|
5'h1E:
|
| 491 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 492 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 493 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 494 |
|
|
// Slave register 30
|
| 495 |
|
|
slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 496 |
|
|
end
|
| 497 |
|
|
5'h1F:
|
| 498 |
|
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
| 499 |
|
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
| 500 |
|
|
// Respective byte enables are asserted as per write strobes
|
| 501 |
|
|
// Slave register 31
|
| 502 |
|
|
slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
| 503 |
|
|
end
|
| 504 |
|
|
default : begin
|
| 505 |
|
|
slv_reg0 <= slv_reg0;
|
| 506 |
|
|
slv_reg1 <= slv_reg1;
|
| 507 |
|
|
slv_reg2 <= slv_reg2;
|
| 508 |
|
|
slv_reg3 <= slv_reg3;
|
| 509 |
|
|
slv_reg4 <= slv_reg4;
|
| 510 |
|
|
slv_reg5 <= slv_reg5;
|
| 511 |
|
|
slv_reg6 <= slv_reg6;
|
| 512 |
|
|
slv_reg7 <= slv_reg7;
|
| 513 |
|
|
slv_reg8 <= slv_reg8;
|
| 514 |
|
|
slv_reg9 <= slv_reg9;
|
| 515 |
|
|
slv_reg10 <= slv_reg10;
|
| 516 |
|
|
slv_reg11 <= slv_reg11;
|
| 517 |
|
|
slv_reg12 <= slv_reg12;
|
| 518 |
|
|
slv_reg13 <= slv_reg13;
|
| 519 |
|
|
slv_reg14 <= slv_reg14;
|
| 520 |
|
|
slv_reg15 <= slv_reg15;
|
| 521 |
|
|
slv_reg16 <= slv_reg16;
|
| 522 |
|
|
slv_reg17 <= slv_reg17;
|
| 523 |
|
|
slv_reg18 <= slv_reg18;
|
| 524 |
|
|
slv_reg19 <= slv_reg19;
|
| 525 |
|
|
slv_reg20 <= slv_reg20;
|
| 526 |
|
|
slv_reg21 <= slv_reg21;
|
| 527 |
|
|
slv_reg22 <= slv_reg22;
|
| 528 |
|
|
slv_reg23 <= slv_reg23;
|
| 529 |
|
|
slv_reg24 <= slv_reg24;
|
| 530 |
|
|
slv_reg25 <= slv_reg25;
|
| 531 |
|
|
slv_reg26 <= slv_reg26;
|
| 532 |
|
|
slv_reg27 <= slv_reg27;
|
| 533 |
|
|
slv_reg28 <= slv_reg28;
|
| 534 |
|
|
slv_reg29 <= slv_reg29;
|
| 535 |
|
|
slv_reg30 <= slv_reg30;
|
| 536 |
|
|
slv_reg31 <= slv_reg31;
|
| 537 |
|
|
end
|
| 538 |
|
|
endcase
|
| 539 |
|
|
end
|
| 540 |
|
|
end
|
| 541 |
|
|
end
|
| 542 |
|
|
|
| 543 |
|
|
// Implement write response logic generation
|
| 544 |
|
|
// The write response and response valid signals are asserted by the slave
|
| 545 |
|
|
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
| 546 |
|
|
// This marks the acceptance of address and indicates the status of
|
| 547 |
|
|
// write transaction.
|
| 548 |
|
|
|
| 549 |
|
|
always @( posedge S_AXI_ACLK )
|
| 550 |
|
|
begin
|
| 551 |
|
|
if ( S_AXI_ARESETN == 1'b0 )
|
| 552 |
|
|
begin
|
| 553 |
|
|
axi_bvalid <= 0;
|
| 554 |
|
|
axi_bresp <= 2'b0;
|
| 555 |
|
|
end
|
| 556 |
|
|
else
|
| 557 |
|
|
begin
|
| 558 |
|
|
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
|
| 559 |
|
|
begin
|
| 560 |
|
|
// indicates a valid write response is available
|
| 561 |
|
|
axi_bvalid <= 1'b1;
|
| 562 |
|
|
axi_bresp <= 2'b0; // 'OKAY' response
|
| 563 |
|
|
end // work error responses in future
|
| 564 |
|
|
else
|
| 565 |
|
|
begin
|
| 566 |
|
|
if (S_AXI_BREADY && axi_bvalid)
|
| 567 |
|
|
//check if bready is asserted while bvalid is high)
|
| 568 |
|
|
//(there is a possibility that bready is always asserted high)
|
| 569 |
|
|
begin
|
| 570 |
|
|
axi_bvalid <= 1'b0;
|
| 571 |
|
|
end
|
| 572 |
|
|
end
|
| 573 |
|
|
end
|
| 574 |
|
|
end
|
| 575 |
|
|
|
| 576 |
|
|
// Implement axi_arready generation
|
| 577 |
|
|
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
| 578 |
|
|
// S_AXI_ARVALID is asserted. axi_awready is
|
| 579 |
|
|
// de-asserted when reset (active low) is asserted.
|
| 580 |
|
|
// The read address is also latched when S_AXI_ARVALID is
|
| 581 |
|
|
// asserted. axi_araddr is reset to zero on reset assertion.
|
| 582 |
|
|
|
| 583 |
|
|
always @( posedge S_AXI_ACLK )
|
| 584 |
|
|
begin
|
| 585 |
|
|
if ( S_AXI_ARESETN == 1'b0 )
|
| 586 |
|
|
begin
|
| 587 |
|
|
axi_arready <= 1'b0;
|
| 588 |
|
|
axi_araddr <= 7'b0;
|
| 589 |
|
|
end
|
| 590 |
|
|
else
|
| 591 |
|
|
begin
|
| 592 |
|
|
if (~axi_arready && S_AXI_ARVALID)
|
| 593 |
|
|
begin
|
| 594 |
|
|
// indicates that the slave has acceped the valid read address
|
| 595 |
|
|
axi_arready <= 1'b1;
|
| 596 |
|
|
// Read address latching
|
| 597 |
|
|
axi_araddr <= S_AXI_ARADDR;
|
| 598 |
|
|
end
|
| 599 |
|
|
else
|
| 600 |
|
|
begin
|
| 601 |
|
|
axi_arready <= 1'b0;
|
| 602 |
|
|
end
|
| 603 |
|
|
end
|
| 604 |
|
|
end
|
| 605 |
|
|
|
| 606 |
|
|
// Implement axi_arvalid generation
|
| 607 |
|
|
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
| 608 |
|
|
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
| 609 |
|
|
// data are available on the axi_rdata bus at this instance. The
|
| 610 |
|
|
// assertion of axi_rvalid marks the validity of read data on the
|
| 611 |
|
|
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
| 612 |
|
|
// is deasserted on reset (active low). axi_rresp and axi_rdata are
|
| 613 |
|
|
// cleared to zero on reset (active low).
|
| 614 |
|
|
always @( posedge S_AXI_ACLK )
|
| 615 |
|
|
begin
|
| 616 |
|
|
if ( S_AXI_ARESETN == 1'b0 )
|
| 617 |
|
|
begin
|
| 618 |
|
|
axi_rvalid <= 0;
|
| 619 |
|
|
axi_rresp <= 0;
|
| 620 |
|
|
end
|
| 621 |
|
|
else
|
| 622 |
|
|
begin
|
| 623 |
|
|
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
|
| 624 |
|
|
begin
|
| 625 |
|
|
// Valid read data is available at the read data bus
|
| 626 |
|
|
axi_rvalid <= 1'b1;
|
| 627 |
|
|
axi_rresp <= 2'b0; // 'OKAY' response
|
| 628 |
|
|
end
|
| 629 |
|
|
else if (axi_rvalid && S_AXI_RREADY)
|
| 630 |
|
|
begin
|
| 631 |
|
|
// Read data is accepted by the master
|
| 632 |
|
|
axi_rvalid <= 1'b0;
|
| 633 |
|
|
end
|
| 634 |
|
|
end
|
| 635 |
|
|
end
|
| 636 |
|
|
|
| 637 |
|
|
// Implement memory mapped register select and read logic generation
|
| 638 |
|
|
// Slave register read enable is asserted when valid address is available
|
| 639 |
|
|
// and the slave is ready to accept the read address.
|
| 640 |
|
|
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
|
| 641 |
|
|
always @(*)
|
| 642 |
|
|
begin
|
| 643 |
|
|
reg_data_out = 0;
|
| 644 |
|
|
// Address decoding for reading registers
|
| 645 |
|
|
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
| 646 |
|
|
5'h00 : reg_data_out = slv_reg0;
|
| 647 |
|
|
5'h01 : reg_data_out = slv_reg1;
|
| 648 |
|
|
5'h02 : reg_data_out = slv_reg2;
|
| 649 |
|
|
5'h03 : reg_data_out = slv_reg3;
|
| 650 |
|
|
5'h04 : reg_data_out = slv_reg4;
|
| 651 |
|
|
5'h05 : reg_data_out = slv_reg5;
|
| 652 |
|
|
5'h06 : reg_data_out = slv_reg6;
|
| 653 |
|
|
5'h07 : reg_data_out = slv_reg7;
|
| 654 |
|
|
5'h08 : reg_data_out = slv_reg8;
|
| 655 |
|
|
5'h09 : reg_data_out = slv_reg9;
|
| 656 |
|
|
5'h0A : reg_data_out = slv_reg10;
|
| 657 |
|
|
5'h0B : reg_data_out = slv_reg11;
|
| 658 |
|
|
5'h0C : reg_data_out = slv_reg12;
|
| 659 |
|
|
5'h0D : reg_data_out = slv_reg13;
|
| 660 |
|
|
5'h0E : reg_data_out = slv_reg14;
|
| 661 |
|
|
5'h0F : reg_data_out = slv_reg15;
|
| 662 |
|
|
5'h10 : reg_data_out = slv_reg16;
|
| 663 |
|
|
5'h11 : reg_data_out = slv_reg17;
|
| 664 |
|
|
5'h12 : reg_data_out = slv_reg18;
|
| 665 |
|
|
5'h13 : reg_data_out = slv_reg19;
|
| 666 |
|
|
5'h14 : reg_data_out = slv_reg20;
|
| 667 |
|
|
5'h15 : reg_data_out = slv_reg21;
|
| 668 |
|
|
5'h16 : reg_data_out = slv_reg22;
|
| 669 |
|
|
5'h17 : reg_data_out = slv_reg23;
|
| 670 |
|
|
5'h18 : reg_data_out = slv_reg24;
|
| 671 |
|
|
5'h19 : reg_data_out = slv_reg25;
|
| 672 |
|
|
5'h1A : reg_data_out = slv_reg26;
|
| 673 |
|
|
5'h1B : reg_data_out = slv_reg27;
|
| 674 |
|
|
5'h1C : reg_data_out = slv_reg28;
|
| 675 |
|
|
5'h1D : reg_data_out = slv_reg29;
|
| 676 |
|
|
5'h1E : reg_data_out = slv_reg30;
|
| 677 |
|
|
5'h1F : reg_data_out = slv_reg31;
|
| 678 |
|
|
default : reg_data_out = 0;
|
| 679 |
|
|
endcase
|
| 680 |
|
|
end
|
| 681 |
|
|
|
| 682 |
|
|
// Output register or memory read data
|
| 683 |
|
|
always @( posedge S_AXI_ACLK )
|
| 684 |
|
|
begin
|
| 685 |
|
|
if ( S_AXI_ARESETN == 1'b0 )
|
| 686 |
|
|
begin
|
| 687 |
|
|
axi_rdata <= 0;
|
| 688 |
|
|
end
|
| 689 |
|
|
else
|
| 690 |
|
|
begin
|
| 691 |
|
|
// When there is a valid read address (S_AXI_ARVALID) with
|
| 692 |
|
|
// acceptance of read address by the slave (axi_arready),
|
| 693 |
|
|
// output the read data
|
| 694 |
|
|
if (slv_reg_rden)
|
| 695 |
|
|
begin
|
| 696 |
|
|
axi_rdata <= reg_data_out; // register read data
|
| 697 |
|
|
end
|
| 698 |
|
|
end
|
| 699 |
|
|
end
|
| 700 |
|
|
|
| 701 |
|
|
// Add user logic here
|
| 702 |
|
|
|
| 703 |
|
|
// User logic ends
|
| 704 |
|
|
//
|
| 705 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 706 |
|
|
//
|
| 707 |
|
|
// Formal Verification section begins here.
|
| 708 |
|
|
//
|
| 709 |
|
|
// The following code was not part of the original Xilinx demo.
|
| 710 |
|
|
//
|
| 711 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 712 |
|
|
`ifdef FORMAL
|
| 713 |
|
|
localparam F_LGDEPTH = 4;
|
| 714 |
|
|
|
| 715 |
|
|
wire [(F_LGDEPTH-1):0] f_axi_awr_outstanding,
|
| 716 |
|
|
f_axi_wr_outstanding,
|
| 717 |
|
|
f_axi_rd_outstanding;
|
| 718 |
|
|
|
| 719 |
|
|
//
|
| 720 |
|
|
// Connect our slave to the AXI-lite property set
|
| 721 |
|
|
//
|
| 722 |
|
|
faxil_slave #(// .C_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
|
| 723 |
|
|
.C_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
|
| 724 |
|
|
.F_LGDEPTH(F_LGDEPTH)) properties(
|
| 725 |
|
|
.i_clk(S_AXI_ACLK),
|
| 726 |
|
|
.i_axi_reset_n(S_AXI_ARESETN),
|
| 727 |
|
|
//
|
| 728 |
|
|
.i_axi_awaddr(S_AXI_AWADDR),
|
| 729 |
|
|
.i_axi_awcache(4'h0),
|
| 730 |
|
|
.i_axi_awprot(S_AXI_AWPROT),
|
| 731 |
|
|
.i_axi_awvalid(S_AXI_AWVALID),
|
| 732 |
|
|
.i_axi_awready(S_AXI_AWREADY),
|
| 733 |
|
|
//
|
| 734 |
|
|
.i_axi_wdata(S_AXI_WDATA),
|
| 735 |
|
|
.i_axi_wstrb(S_AXI_WSTRB),
|
| 736 |
|
|
.i_axi_wvalid(S_AXI_WVALID),
|
| 737 |
|
|
.i_axi_wready(S_AXI_WREADY),
|
| 738 |
|
|
//
|
| 739 |
|
|
.i_axi_bresp(S_AXI_BRESP),
|
| 740 |
|
|
.i_axi_bvalid(S_AXI_BVALID),
|
| 741 |
|
|
.i_axi_bready(S_AXI_BREADY),
|
| 742 |
|
|
//
|
| 743 |
|
|
.i_axi_araddr(S_AXI_ARADDR),
|
| 744 |
|
|
.i_axi_arprot(S_AXI_ARPROT),
|
| 745 |
|
|
.i_axi_arcache(4'h0),
|
| 746 |
|
|
.i_axi_arvalid(S_AXI_ARVALID),
|
| 747 |
|
|
.i_axi_arready(S_AXI_ARREADY),
|
| 748 |
|
|
//
|
| 749 |
|
|
.i_axi_rdata(S_AXI_RDATA),
|
| 750 |
|
|
.i_axi_rresp(S_AXI_RRESP),
|
| 751 |
|
|
.i_axi_rvalid(S_AXI_RVALID),
|
| 752 |
|
|
.i_axi_rready(S_AXI_RREADY),
|
| 753 |
|
|
//
|
| 754 |
|
|
.f_axi_rd_outstanding(f_axi_rd_outstanding),
|
| 755 |
|
|
.f_axi_wr_outstanding(f_axi_wr_outstanding),
|
| 756 |
|
|
.f_axi_awr_outstanding(f_axi_awr_outstanding));
|
| 757 |
|
|
|
| 758 |
|
|
reg f_past_valid;
|
| 759 |
|
|
initial f_past_valid = 1'b0;
|
| 760 |
|
|
always @(posedge S_AXI_ACLK)
|
| 761 |
|
|
f_past_valid <= 1'b1;
|
| 762 |
|
|
|
| 763 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 764 |
|
|
//
|
| 765 |
|
|
//
|
| 766 |
|
|
// Properties necessary to pass induction
|
| 767 |
|
|
// --- assuming we make it that far (we won't)
|
| 768 |
|
|
//
|
| 769 |
|
|
//
|
| 770 |
|
|
always @(*)
|
| 771 |
|
|
if (S_AXI_ARESETN)
|
| 772 |
|
|
begin
|
| 773 |
|
|
assert(f_axi_rd_outstanding == ((S_AXI_RVALID)? 1:0));
|
| 774 |
|
|
assert(f_axi_wr_outstanding == ((S_AXI_BVALID)? 1:0));
|
| 775 |
|
|
end
|
| 776 |
|
|
|
| 777 |
|
|
always @(*)
|
| 778 |
|
|
assert(f_axi_awr_outstanding == f_axi_wr_outstanding);
|
| 779 |
|
|
|
| 780 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 781 |
|
|
//
|
| 782 |
|
|
//
|
| 783 |
|
|
// Cover properties
|
| 784 |
|
|
//
|
| 785 |
|
|
//
|
| 786 |
|
|
// Make sure it is possible to change our register
|
| 787 |
|
|
always @(posedge S_AXI_ACLK)
|
| 788 |
|
|
cover($changed(slv_reg0)&&(slv_reg0 == 32'hdeadbeef));
|
| 789 |
|
|
|
| 790 |
|
|
always @(posedge S_AXI_ACLK)
|
| 791 |
|
|
cover((axi_rvalid)&&(axi_rdata == 32'hdeadbeef)
|
| 792 |
|
|
&&($past(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 0)));
|
| 793 |
|
|
|
| 794 |
|
|
// Make sure it is possible to read from our register
|
| 795 |
|
|
always @(posedge S_AXI_ACLK)
|
| 796 |
|
|
cover($past(reg_data_out == slv_reg0)
|
| 797 |
|
|
&&($past(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB])==0)
|
| 798 |
|
|
&&(axi_rdata == slv_reg0));
|
| 799 |
|
|
|
| 800 |
|
|
// Performance test. See if we can retire a request on every other
|
| 801 |
|
|
// instruction
|
| 802 |
|
|
//
|
| 803 |
|
|
// --- This first pair of cover statements will pass as written
|
| 804 |
|
|
//
|
| 805 |
|
|
// First a write check
|
| 806 |
|
|
always @(posedge S_AXI_ACLK)
|
| 807 |
|
|
cover( ((S_AXI_BVALID)&&(S_AXI_BREADY))
|
| 808 |
|
|
&&(!$past((S_AXI_BVALID)&&(S_AXI_BREADY),1))
|
| 809 |
|
|
&&( $past((S_AXI_BVALID)&&(S_AXI_BREADY),2))
|
| 810 |
|
|
&&(!$past((S_AXI_BVALID)&&(S_AXI_BREADY),3)));
|
| 811 |
|
|
|
| 812 |
|
|
// Now a read check
|
| 813 |
|
|
always @(posedge S_AXI_ACLK)
|
| 814 |
|
|
cover( ((S_AXI_RVALID)&&(S_AXI_RREADY))
|
| 815 |
|
|
&&(!$past((S_AXI_RVALID)&&(S_AXI_RREADY),1))
|
| 816 |
|
|
&&( $past((S_AXI_RVALID)&&(S_AXI_RREADY),2))
|
| 817 |
|
|
&&(!$past((S_AXI_RVALID)&&(S_AXI_RREADY),3)));
|
| 818 |
|
|
|
| 819 |
|
|
// Now let's see if we can retire one value every clock tick
|
| 820 |
|
|
//
|
| 821 |
|
|
// --- These two cover statements will fail, even though the ones
|
| 822 |
|
|
// above will pass. This is why I call the design "crippled".
|
| 823 |
|
|
//
|
| 824 |
|
|
// First a write check
|
| 825 |
|
|
always @(posedge S_AXI_ACLK)
|
| 826 |
|
|
cover( ((S_AXI_BVALID)&&(S_AXI_BREADY))
|
| 827 |
|
|
&&($past((S_AXI_BVALID)&&(S_AXI_BREADY),1))
|
| 828 |
|
|
&&($past((S_AXI_BVALID)&&(S_AXI_BREADY),2))
|
| 829 |
|
|
&&($past((S_AXI_BVALID)&&(S_AXI_BREADY),3)));
|
| 830 |
|
|
|
| 831 |
|
|
// Now a read check
|
| 832 |
|
|
always @(posedge S_AXI_ACLK)
|
| 833 |
|
|
cover( ((S_AXI_RVALID)&&(S_AXI_RREADY))
|
| 834 |
|
|
&&($past((S_AXI_RVALID)&&(S_AXI_RREADY),1))
|
| 835 |
|
|
&&($past((S_AXI_RVALID)&&(S_AXI_RREADY),2))
|
| 836 |
|
|
&&($past((S_AXI_RVALID)&&(S_AXI_RREADY),3)));
|
| 837 |
|
|
|
| 838 |
|
|
// Now let's spend some time to develop a more complicated read
|
| 839 |
|
|
// trace, showing the capabilities of the core. We'll avoid the
|
| 840 |
|
|
// broken parts of the core, and just present ... something useful.
|
| 841 |
|
|
//
|
| 842 |
|
|
reg [12:0] fr_rdcover, fw_rdcover;
|
| 843 |
|
|
|
| 844 |
|
|
initial fr_rdcover = 0;
|
| 845 |
|
|
always @(posedge S_AXI_ACLK)
|
| 846 |
|
|
if (!S_AXI_ARESETN)
|
| 847 |
|
|
fr_rdcover <= 0;
|
| 848 |
|
|
else
|
| 849 |
|
|
fr_rdcover <= fw_rdcover;
|
| 850 |
|
|
|
| 851 |
|
|
always @(*)
|
| 852 |
|
|
if ((!S_AXI_ARESETN)||(S_AXI_AWVALID)||(S_AXI_WVALID))
|
| 853 |
|
|
fw_rdcover = 0;
|
| 854 |
|
|
else begin
|
| 855 |
|
|
//
|
| 856 |
|
|
// A basic read request
|
| 857 |
|
|
fw_rdcover[0] = (S_AXI_ARVALID)
|
| 858 |
|
|
&&(S_AXI_RREADY);
|
| 859 |
|
|
fw_rdcover[1] = fr_rdcover[0]
|
| 860 |
|
|
&&(S_AXI_ARVALID)
|
| 861 |
|
|
&&(S_AXI_RREADY);
|
| 862 |
|
|
fw_rdcover[2] = fr_rdcover[1]
|
| 863 |
|
|
&&(!S_AXI_ARVALID)
|
| 864 |
|
|
&&(S_AXI_RREADY);
|
| 865 |
|
|
fw_rdcover[3] = fr_rdcover[2]
|
| 866 |
|
|
&&(!S_AXI_ARVALID)
|
| 867 |
|
|
&&(S_AXI_RREADY);
|
| 868 |
|
|
fw_rdcover[4] = fr_rdcover[3]
|
| 869 |
|
|
&&(!S_AXI_ARVALID)
|
| 870 |
|
|
&&(S_AXI_RREADY);
|
| 871 |
|
|
//
|
| 872 |
|
|
// A high speed/pipelined read request
|
| 873 |
|
|
fw_rdcover[5] = fr_rdcover[4]
|
| 874 |
|
|
&&(S_AXI_ARVALID)
|
| 875 |
|
|
&&(S_AXI_RREADY);
|
| 876 |
|
|
fw_rdcover[6] = fr_rdcover[5]
|
| 877 |
|
|
&&(S_AXI_ARVALID)
|
| 878 |
|
|
&&(S_AXI_RREADY);
|
| 879 |
|
|
fw_rdcover[7] = fr_rdcover[6]
|
| 880 |
|
|
&&(S_AXI_ARVALID)
|
| 881 |
|
|
&&(S_AXI_RREADY);
|
| 882 |
|
|
fw_rdcover[8] = fr_rdcover[7]
|
| 883 |
|
|
&&(S_AXI_ARVALID)
|
| 884 |
|
|
&&(S_AXI_RREADY);
|
| 885 |
|
|
fw_rdcover[9] = fr_rdcover[8]
|
| 886 |
|
|
&&(S_AXI_ARVALID)
|
| 887 |
|
|
&&(S_AXI_RREADY);
|
| 888 |
|
|
fw_rdcover[10] = fr_rdcover[9]
|
| 889 |
|
|
&&(S_AXI_ARVALID)
|
| 890 |
|
|
&&(S_AXI_RREADY);
|
| 891 |
|
|
fw_rdcover[11] = fr_rdcover[10]
|
| 892 |
|
|
&&(!S_AXI_ARVALID)
|
| 893 |
|
|
&&(S_AXI_RREADY);
|
| 894 |
|
|
fw_rdcover[12] = fr_rdcover[11]
|
| 895 |
|
|
&&(!S_AXI_ARVALID)
|
| 896 |
|
|
&&(S_AXI_RREADY);
|
| 897 |
|
|
end
|
| 898 |
|
|
|
| 899 |
|
|
always @(*)
|
| 900 |
|
|
begin
|
| 901 |
|
|
cover(fw_rdcover[0]);
|
| 902 |
|
|
cover(fw_rdcover[1]);
|
| 903 |
|
|
cover(fw_rdcover[2]);
|
| 904 |
|
|
cover(fw_rdcover[3]);
|
| 905 |
|
|
cover(fw_rdcover[4]);
|
| 906 |
|
|
cover(fw_rdcover[5]); //
|
| 907 |
|
|
cover(fw_rdcover[6]);
|
| 908 |
|
|
cover(fw_rdcover[7]);
|
| 909 |
|
|
cover(fw_rdcover[8]);
|
| 910 |
|
|
cover(fw_rdcover[9]);
|
| 911 |
|
|
cover(fw_rdcover[10]);
|
| 912 |
|
|
cover(fw_rdcover[11]);
|
| 913 |
|
|
cover(fw_rdcover[12]);
|
| 914 |
|
|
end
|
| 915 |
|
|
|
| 916 |
|
|
//
|
| 917 |
|
|
// Now let's repeat our complicated cover approach for the write
|
| 918 |
|
|
// channel.
|
| 919 |
|
|
//
|
| 920 |
|
|
reg [24:0] fr_wrcover, fw_wrcover;
|
| 921 |
|
|
|
| 922 |
|
|
initial fr_wrcover = 0;
|
| 923 |
|
|
always @(posedge S_AXI_ACLK)
|
| 924 |
|
|
if (!S_AXI_ARESETN)
|
| 925 |
|
|
fr_wrcover <= 0;
|
| 926 |
|
|
else
|
| 927 |
|
|
fr_wrcover <= fw_wrcover;
|
| 928 |
|
|
|
| 929 |
|
|
always @(*)
|
| 930 |
|
|
if ((!S_AXI_ARESETN)||(S_AXI_ARVALID)||(!S_AXI_BREADY))
|
| 931 |
|
|
fw_wrcover = 0;
|
| 932 |
|
|
else begin
|
| 933 |
|
|
//
|
| 934 |
|
|
// A basic (synchronized) write request
|
| 935 |
|
|
fw_wrcover[0] = (S_AXI_AWVALID)
|
| 936 |
|
|
&&(S_AXI_WVALID);
|
| 937 |
|
|
fw_wrcover[1] = fr_wrcover[0]
|
| 938 |
|
|
&&(S_AXI_AWVALID)
|
| 939 |
|
|
&&(S_AXI_WVALID);
|
| 940 |
|
|
fw_wrcover[2] = fr_wrcover[1]
|
| 941 |
|
|
&&(!S_AXI_AWVALID)
|
| 942 |
|
|
&&(!S_AXI_WVALID);
|
| 943 |
|
|
fw_wrcover[3] = fr_wrcover[2]
|
| 944 |
|
|
&&(!S_AXI_AWVALID)
|
| 945 |
|
|
&&(!S_AXI_WVALID);
|
| 946 |
|
|
fw_wrcover[4] = fr_wrcover[3]
|
| 947 |
|
|
&&(!S_AXI_ARVALID)
|
| 948 |
|
|
&&(S_AXI_RREADY);
|
| 949 |
|
|
//
|
| 950 |
|
|
// Address before data
|
| 951 |
|
|
fw_wrcover[5] = fr_wrcover[4]
|
| 952 |
|
|
&&(S_AXI_AWVALID)
|
| 953 |
|
|
&&(!S_AXI_WVALID);
|
| 954 |
|
|
fw_wrcover[6] = fr_wrcover[5]
|
| 955 |
|
|
&&(S_AXI_AWVALID)
|
| 956 |
|
|
&&(!S_AXI_WVALID);
|
| 957 |
|
|
fw_wrcover[7] = fr_wrcover[6]
|
| 958 |
|
|
&&(S_AXI_AWVALID)
|
| 959 |
|
|
&&(S_AXI_WVALID);
|
| 960 |
|
|
fw_wrcover[8] = fr_wrcover[7]
|
| 961 |
|
|
&&(S_AXI_AWVALID)
|
| 962 |
|
|
&&(S_AXI_WVALID);
|
| 963 |
|
|
fw_wrcover[9] = fr_wrcover[8]
|
| 964 |
|
|
&&(!S_AXI_AWVALID)
|
| 965 |
|
|
&&(!S_AXI_WVALID);
|
| 966 |
|
|
fw_wrcover[10] = fr_wrcover[9]
|
| 967 |
|
|
&&(!S_AXI_AWVALID)
|
| 968 |
|
|
&&(!S_AXI_WVALID);
|
| 969 |
|
|
//
|
| 970 |
|
|
// Data before address
|
| 971 |
|
|
fw_wrcover[11] = fr_wrcover[10]
|
| 972 |
|
|
&&(!S_AXI_AWVALID)
|
| 973 |
|
|
&&(S_AXI_WVALID);
|
| 974 |
|
|
fw_wrcover[12] = fr_wrcover[11]
|
| 975 |
|
|
&&(S_AXI_AWVALID)
|
| 976 |
|
|
&&(S_AXI_WVALID);
|
| 977 |
|
|
fw_wrcover[13] = fr_wrcover[12]
|
| 978 |
|
|
&&(S_AXI_AWVALID)
|
| 979 |
|
|
&&(S_AXI_WVALID);
|
| 980 |
|
|
fw_wrcover[14] = fr_wrcover[13]
|
| 981 |
|
|
&&(!S_AXI_AWVALID)
|
| 982 |
|
|
&&(!S_AXI_WVALID);
|
| 983 |
|
|
fw_wrcover[15] = fr_wrcover[14]
|
| 984 |
|
|
&&(!S_AXI_AWVALID)
|
| 985 |
|
|
&&(!S_AXI_WVALID);
|
| 986 |
|
|
//
|
| 987 |
|
|
// A high speed/pipelined read request
|
| 988 |
|
|
fw_wrcover[16] = fr_wrcover[15]
|
| 989 |
|
|
&&(S_AXI_AWVALID)
|
| 990 |
|
|
&&(S_AXI_WVALID);
|
| 991 |
|
|
fw_wrcover[17] = fr_wrcover[16]
|
| 992 |
|
|
&&(S_AXI_AWVALID)
|
| 993 |
|
|
&&(S_AXI_WVALID);
|
| 994 |
|
|
fw_wrcover[18] = fr_wrcover[17]
|
| 995 |
|
|
&&(S_AXI_AWVALID)
|
| 996 |
|
|
&&(S_AXI_WVALID);
|
| 997 |
|
|
fw_wrcover[19] = fr_wrcover[18]
|
| 998 |
|
|
&&(S_AXI_AWVALID)
|
| 999 |
|
|
&&(S_AXI_WVALID);
|
| 1000 |
|
|
fw_wrcover[20] = fr_wrcover[19]
|
| 1001 |
|
|
&&(S_AXI_AWVALID)
|
| 1002 |
|
|
&&(S_AXI_WVALID);
|
| 1003 |
|
|
fw_wrcover[21] = fr_wrcover[20]
|
| 1004 |
|
|
&&(S_AXI_AWVALID)
|
| 1005 |
|
|
&&(S_AXI_WVALID);
|
| 1006 |
|
|
fw_wrcover[22] = fr_wrcover[21]
|
| 1007 |
|
|
&&(!S_AXI_AWVALID)
|
| 1008 |
|
|
&&(!S_AXI_WVALID);
|
| 1009 |
|
|
fw_wrcover[23] = fr_wrcover[22]
|
| 1010 |
|
|
&&(!S_AXI_AWVALID)
|
| 1011 |
|
|
&&(!S_AXI_WVALID);
|
| 1012 |
|
|
fw_wrcover[24] = fr_wrcover[23]
|
| 1013 |
|
|
&&(!S_AXI_AWVALID)
|
| 1014 |
|
|
&&(!S_AXI_WVALID);
|
| 1015 |
|
|
end
|
| 1016 |
|
|
|
| 1017 |
|
|
always @(*)
|
| 1018 |
|
|
begin
|
| 1019 |
|
|
cover(fw_wrcover[0]);
|
| 1020 |
|
|
cover(fw_wrcover[1]);
|
| 1021 |
|
|
cover(fw_wrcover[2]);
|
| 1022 |
|
|
cover(fw_wrcover[3]);
|
| 1023 |
|
|
cover(fw_wrcover[4]);
|
| 1024 |
|
|
cover(fw_wrcover[5]); //
|
| 1025 |
|
|
cover(fw_wrcover[6]);
|
| 1026 |
|
|
cover(fw_wrcover[7]);
|
| 1027 |
|
|
cover(fw_wrcover[8]);
|
| 1028 |
|
|
cover(fw_wrcover[9]);
|
| 1029 |
|
|
cover(fw_wrcover[11]);
|
| 1030 |
|
|
cover(fw_wrcover[12]);
|
| 1031 |
|
|
cover(fw_wrcover[13]);
|
| 1032 |
|
|
cover(fw_wrcover[14]);
|
| 1033 |
|
|
cover(fw_wrcover[15]);
|
| 1034 |
|
|
cover(fw_wrcover[16]);
|
| 1035 |
|
|
cover(fw_wrcover[17]);
|
| 1036 |
|
|
cover(fw_wrcover[18]);
|
| 1037 |
|
|
cover(fw_wrcover[19]);
|
| 1038 |
|
|
cover(fw_wrcover[20]);
|
| 1039 |
|
|
cover(fw_wrcover[21]);
|
| 1040 |
|
|
cover(fw_wrcover[22]);
|
| 1041 |
|
|
cover(fw_wrcover[23]);
|
| 1042 |
|
|
cover(fw_wrcover[24]);
|
| 1043 |
|
|
end
|
| 1044 |
|
|
`endif
|
| 1045 |
|
|
//
|
| 1046 |
|
|
//
|
| 1047 |
|
|
// Bug fixes section
|
| 1048 |
|
|
//
|
| 1049 |
|
|
// The lines below contain assumptions necessary to get the design
|
| 1050 |
|
|
// to work. They represent things Xilinx never thought of when
|
| 1051 |
|
|
// building their demo.
|
| 1052 |
|
|
//
|
| 1053 |
|
|
// The following lines are only questionable a bug
|
| 1054 |
|
|
initial axi_arready = 1'b0;
|
| 1055 |
|
|
initial axi_awready = 1'b0;
|
| 1056 |
|
|
initial axi_wready = 1'b0;
|
| 1057 |
|
|
initial axi_bvalid = 1'b0;
|
| 1058 |
|
|
initial axi_rvalid = 1'b0;
|
| 1059 |
|
|
|
| 1060 |
|
|
//
|
| 1061 |
|
|
// This here is necessary to avoid the biggest bug within the design.
|
| 1062 |
|
|
//
|
| 1063 |
|
|
// If you uncomment the following two lines, the design will work as
|
| 1064 |
|
|
// intended. Only ... the bus now has more requirements to it.
|
| 1065 |
|
|
//
|
| 1066 |
|
|
// always @(posedge S_AXI_ACLK)
|
| 1067 |
|
|
// if ($past(S_AXI_ARESETN))
|
| 1068 |
|
|
// assume((S_AXI_RREADY)&&(S_AXI_BREADY));
|
| 1069 |
|
|
|
| 1070 |
|
|
// verilator lint_off UNUSED
|
| 1071 |
|
|
wire [9:0] unused;
|
| 1072 |
|
|
assign unused = { S_AXI_ARPROT, S_AXI_AWPROT,
|
| 1073 |
|
|
axi_awaddr[1:0], axi_araddr[1:0] };
|
| 1074 |
|
|
// verilator lint_on UNUSED
|
| 1075 |
|
|
endmodule
|
