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dgisselq |
################################################################################
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##
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## Filename: Makefile
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##
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## Project: Pipelined Wishbone to AXI converter
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##
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## Purpose: To describe how to build the Verilator libraries from the
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## RTL, for the purposes of trying to discover if they work.
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## Any actual testing will be done from the code within the bench/cpp
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## directory.
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##
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## Targets: The default target, all, builds the target test, which includes
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## the libraries necessary for Verilator testing.
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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##
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dgisselq |
## Copyright (C) 2016,2018, Gisselquist Technology, LLC
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##
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## This file is part of the pipelined Wishbone to AXI converter project, a
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## project that contains multiple bus bridging designs and formal bus property
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## sets.
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##
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## The bus bridge designs and property sets are free RTL designs: you can
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## redistribute them and/or modify any of them under the terms of the GNU
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## Lesser General Public License as published by the Free Software Foundation,
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## either version 3 of the License, or (at your option) any later version.
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##
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## The bus bridge designs and property sets are distributed in the hope that
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## they will be useful, but WITHOUT ANY WARRANTY; without even the implied
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## warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU Lesser General Public License for more details.
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##
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## You should have received a copy of the GNU Lesser General Public License
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## along with these designs. (It's in the $(ROOT)/doc directory. Run make
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## with no target there if the PDF file isn't present.) If not, see
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## for a copy.
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##
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## License: LGPL, v3, as defined and found on www.gnu.org,
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## http://www.gnu.org/licenses/lgpl.html
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##
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################################################################################
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##
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##
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all: test
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YYMMDD=`date +%Y%m%d`
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CXX := g++
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FBDIR := .
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VDIRFB:= $(FBDIR)/obj_dir
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.PHONY: test
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test: testwb
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.PHONY: testwb
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.PHONY: testaxi
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.PHONY: wbm2axisp
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wbm2axisp: testwb
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.PHONY: axim2wbsp
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axim2wbsp: testaxi
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.PHONY: axilite
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testwb: $(VDIRFB)/Vwbm2axisp__ALL.a
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testaxi: $(VDIRFB)/Vaxim2wbsp__ALL.a
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axilite: $(VDIRFB)/Vwbm2axilite__ALL.a
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axilite: $(VDIRFB)/Vaxilrd2wbsp__ALL.a
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axilite: $(VDIRFB)/Vaxilwr2wbsp__ALL.a
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axilite: $(VDIRFB)/Vaxlite2wbsp__ALL.a
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.PHONY: wbm2axisp
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wbm2axisp: $(VDIRFB)/Vwbm2axisp__ALL.a
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$(VDIRFB)/Vwbm2axisp__ALL.a: $(VDIRFB)/Vwbm2axisp.h $(VDIRFB)/Vwbm2axisp.cpp
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$(VDIRFB)/Vwbm2axisp__ALL.a: $(VDIRFB)/Vwbm2axisp.mk
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$(VDIRFB)/Vwbm2axisp.h $(VDIRFB)/Vwbm2axisp.cpp $(VDIRFB)/Vwbm2axisp.mk: wbm2axisp.v
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.PHONY: wbm2axilite
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wbm2axilite: $(VDIRFB)/Vwbm2axilite__ALL.a
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$(VDIRFB)/Vwbm2axilite__ALL.a: $(VDIRFB)/Vwbm2axilite.h $(VDIRFB)/Vwbm2axilite.cpp
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$(VDIRFB)/Vwbm2axilite__ALL.a: $(VDIRFB)/Vwbm2axilite.mk
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$(VDIRFB)/Vwbm2axilite.h $(VDIRFB)/Vwbm2axilite.cpp $(VDIRFB)/Vwbm2axilite.mk: wbm2axilite.v
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.PHONY: axilrd2wbsp
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axilrd2wbsp: $(VDIRFB)/Vaxilrd2wbsp__ALL.a
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$(VDIRFB)/Vaxilrd2wbsp__ALL.a: $(VDIRFB)/Vaxilrd2wbsp.h $(VDIRFB)/Vaxilrd2wbsp.cpp
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$(VDIRFB)/Vaxilrd2wbsp__ALL.a: $(VDIRFB)/Vaxilrd2wbsp.mk
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$(VDIRFB)/Vaxilrd2wbsp.h $(VDIRFB)/Vaxilrd2wbsp.cpp $(VDIRFB)/Vaxilrd2wbsp.mk: axilrd2wbsp.v
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.PHONY: axilwr2wbsp
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axilwr2wbsp: $(VDIRFB)/Vaxilwr2wbsp__ALL.a
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$(VDIRFB)/Vaxilwr2wbsp__ALL.a: $(VDIRFB)/Vaxilwr2wbsp.h $(VDIRFB)/Vaxilwr2wbsp.cpp
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$(VDIRFB)/Vaxilwr2wbsp__ALL.a: $(VDIRFB)/Vaxilwr2wbsp.mk
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$(VDIRFB)/Vaxilwr2wbsp.h $(VDIRFB)/Vaxilwr2wbsp.cpp $(VDIRFB)/Vaxilwr2wbsp.mk: axilwr2wbsp.v
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.PHONY: axlite2wbsp
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axlite2wbsp: $(VDIRFB)/Vaxlite2wbsp__ALL.a
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$(VDIRFB)/Vaxlite2wbsp__ALL.a: $(VDIRFB)/Vaxlite2wbsp.h $(VDIRFB)/Vaxlite2wbsp.cpp
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$(VDIRFB)/Vaxlite2wbsp__ALL.a: $(VDIRFB)/Vaxlite2wbsp.mk
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$(VDIRFB)/Vaxlite2wbsp.h $(VDIRFB)/Vaxlite2wbsp.cpp $(VDIRFB)/Vaxlite2wbsp.mk: axlite2wbsp.v
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$(VDIRFB)/Vaxim2wbsp__ALL.a: $(VDIRFB)/Vaxim2wbsp.h $(VDIRFB)/Vaxim2wbsp.cpp
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$(VDIRFB)/Vaxim2wbsp__ALL.a: $(VDIRFB)/Vaxim2wbsp.mk
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$(VDIRFB)/Vaxim2wbsp.h $(VDIRFB)/Vaxim2wbsp.cpp $(VDIRFB)/Vaxim2wbsp.mk: \
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axim2wbsp.v aximrd2wbsp.v aximwr2wbsp.v wbarbiter.v
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$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
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verilator -cc $*.v
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$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
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cd $(VDIRFB); make -f V$*.mk
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.PHONY: clean
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clean:
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rm -rf $(VDIRFB)/*.mk
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rm -rf $(VDIRFB)/*.cpp
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rm -rf $(VDIRFB)/*.h
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rm -rf $(VDIRFB)/
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