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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: axlite2wbsp.v
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//
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// Project: Pipelined Wishbone to AXI converter
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//
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// Purpose: Take an AXI lite input, and convert it into WB.
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//
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// We'll treat AXI as two separate busses: one for writes, another for
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// reads, further, we'll insist that the two channels AXI uses for writes
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// combine into one channel for our purposes.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016-2019, Gisselquist Technology, LLC
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//
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// This file is part of the pipelined Wishbone to AXI converter project, a
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// project that contains multiple bus bridging designs and formal bus property
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// sets.
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//
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// The bus bridge designs and property sets are free RTL designs: you can
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// redistribute them and/or modify any of them under the terms of the GNU
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// Lesser General Public License as published by the Free Software Foundation,
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// either version 3 of the License, or (at your option) any later version.
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//
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// The bus bridge designs and property sets are distributed in the hope that
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// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with these designs. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/lgpl.html
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module axlite2wbsp( i_clk, i_axi_reset_n,
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//
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o_axi_awready, i_axi_awaddr, i_axi_awcache, i_axi_awprot,i_axi_awvalid,
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//
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o_axi_wready, i_axi_wdata, i_axi_wstrb, i_axi_wvalid,
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//
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o_axi_bresp, o_axi_bvalid, i_axi_bready,
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//
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o_axi_arready, i_axi_araddr, i_axi_arcache, i_axi_arprot, i_axi_arvalid,
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//
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o_axi_rresp, o_axi_rvalid, o_axi_rdata, i_axi_rready,
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//
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// Wishbone interface
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o_reset, o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
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//
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parameter C_AXI_DATA_WIDTH = 32;// Width of the AXI R&W data
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parameter C_AXI_ADDR_WIDTH = 28; // AXI Address width
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parameter LGFIFO = 4;
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parameter F_MAXSTALL = 3;
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parameter F_MAXDELAY = 3;
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parameter [0:0] OPT_READONLY = 1'b0;
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parameter [0:0] OPT_WRITEONLY = 1'b0;
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localparam F_LGDEPTH = LGFIFO+1;
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//
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input wire i_clk; // System clock
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input wire i_axi_reset_n;
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// AXI write address channel signals
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output wire o_axi_awready;//Slave is ready to accept
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input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_awaddr; // Write address
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input wire [3:0] i_axi_awcache; // Write Cache type
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input wire [2:0] i_axi_awprot; // Write Protection type
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input wire i_axi_awvalid; // Write address valid
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// AXI write data channel signals
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output wire o_axi_wready; // Write data ready
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input wire [C_AXI_DATA_WIDTH-1:0] i_axi_wdata; // Write data
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input wire [C_AXI_DATA_WIDTH/8-1:0] i_axi_wstrb; // Write strobes
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input wire i_axi_wvalid; // Write valid
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// AXI write response channel signals
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output wire [1:0] o_axi_bresp; // Write response
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output wire o_axi_bvalid; // Write reponse valid
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input wire i_axi_bready; // Response ready
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// AXI read address channel signals
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output wire o_axi_arready; // Read address ready
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input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_araddr; // Read address
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input wire [3:0] i_axi_arcache; // Read Cache type
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input wire [2:0] i_axi_arprot; // Read Protection type
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input wire i_axi_arvalid; // Read address valid
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// AXI read data channel signals
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output wire [1:0] o_axi_rresp; // Read response
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output wire o_axi_rvalid; // Read reponse valid
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output wire [C_AXI_DATA_WIDTH-1:0] o_axi_rdata; // Read data
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input wire i_axi_rready; // Read Response ready
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// We'll share the clock and the reset
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output wire o_reset;
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output wire o_wb_cyc;
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output wire o_wb_stb;
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output wire o_wb_we;
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output wire [(C_AXI_ADDR_WIDTH-3):0] o_wb_addr;
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output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data;
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output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel;
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input wire i_wb_ack;
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input wire i_wb_stall;
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input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data;
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input wire i_wb_err;
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localparam DW = C_AXI_DATA_WIDTH;
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localparam AW = C_AXI_ADDR_WIDTH-2;
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//
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//
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//
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wire [(AW-1):0] w_wb_addr, r_wb_addr;
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wire [(C_AXI_DATA_WIDTH-1):0] w_wb_data;
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wire [(C_AXI_DATA_WIDTH/8-1):0] w_wb_sel;
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wire r_wb_err, r_wb_cyc, r_wb_stb, r_wb_stall, r_wb_ack;
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wire w_wb_err, w_wb_cyc, w_wb_stb, w_wb_stall, w_wb_ack;
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// verilator lint_off UNUSED
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wire r_wb_we, w_wb_we;
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assign r_wb_we = 1'b0;
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assign w_wb_we = 1'b1;
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// verilator lint_on UNUSED
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`ifdef FORMAL
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wire [LGFIFO:0] f_wr_fifo_first, f_rd_fifo_first,
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f_wr_fifo_mid, f_rd_fifo_mid,
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f_wr_fifo_last, f_rd_fifo_last;
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wire [(F_LGDEPTH-1):0] f_wb_nreqs, f_wb_nacks,
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f_wb_outstanding;
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wire [(F_LGDEPTH-1):0] f_wb_wr_nreqs, f_wb_wr_nacks,
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f_wb_wr_outstanding;
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wire [(F_LGDEPTH-1):0] f_wb_rd_nreqs, f_wb_rd_nacks,
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f_wb_rd_outstanding;
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wire f_pending_awvalid, f_pending_wvalid;
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`endif
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//
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// AXI-lite write channel to WB processing
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//
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generate if (!OPT_READONLY)
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begin : AXI_WR
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axilwr2wbsp #(
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// .F_LGDEPTH(F_LGDEPTH),
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// .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
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.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), // .AW(AW),
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.LGFIFO(LGFIFO))
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axi_write_decoder(
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.i_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
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//
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.o_axi_awready(o_axi_awready),
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.i_axi_awaddr( i_axi_awaddr),
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.i_axi_awcache(i_axi_awcache),
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.i_axi_awprot( i_axi_awprot),
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.i_axi_awvalid(i_axi_awvalid),
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//
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.o_axi_wready( o_axi_wready),
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.i_axi_wdata( i_axi_wdata),
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.i_axi_wstrb( i_axi_wstrb),
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.i_axi_wvalid( i_axi_wvalid),
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//
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.o_axi_bresp(o_axi_bresp),
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.o_axi_bvalid(o_axi_bvalid),
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.i_axi_bready(i_axi_bready),
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//
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.o_wb_cyc( w_wb_cyc),
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.o_wb_stb( w_wb_stb),
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.o_wb_addr( w_wb_addr),
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.o_wb_data( w_wb_data),
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.o_wb_sel( w_wb_sel),
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.i_wb_ack( w_wb_ack),
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.i_wb_stall(w_wb_stall),
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.i_wb_err( w_wb_err)
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`ifdef FORMAL
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,
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.f_first(f_wr_fifo_first),
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.f_mid( f_wr_fifo_mid),
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.f_last( f_wr_fifo_last),
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.f_wpending({ f_pending_awvalid, f_pending_wvalid })
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`endif
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);
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end else begin
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assign w_wb_cyc = 0;
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assign w_wb_stb = 0;
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assign w_wb_addr = 0;
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assign w_wb_data = 0;
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assign w_wb_sel = 0;
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assign o_axi_awready = 0;
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assign o_axi_wready = 0;
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assign o_axi_bvalid = (i_axi_wvalid);
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assign o_axi_bresp = 2'b11;
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`ifdef FORMAL
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assign f_wr_fifo_first = 0;
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assign f_wr_fifo_mid = 0;
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assign f_wr_fifo_last = 0;
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assign f_pending_awvalid=0;
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assign f_pending_wvalid =0;
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`endif
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end endgenerate
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assign w_wb_we = 1'b1;
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//
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// AXI-lite read channel to WB processing
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//
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generate if (!OPT_WRITEONLY)
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begin : AXI_RD
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axilrd2wbsp #(
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// .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
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.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
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.LGFIFO(LGFIFO))
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axi_read_decoder(
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.i_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
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//
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.o_axi_arready(o_axi_arready),
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.i_axi_araddr( i_axi_araddr),
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.i_axi_arcache(i_axi_arcache),
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.i_axi_arprot( i_axi_arprot),
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.i_axi_arvalid(i_axi_arvalid),
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//
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.o_axi_rresp( o_axi_rresp),
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.o_axi_rvalid(o_axi_rvalid),
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.o_axi_rdata( o_axi_rdata),
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.i_axi_rready(i_axi_rready),
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//
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.o_wb_cyc( r_wb_cyc),
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.o_wb_stb( r_wb_stb),
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.o_wb_addr( r_wb_addr),
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.i_wb_ack( r_wb_ack),
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.i_wb_stall(r_wb_stall),
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.i_wb_data( i_wb_data),
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.i_wb_err( r_wb_err)
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`ifdef FORMAL
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,
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.f_first(f_rd_fifo_first),
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.f_mid( f_rd_fifo_mid),
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.f_last( f_rd_fifo_last)
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`endif
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);
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end else begin
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assign r_wb_cyc = 0;
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assign r_wb_stb = 0;
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assign r_wb_addr = 0;
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//
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assign o_axi_arready = 1'b1;
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assign o_axi_rvalid = (i_axi_arvalid)&&(o_axi_arready);
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assign o_axi_rresp = (i_axi_arvalid) ? 2'b11 : 2'b00;
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assign o_axi_rdata = 0;
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`ifdef FORMAL
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assign f_rd_fifo_first = 0;
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assign f_rd_fifo_mid = 0;
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assign f_rd_fifo_last = 0;
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`endif
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end endgenerate
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//
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//
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// The arbiter that pastes the two sides together
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//
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//
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generate if (OPT_READONLY)
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begin : ARB_RD
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assign o_wb_cyc = r_wb_cyc;
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assign o_wb_stb = r_wb_stb;
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assign o_wb_we = 1'b0;
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assign o_wb_addr = r_wb_addr;
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assign o_wb_data = 32'h0;
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assign o_wb_sel = 0;
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assign r_wb_ack = i_wb_ack;
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assign r_wb_stall= i_wb_stall;
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assign r_wb_ack = i_wb_ack;
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assign r_wb_err = i_wb_err;
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`ifdef FORMAL
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fwb_master #(.DW(DW), .AW(AW),
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.F_LGDEPTH(F_LGDEPTH),
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.F_MAX_STALL(F_MAXSTALL),
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.F_MAX_ACK_DELAY(F_MAXDELAY))
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f_wb(i_clk, !i_axi_reset_n,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
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assign f_wb_rd_nreqs = f_wb_nreqs;
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assign f_wb_rd_nacks = f_wb_nacks;
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assign f_wb_rd_outstanding = f_wb_outstanding;
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//
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assign f_wb_wr_nreqs = 0;
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assign f_wb_wr_nacks = 0;
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assign f_wb_wr_outstanding = 0;
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`endif
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end else if (OPT_WRITEONLY)
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begin : ARB_WR
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assign o_wb_cyc = w_wb_cyc;
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assign o_wb_stb = w_wb_stb;
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311 |
|
|
assign o_wb_we = 1'b1;
|
312 |
|
|
assign o_wb_addr = w_wb_addr;
|
313 |
|
|
assign o_wb_data = w_wb_data;
|
314 |
|
|
assign o_wb_sel = w_wb_sel;
|
315 |
|
|
assign w_wb_ack = i_wb_ack;
|
316 |
|
|
assign w_wb_stall= i_wb_stall;
|
317 |
|
|
assign w_wb_ack = i_wb_ack;
|
318 |
|
|
assign w_wb_err = i_wb_err;
|
319 |
|
|
|
320 |
|
|
`ifdef FORMAL
|
321 |
|
|
fwb_master #(.DW(DW), .AW(AW),
|
322 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
323 |
|
|
.F_MAX_STALL(F_MAXSTALL),
|
324 |
|
|
.F_MAX_ACK_DELAY(F_MAXDELAY))
|
325 |
|
|
f_wb(i_clk, !i_axi_reset_n,
|
326 |
|
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
327 |
|
|
o_wb_sel,
|
328 |
|
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
|
329 |
|
|
f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
|
330 |
|
|
|
331 |
|
|
assign f_wb_wr_nreqs = f_wb_nreqs;
|
332 |
|
|
assign f_wb_wr_nacks = f_wb_nacks;
|
333 |
|
|
assign f_wb_wr_outstanding = f_wb_outstanding;
|
334 |
|
|
//
|
335 |
|
|
assign f_wb_rd_nreqs = 0;
|
336 |
|
|
assign f_wb_rd_nacks = 0;
|
337 |
|
|
assign f_wb_rd_outstanding = 0;
|
338 |
|
|
`endif
|
339 |
|
|
end else begin : ARB_WB
|
340 |
|
|
wbarbiter #(.DW(DW), .AW(AW),
|
341 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
342 |
|
|
.F_MAX_STALL(F_MAXSTALL),
|
343 |
|
|
.F_MAX_ACK_DELAY(F_MAXDELAY))
|
344 |
|
|
readorwrite(i_clk, !i_axi_reset_n,
|
345 |
|
|
r_wb_cyc, r_wb_stb, 1'b0, r_wb_addr, w_wb_data, w_wb_sel,
|
346 |
|
|
r_wb_ack, r_wb_stall, r_wb_err,
|
347 |
|
|
w_wb_cyc, w_wb_stb, 1'b1, w_wb_addr, w_wb_data, w_wb_sel,
|
348 |
|
|
w_wb_ack, w_wb_stall, w_wb_err,
|
349 |
|
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
|
350 |
|
|
i_wb_ack, i_wb_stall, i_wb_err
|
351 |
|
|
`ifdef FORMAL
|
352 |
|
|
,
|
353 |
|
|
f_wb_rd_nreqs, f_wb_rd_nacks, f_wb_rd_outstanding,
|
354 |
|
|
f_wb_wr_nreqs, f_wb_wr_nacks, f_wb_wr_outstanding,
|
355 |
|
|
f_wb_nreqs, f_wb_nacks, f_wb_outstanding
|
356 |
|
|
`endif
|
357 |
|
|
);
|
358 |
|
|
end endgenerate
|
359 |
|
|
|
360 |
|
|
assign o_reset = (i_axi_reset_n == 1'b0);
|
361 |
|
|
|
362 |
|
|
`ifdef FORMAL
|
363 |
|
|
reg f_past_valid;
|
364 |
|
|
|
365 |
|
|
initial f_past_valid = 1'b0;
|
366 |
|
|
always @(posedge i_clk)
|
367 |
|
|
f_past_valid = 1'b1;
|
368 |
|
|
|
369 |
|
|
initial assume(!i_axi_reset_n);
|
370 |
|
|
always @(*)
|
371 |
|
|
if (!f_past_valid)
|
372 |
|
|
assume(!i_axi_reset_n);
|
373 |
|
|
|
374 |
|
|
wire [(F_LGDEPTH-1):0] f_axi_rd_outstanding,
|
375 |
|
|
f_axi_wr_outstanding,
|
376 |
|
|
f_axi_awr_outstanding;
|
377 |
|
|
wire [(F_LGDEPTH-1):0] f_axi_rd_id_outstanding,
|
378 |
|
|
f_axi_awr_id_outstanding,
|
379 |
|
|
f_axi_wr_id_outstanding;
|
380 |
|
|
wire [8:0] f_axi_wr_pending,
|
381 |
|
|
f_axi_rd_count,
|
382 |
|
|
f_axi_wr_count;
|
383 |
|
|
|
384 |
|
|
faxil_slave #(
|
385 |
|
|
// .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
|
386 |
|
|
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
|
387 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
388 |
|
|
.F_AXI_MAXWAIT(0),
|
389 |
|
|
.F_AXI_MAXDELAY(0))
|
390 |
|
|
f_axi(.i_clk(i_clk), .i_axi_reset_n(i_axi_reset_n),
|
391 |
|
|
// AXI write address channnel
|
392 |
|
|
.i_axi_awready(o_axi_awready),
|
393 |
|
|
.i_axi_awaddr( i_axi_awaddr),
|
394 |
|
|
.i_axi_awcache(i_axi_awcache),
|
395 |
|
|
.i_axi_awprot( i_axi_awprot),
|
396 |
|
|
.i_axi_awvalid(i_axi_awvalid),
|
397 |
|
|
// AXI write data channel
|
398 |
|
|
.i_axi_wready( o_axi_wready),
|
399 |
|
|
.i_axi_wdata( i_axi_wdata),
|
400 |
|
|
.i_axi_wstrb( i_axi_wstrb),
|
401 |
|
|
.i_axi_wvalid( i_axi_wvalid),
|
402 |
|
|
// AXI write acknowledgement channel
|
403 |
|
|
.i_axi_bresp( o_axi_bresp),
|
404 |
|
|
.i_axi_bvalid(o_axi_bvalid),
|
405 |
|
|
.i_axi_bready(i_axi_bready),
|
406 |
|
|
// AXI read address channel
|
407 |
|
|
.i_axi_arready(o_axi_arready),
|
408 |
|
|
.i_axi_araddr( i_axi_araddr),
|
409 |
|
|
.i_axi_arcache(i_axi_arcache),
|
410 |
|
|
.i_axi_arprot( i_axi_arprot),
|
411 |
|
|
.i_axi_arvalid(i_axi_arvalid),
|
412 |
|
|
// AXI read data return
|
413 |
|
|
.i_axi_rresp( o_axi_rresp),
|
414 |
|
|
.i_axi_rvalid( o_axi_rvalid),
|
415 |
|
|
.i_axi_rdata( o_axi_rdata),
|
416 |
|
|
.i_axi_rready( i_axi_rready),
|
417 |
|
|
// Quantify where we are within a transaction
|
418 |
|
|
.f_axi_rd_outstanding( f_axi_rd_outstanding),
|
419 |
|
|
.f_axi_wr_outstanding( f_axi_wr_outstanding),
|
420 |
|
|
.f_axi_awr_outstanding(f_axi_awr_outstanding));
|
421 |
|
|
|
422 |
|
|
wire f_axi_ard_req, f_axi_awr_req, f_axi_wr_req,
|
423 |
|
|
f_axi_rd_ack, f_axi_wr_ack;
|
424 |
|
|
|
425 |
|
|
assign f_axi_ard_req = (i_axi_arvalid)&&(o_axi_arready);
|
426 |
|
|
assign f_axi_awr_req = (i_axi_awvalid)&&(o_axi_awready);
|
427 |
|
|
assign f_axi_wr_req = (i_axi_wvalid)&&(o_axi_wready);
|
428 |
|
|
assign f_axi_wr_ack = (o_axi_bvalid)&&(i_axi_bready);
|
429 |
|
|
assign f_axi_rd_ack = (o_axi_rvalid)&&(i_axi_rready);
|
430 |
|
|
|
431 |
|
|
wire [LGFIFO:0] f_awr_fifo_axi_used,
|
432 |
|
|
f_dwr_fifo_axi_used,
|
433 |
|
|
f_rd_fifo_axi_used,
|
434 |
|
|
f_wr_fifo_wb_outstanding,
|
435 |
|
|
f_rd_fifo_wb_outstanding;
|
436 |
|
|
|
437 |
|
|
assign f_awr_fifo_axi_used = f_wr_fifo_first - f_wr_fifo_last;
|
438 |
|
|
assign f_rd_fifo_axi_used = f_rd_fifo_first - f_rd_fifo_last;
|
439 |
|
|
assign f_wr_fifo_wb_outstanding = f_wr_fifo_first - f_wr_fifo_last;
|
440 |
|
|
assign f_rd_fifo_wb_outstanding = f_rd_fifo_first - f_rd_fifo_last;
|
441 |
|
|
|
442 |
|
|
always @(*)
|
443 |
|
|
begin
|
444 |
|
|
assert(f_axi_rd_outstanding == f_rd_fifo_axi_used);
|
445 |
|
|
assert(f_axi_awr_outstanding == f_awr_fifo_axi_used+ (f_pending_awvalid?1:0));
|
446 |
|
|
assert(f_axi_wr_outstanding == f_awr_fifo_axi_used+ (f_pending_wvalid?1:0));
|
447 |
|
|
end
|
448 |
|
|
|
449 |
|
|
always @(*)
|
450 |
|
|
if (OPT_READONLY)
|
451 |
|
|
begin
|
452 |
|
|
assert(f_axi_awr_outstanding == 0);
|
453 |
|
|
assert(f_axi_wr_outstanding == 0);
|
454 |
|
|
end
|
455 |
|
|
|
456 |
|
|
always @(*)
|
457 |
|
|
if (OPT_WRITEONLY)
|
458 |
|
|
begin
|
459 |
|
|
assert(f_axi_ard_outstanding == 0);
|
460 |
|
|
end
|
461 |
|
|
|
462 |
|
|
//
|
463 |
|
|
initial assert((!OPT_READONLY)||(!OPT_WRITEONLY));
|
464 |
|
|
|
465 |
|
|
always @(*)
|
466 |
|
|
if (OPT_READONLY)
|
467 |
|
|
begin
|
468 |
|
|
assume(i_axi_awvalid == 0);
|
469 |
|
|
assume(i_axi_wvalid == 0);
|
470 |
|
|
|
471 |
|
|
assert(o_axi_bvalid == 0);
|
472 |
|
|
end
|
473 |
|
|
|
474 |
|
|
always @(*)
|
475 |
|
|
if (OPT_WRITEONLY)
|
476 |
|
|
begin
|
477 |
|
|
assume(i_axi_arvalid == 0);
|
478 |
|
|
assert(o_axi_rvalid == 0);
|
479 |
|
|
end
|
480 |
|
|
`endif
|
481 |
|
|
endmodule
|
482 |
|
|
|