OpenCores
URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [rtl/] [demoaxi.v] - Blame information for rev 16

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    demoaxi.v
4
//
5
// Project:     Pipelined Wishbone to AXI converter
6
//
7
// Purpose:     Demonstrate an AXI-lite bus design.  The goal of this design
8
//              is to support a completely pipelined AXI-lite transaction
9
//      which can transfer one data item per clock.
10
//
11
//      Note that the AXI spec requires that there be no combinatorial
12
//      logic between input ports and output ports.  Hence all of the *valid
13
//      and *ready signals produced here are registered.  This forces us into
14
//      the buffered handshake strategy.
15
//
16
//      Some curious variable meanings below:
17
//
18
//      !axi_arvalid is synonymous with having a request, but stalling because
19
//              of a current request sitting in axi_rvalid with !axi_rready
20
//      !axi_awvalid is also synonymous with having an axi address being
21
//              received, but either the axi_bvalid && !axi_bready, or
22
//              no write data has been received
23
//      !axi_wvalid is similar to axi_awvalid.
24
//
25
// Creator:     Dan Gisselquist, Ph.D.
26
//              Gisselquist Technology, LLC
27
//
28
////////////////////////////////////////////////////////////////////////////////
29
//
30
// Copyright (C) 2018-2019, Gisselquist Technology, LLC
31
//
32
// This file is part of the pipelined Wishbone to AXI converter project, a
33
// project that contains multiple bus bridging designs and formal bus property
34
// sets.
35
//
36
// The bus bridge designs and property sets are free RTL designs: you can
37
// redistribute them and/or modify any of them under the terms of the GNU
38
// Lesser General Public License as published by the Free Software Foundation,
39
// either version 3 of the License, or (at your option) any later version.
40
//
41
// The bus bridge designs and property sets are distributed in the hope that
42
// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
43
// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
44
// GNU Lesser General Public License for more details.
45
//
46
// You should have received a copy of the GNU Lesser General Public License
47
// along with these designs.  (It's in the $(ROOT)/doc directory.  Run make
48
// with no target there if the PDF file isn't present.)  If not, see
49
// <http://www.gnu.org/licenses/> for a copy.
50
//
51
// License:     LGPL, v3, as defined and found on www.gnu.org,
52
//              http://www.gnu.org/licenses/lgpl.html
53
//
54
////////////////////////////////////////////////////////////////////////////////
55
//
56
//
57
`default_nettype none
58
 
59
`timescale 1 ns / 1 ps
60
 
61
module  demoaxi
62
        #(
63
                // Users to add parameters here
64
                parameter [0:0] OPT_READ_SIDEEFFECTS = 1,
65
                // User parameters ends
66
                // Do not modify the parameters beyond this line
67
                // Width of S_AXI data bus
68
                parameter integer C_S_AXI_DATA_WIDTH    = 32,
69
                // Width of S_AXI address bus
70
                parameter integer C_S_AXI_ADDR_WIDTH    = 8
71
        ) (
72
                // Users to add ports here
73
                // No user ports (yet) in this design
74
                // User ports ends
75
 
76
                // Do not modify the ports beyond this line
77
                // Global Clock Signal
78
                input wire  S_AXI_ACLK,
79
                // Global Reset Signal. This Signal is Active LOW
80
                input wire  S_AXI_ARESETN,
81
                // Write address (issued by master, acceped by Slave)
82
                input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
83
                // Write channel Protection type. This signal indicates the
84
                // privilege and security level of the transaction, and whether
85
                // the transaction is a data access or an instruction access.
86
                input wire [2 : 0] S_AXI_AWPROT,
87
                // Write address valid. This signal indicates that the master
88
                // signaling valid write address and control information.
89
                input wire  S_AXI_AWVALID,
90
                // Write address ready. This signal indicates that the slave
91
                // is ready to accept an address and associated control signals.
92
                output wire  S_AXI_AWREADY,
93
                // Write data (issued by master, acceped by Slave)
94
                input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
95
                // Write strobes. This signal indicates which byte lanes hold
96
                // valid data. There is one write strobe bit for each eight
97
                // bits of the write data bus.
98
                input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
99
                // Write valid. This signal indicates that valid write
100
                // data and strobes are available.
101
                input wire  S_AXI_WVALID,
102
                // Write ready. This signal indicates that the slave
103
                // can accept the write data.
104
                output wire  S_AXI_WREADY,
105
                // Write response. This signal indicates the status
106
                // of the write transaction.
107
                output wire [1 : 0] S_AXI_BRESP,
108
                // Write response valid. This signal indicates that the channel
109
                // is signaling a valid write response.
110
                output wire  S_AXI_BVALID,
111
                // Response ready. This signal indicates that the master
112
                // can accept a write response.
113
                input wire  S_AXI_BREADY,
114
                // Read address (issued by master, acceped by Slave)
115
                input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
116
                // Protection type. This signal indicates the privilege
117
                // and security level of the transaction, and whether the
118
                // transaction is a data access or an instruction access.
119
                input wire [2 : 0] S_AXI_ARPROT,
120
                // Read address valid. This signal indicates that the channel
121
                // is signaling valid read address and control information.
122
                input wire  S_AXI_ARVALID,
123
                // Read address ready. This signal indicates that the slave is
124
                // ready to accept an address and associated control signals.
125
                output wire  S_AXI_ARREADY,
126
                // Read data (issued by slave)
127
                output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
128
                // Read response. This signal indicates the status of the
129
                // read transfer.
130
                output wire [1 : 0] S_AXI_RRESP,
131
                // Read valid. This signal indicates that the channel is
132
                // signaling the required read data.
133
                output wire  S_AXI_RVALID,
134
                // Read ready. This signal indicates that the master can
135
                // accept the read data and response information.
136
                input wire  S_AXI_RREADY
137
        );
138
 
139
        // AXI4LITE signals
140
        reg             axi_awready;
141
        reg             axi_wready;
142
        reg [1 : 0]      axi_bresp;
143
        reg             axi_bvalid;
144
        reg             axi_arready;
145
        reg [C_S_AXI_DATA_WIDTH-1 : 0]   axi_rdata;
146
        reg [1 : 0]      axi_rresp;
147
        reg             axi_rvalid;
148
 
149
        // Example-specific design signals
150
        // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
151
        // ADDR_LSB is used for addressing 32/64 bit registers/memories
152
        // ADDR_LSB = 2 for 32 bits (n downto 2)
153
        // ADDR_LSB = 3 for 64 bits (n downto 3)
154
        localparam integer ADDR_LSB = 2;
155
        localparam integer AW = C_S_AXI_ADDR_WIDTH-2;
156
        localparam integer DW = C_S_AXI_DATA_WIDTH;
157
        //----------------------------------------------
158
        //-- Signals for user logic register space example
159
        //------------------------------------------------
160
        reg [DW-1:0]     slv_mem [0:63];
161
 
162
        // I/O Connections assignments
163
 
164
        assign S_AXI_AWREADY    = axi_awready;
165
        assign S_AXI_WREADY     = axi_wready;
166
        assign S_AXI_BRESP      = axi_bresp;
167
        assign S_AXI_BVALID     = axi_bvalid;
168
        assign S_AXI_ARREADY    = axi_arready;
169
        assign S_AXI_RDATA      = axi_rdata;
170
        assign S_AXI_RRESP      = axi_rresp;
171
        assign S_AXI_RVALID     = axi_rvalid;
172
        // Implement axi_*wready generation
173
 
174
        //////////////////////////////////////
175
        //
176
        // Read processing
177
        //
178
        //
179
        initial axi_rvalid = 1'b0;
180
        always @( posedge S_AXI_ACLK )
181
        if (!S_AXI_ARESETN)
182
                axi_rvalid <= 0;
183
        else if (S_AXI_ARVALID)
184
                axi_rvalid <= 1'b1;
185
        else if ((S_AXI_RVALID)&&(!S_AXI_RREADY))
186
                axi_rvalid <= 1'b1;
187
        else if (!axi_arready)
188
                axi_rvalid <= 1'b1;
189
        else
190
                axi_rvalid <= 1'b0;
191
 
192
        always @(*)
193
                axi_rresp  = 0;  // "OKAY" response
194
 
195
        reg [C_S_AXI_ADDR_WIDTH-1 : 0]   dly_addr, rd_addr;
196
 
197
        always @(posedge S_AXI_ACLK)
198
        if (S_AXI_ARREADY)
199
                dly_addr <= S_AXI_ARADDR;
200
 
201
        always @(*)
202
        if (!axi_arready)
203
                rd_addr = dly_addr;
204
        else
205
                rd_addr = S_AXI_ARADDR;
206
 
207
        always @(posedge S_AXI_ACLK)
208
        if (((!S_AXI_RVALID)||(S_AXI_RREADY))
209
                &&(!OPT_READ_SIDEEFFECTS
210
                        ||(!S_AXI_ARREADY || S_AXI_ARVALID)))
211
                // If the outgoing channel is not stalled (above)
212
                // then read
213
                axi_rdata <= slv_mem[rd_addr[AW+ADDR_LSB-1:ADDR_LSB]];
214
 
215
        initial axi_arready = 1'b0;
216
        always @(posedge S_AXI_ACLK)
217
        if (!S_AXI_ARESETN)
218
                axi_arready <= 1'b1;
219
        else if ((S_AXI_RVALID)&&(!S_AXI_RREADY))
220
        begin
221
                // Outgoing channel is stalled
222
                if (!axi_arready)
223
                        // If something is already in the buffer,
224
                        // axi_arready needs to stay low
225
                        axi_arready <= 1'b0;
226
                else
227
                        axi_arready <= (!S_AXI_ARVALID);
228
        end else
229
                axi_arready <= 1'b1;
230
 
231
        //////////////////////////////////////
232
        //
233
        // Write processing
234
        //
235
        //
236
        reg [C_S_AXI_ADDR_WIDTH-1 : 0]           pre_waddr, waddr;
237
        reg [C_S_AXI_DATA_WIDTH-1 : 0]           pre_wdata, wdata;
238
        reg [(C_S_AXI_DATA_WIDTH/8)-1 : 0]       pre_wstrb, wstrb;
239
 
240
        //
241
        // The write address channel ready signal
242
        //
243
        initial axi_awready = 1'b1;
244
        always @(posedge S_AXI_ACLK)
245
        if (!S_AXI_ARESETN)
246
                axi_awready <= 1'b1;
247
        else if ((S_AXI_BVALID)&&(!S_AXI_BREADY))
248
        begin
249
                // The output channel is stalled
250
                if (!axi_awready)
251
                        // If our buffer is full, remain stalled
252
                        axi_awready <= 1'b0;
253
                else
254
                        // If the buffer is empty, accept one transaction
255
                        // to fill it and then stall
256
                        axi_awready <= (!S_AXI_AWVALID);
257
        end else if ((!axi_wready)||((S_AXI_WVALID)&&(S_AXI_WREADY)))
258
                // The output channel is clear, and write data
259
                // are available
260
                axi_awready <= 1'b1;
261
        else
262
                // If we were ready before, then remain ready unless an
263
                // address unaccompanied by data shows up
264
                axi_awready <= ((axi_awready)&&(!S_AXI_AWVALID));
265
 
266
        //
267
        // The write data channel ready signal
268
        //
269
        initial axi_wready = 1'b1;
270
        always @(posedge S_AXI_ACLK)
271
        if (!S_AXI_ARESETN)
272
                axi_wready <= 1'b1;
273
        else if ((S_AXI_BVALID)&&(!S_AXI_BREADY))
274
        begin
275
                // The output channel is stalled
276
                if (!axi_wready)
277
                        axi_wready <= 1'b0;
278
                else
279
                        axi_wready <= (!S_AXI_WVALID);
280
        end else if ((!axi_awready)||((S_AXI_AWVALID)&&(S_AXI_AWREADY)))
281
                // The output channel is clear, and a write address
282
                // is available
283
                axi_wready <= 1'b1;
284
        else
285
                // if we were ready before, and there's no new data avaialble
286
                // to cause us to stall, remain ready
287
                axi_wready <= (axi_wready)&&(!S_AXI_WVALID);
288
 
289
 
290
        // Buffer the address
291
        always @(posedge S_AXI_ACLK)
292
        if ((S_AXI_AWREADY)&&(S_AXI_AWVALID))
293
                pre_waddr <= S_AXI_AWADDR;
294
 
295
        // Buffer the data
296
        always @(posedge S_AXI_ACLK)
297
        if ((S_AXI_WREADY)&&(S_AXI_WVALID))
298
        begin
299
                pre_wdata <= S_AXI_WDATA;
300
                pre_wstrb <= S_AXI_WSTRB;
301
        end
302
 
303
        always @(*)
304
        if (!axi_awready)
305
                // Read the write address from our "buffer"
306
                waddr = pre_waddr;
307
        else
308
                waddr = S_AXI_AWADDR;
309
 
310
        always @(*)
311
        if (!axi_wready)
312
        begin
313
                // Read the write data from our "buffer"
314
                wstrb = pre_wstrb;
315
                wdata = pre_wdata;
316
        end else begin
317
                wstrb = S_AXI_WSTRB;
318
                wdata = S_AXI_WDATA;
319
        end
320
 
321
 
322
        always @( posedge S_AXI_ACLK )
323
        // If the output channel isn't stalled, and
324
        if (((!S_AXI_BVALID)||(S_AXI_BREADY))
325
                // If we have a valid address, and
326
                &&((!axi_awready)||(S_AXI_AWVALID))
327
                // If we have valid data
328
                &&((!axi_wready)||((S_AXI_WVALID))))
329
        begin
330
                if (wstrb[0])
331
                        slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][7:0]
332
                                <= wdata[7:0];
333
                if (wstrb[1])
334
                        slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][15:8]
335
                                <= wdata[15:8];
336
                if (wstrb[2])
337
                        slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][23:16]
338
                                <= wdata[23:16];
339
                if (wstrb[3])
340
                        slv_mem[waddr[AW+ADDR_LSB-1:ADDR_LSB]][31:24]
341
                                <= wdata[31:24];
342
        end
343
 
344
        initial axi_bvalid = 1'b0;
345
        always @( posedge S_AXI_ACLK )
346
        if (!S_AXI_ARESETN)
347
                axi_bvalid <= 1'b0;
348
        //
349
        // The outgoing response channel should indicate a valid write if ...
350
                // 1. We have a valid address, and
351
        else if (((!axi_awready)||(S_AXI_AWVALID))
352
                        // 2. We had valid data
353
                        &&((!axi_wready)||((S_AXI_WVALID))))
354
                // It doesn't matter here if we are stalled or not
355
                // We can keep setting ready as often as we want
356
                axi_bvalid <= 1'b1;
357
        else if (S_AXI_BREADY)
358
                axi_bvalid <= 1'b0;
359
 
360
        always @(*)
361
                axi_bresp = 2'b0;       // "OKAY" response
362
 
363
        // Make Verilator happy
364
        // Verilator lint_off UNUSED
365
        wire    [5*ADDR_LSB+5:0] unused;
366
        assign  unused = { S_AXI_AWPROT, S_AXI_ARPROT,
367
                                S_AXI_AWADDR[ADDR_LSB-1:0],
368
                                dly_addr[ADDR_LSB-1:0],
369
                                rd_addr[ADDR_LSB-1:0],
370
                                waddr[ADDR_LSB-1:0],
371
                                S_AXI_ARADDR[ADDR_LSB-1:0] };
372
        // Verilator lint_on UNUSED
373
 
374
////////////////////////////////////////////////////////////////////////////////
375
////////////////////////////////////////////////////////////////////////////////
376
////////////////////////////////////////////////////////////////////////////////
377
////////////////////////////////////////////////////////////////////////////////
378
////////////////////////////////////////////////////////////////////////////////
379
////////////////////////////////////////////////////////////////////////////////
380
////////////////////////////////////////////////////////////////////////////////
381
`ifdef  FORMAL
382
        localparam      F_LGDEPTH = 4;
383
 
384
        wire    [(F_LGDEPTH-1):0]        f_axi_awr_outstanding,
385
                                        f_axi_wr_outstanding,
386
                                        f_axi_rd_outstanding;
387
 
388
        faxil_slave #(// .C_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
389
                        .C_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
390
                        // .F_OPT_NO_READS(1'b0),
391
                        // .F_OPT_NO_WRITES(1'b0),
392
                        .F_LGDEPTH(F_LGDEPTH))
393
                properties (
394
                .i_clk(S_AXI_ACLK),
395
                .i_axi_reset_n(S_AXI_ARESETN),
396
                //
397
                .i_axi_awaddr(S_AXI_AWADDR),
398
                .i_axi_awcache(4'h0),
399
                .i_axi_awprot(S_AXI_AWPROT),
400
                .i_axi_awvalid(S_AXI_AWVALID),
401
                .i_axi_awready(S_AXI_AWREADY),
402
                //
403
                .i_axi_wdata(S_AXI_WDATA),
404
                .i_axi_wstrb(S_AXI_WSTRB),
405
                .i_axi_wvalid(S_AXI_WVALID),
406
                .i_axi_wready(S_AXI_WREADY),
407
                //
408
                .i_axi_bresp(S_AXI_BRESP),
409
                .i_axi_bvalid(S_AXI_BVALID),
410
                .i_axi_bready(S_AXI_BREADY),
411
                //
412
                .i_axi_araddr(S_AXI_ARADDR),
413
                .i_axi_arprot(S_AXI_ARPROT),
414
                .i_axi_arcache(4'h0),
415
                .i_axi_arvalid(S_AXI_ARVALID),
416
                .i_axi_arready(S_AXI_ARREADY),
417
                //
418
                .i_axi_rdata(S_AXI_RDATA),
419
                .i_axi_rresp(S_AXI_RRESP),
420
                .i_axi_rvalid(S_AXI_RVALID),
421
                .i_axi_rready(S_AXI_RREADY),
422
                //
423
                .f_axi_rd_outstanding(f_axi_rd_outstanding),
424
                .f_axi_wr_outstanding(f_axi_wr_outstanding),
425
                .f_axi_awr_outstanding(f_axi_awr_outstanding));
426
 
427
        reg     f_past_valid;
428
        initial f_past_valid = 1'b0;
429
        always @(posedge S_AXI_ACLK)
430
                f_past_valid <= 1'b1;
431
 
432
        ///////
433
        //
434
        // Properties necessary to pass induction
435
        always @(*)
436
        if (S_AXI_ARESETN)
437
        begin
438
                if (!S_AXI_RVALID)
439
                        assert(f_axi_rd_outstanding == 0);
440
                else if (!S_AXI_ARREADY)
441
                        assert((f_axi_rd_outstanding == 2)||(f_axi_rd_outstanding == 1));
442
                else
443
                        assert(f_axi_rd_outstanding == 1);
444
        end
445
 
446
        always @(*)
447
        if (S_AXI_ARESETN)
448
        begin
449
                if (axi_bvalid)
450
                begin
451
                        assert(f_axi_awr_outstanding == 1+(axi_awready ? 0:1));
452
                        assert(f_axi_wr_outstanding  == 1+(axi_wready  ? 0:1));
453
                end else begin
454
                        assert(f_axi_awr_outstanding == (axi_awready ? 0:1));
455
                        assert(f_axi_wr_outstanding  == (axi_wready  ? 0:1));
456
                end
457
        end
458
 
459
 
460
        ////////////////////////////////////////////////////////////////////////
461
        //
462
        // Cover properties
463
        //
464
        // In addition to making sure the design returns a value, any value,
465
        // let's cover returning three values on adjacent clocks--just to prove
466
        // we can.
467
        //
468
        ////////////////////////////////////////////////////////////////////////
469
        //
470
        //
471
        always @( posedge S_AXI_ACLK )
472
        if ((f_past_valid)&&(S_AXI_ARESETN))
473
                cover(($past((S_AXI_BVALID && S_AXI_BREADY)))
474
                        &&($past((S_AXI_BVALID && S_AXI_BREADY),2))
475
                        &&(S_AXI_BVALID && S_AXI_BREADY));
476
 
477
        always @( posedge S_AXI_ACLK )
478
        if ((f_past_valid)&&(S_AXI_ARESETN))
479
                cover(($past((S_AXI_RVALID && S_AXI_RREADY)))
480
                        &&($past((S_AXI_RVALID && S_AXI_RREADY),2))
481
                        &&(S_AXI_RVALID && S_AXI_RREADY));
482
 
483
        // Let's go just one further, and verify we can do three returns in a
484
        // row.  Why?  It might just be possible that one value was waiting
485
        // already, and so we haven't yet tested that two requests could be
486
        // made in a row.
487
        always @( posedge S_AXI_ACLK )
488
        if ((f_past_valid)&&(S_AXI_ARESETN))
489
                cover(($past((S_AXI_BVALID && S_AXI_BREADY)))
490
                        &&($past((S_AXI_BVALID && S_AXI_BREADY),2))
491
                        &&($past((S_AXI_BVALID && S_AXI_BREADY),3))
492
                        &&(S_AXI_BVALID && S_AXI_BREADY));
493
 
494
        always @( posedge S_AXI_ACLK )
495
        if ((f_past_valid)&&(S_AXI_ARESETN))
496
                cover(($past((S_AXI_RVALID && S_AXI_RREADY)))
497
                        &&($past((S_AXI_RVALID && S_AXI_RREADY),2))
498
                        &&($past((S_AXI_RVALID && S_AXI_RREADY),3))
499
                        &&(S_AXI_RVALID && S_AXI_RREADY));
500
 
501
        //
502
        // Let's create a sophisticated cover statement designed to show off
503
        // how our core can handle stalls and non-valids, synchronizing
504
        // across multiple scenarios
505
        reg     [22:0]   fw_wrdemo_pipe, fr_wrdemo_pipe;
506
        always @(*)
507
        if (!S_AXI_ARESETN)
508
                fw_wrdemo_pipe = 0;
509
        else begin
510
                fw_wrdemo_pipe[0] = (S_AXI_AWVALID)
511
                                &&(S_AXI_WVALID)
512
                                &&(S_AXI_BREADY);
513
                fw_wrdemo_pipe[1] = fr_wrdemo_pipe[0]
514
                                &&(!S_AXI_AWVALID)
515
                                &&(!S_AXI_WVALID)
516
                                &&(S_AXI_BREADY);
517
                fw_wrdemo_pipe[2] = fr_wrdemo_pipe[1]
518
                                &&(!S_AXI_AWVALID)
519
                                &&(!S_AXI_WVALID)
520
                                &&(S_AXI_BREADY);
521
                //
522
                //
523
                fw_wrdemo_pipe[3] = fr_wrdemo_pipe[2]
524
                                &&(S_AXI_AWVALID)
525
                                &&(S_AXI_WVALID)
526
                                &&(S_AXI_BREADY);
527
                fw_wrdemo_pipe[4] = fr_wrdemo_pipe[3]
528
                                &&(S_AXI_AWVALID)
529
                                &&(S_AXI_WVALID)
530
                                &&(S_AXI_BREADY);
531
                fw_wrdemo_pipe[5] = fr_wrdemo_pipe[4]
532
                                &&(!S_AXI_AWVALID)
533
                                &&(S_AXI_WVALID)
534
                                &&(S_AXI_BREADY);
535
                fw_wrdemo_pipe[6] = fr_wrdemo_pipe[5]
536
                                &&(S_AXI_AWVALID)
537
                                &&( S_AXI_WVALID)
538
                                &&( S_AXI_BREADY);
539
                fw_wrdemo_pipe[7] = fr_wrdemo_pipe[6]
540
                                &&(!S_AXI_AWVALID)
541
                                &&(S_AXI_WVALID)
542
                                &&( S_AXI_BREADY);
543
                fw_wrdemo_pipe[8] = fr_wrdemo_pipe[7]
544
                                &&(S_AXI_AWVALID)
545
                                &&(S_AXI_WVALID)
546
                                &&(S_AXI_BREADY);
547
                fw_wrdemo_pipe[9] = fr_wrdemo_pipe[8]
548
//                              &&(S_AXI_AWVALID)
549
//                              &&(!S_AXI_WVALID)
550
                                &&(S_AXI_BREADY);
551
                fw_wrdemo_pipe[10] = fr_wrdemo_pipe[9]
552
//                              &&(S_AXI_AWVALID)
553
//                              &&(S_AXI_WVALID)
554
                                // &&(S_AXI_BREADY);
555
                                &&(S_AXI_BREADY);
556
                fw_wrdemo_pipe[11] = fr_wrdemo_pipe[10]
557
                                &&(S_AXI_AWVALID)
558
                                &&(S_AXI_WVALID)
559
                                &&(!S_AXI_BREADY);
560
                fw_wrdemo_pipe[12] = fr_wrdemo_pipe[11]
561
                                &&(!S_AXI_AWVALID)
562
                                &&(!S_AXI_WVALID)
563
                                &&(S_AXI_BREADY);
564
                fw_wrdemo_pipe[13] = fr_wrdemo_pipe[12]
565
                                &&(!S_AXI_AWVALID)
566
                                &&(!S_AXI_WVALID)
567
                                &&(S_AXI_BREADY);
568
                fw_wrdemo_pipe[14] = fr_wrdemo_pipe[13]
569
                                &&(!S_AXI_AWVALID)
570
                                &&(!S_AXI_WVALID)
571
                                &&(f_axi_awr_outstanding == 0)
572
                                &&(f_axi_wr_outstanding == 0)
573
                                &&(S_AXI_BREADY);
574
                //
575
                //
576
                //
577
                fw_wrdemo_pipe[15] = fr_wrdemo_pipe[14]
578
                                &&(S_AXI_AWVALID)
579
                                &&(S_AXI_WVALID)
580
                                &&(S_AXI_BREADY);
581
                fw_wrdemo_pipe[16] = fr_wrdemo_pipe[15]
582
                                &&(S_AXI_AWVALID)
583
                                &&(S_AXI_WVALID)
584
                                &&(S_AXI_BREADY);
585
                fw_wrdemo_pipe[17] = fr_wrdemo_pipe[16]
586
                                &&(S_AXI_AWVALID)
587
                                &&(S_AXI_WVALID)
588
                                &&(S_AXI_BREADY);
589
                fw_wrdemo_pipe[18] = fr_wrdemo_pipe[17]
590
                                &&(S_AXI_AWVALID)
591
                                &&(S_AXI_WVALID)
592
                                &&(!S_AXI_BREADY);
593
                fw_wrdemo_pipe[19] = fr_wrdemo_pipe[18]
594
                                &&(S_AXI_AWVALID)
595
                                &&(S_AXI_WVALID)
596
                                &&(S_AXI_BREADY);
597
                fw_wrdemo_pipe[20] = fr_wrdemo_pipe[19]
598
                                &&(S_AXI_AWVALID)
599
                                &&(S_AXI_WVALID)
600
                                &&(S_AXI_BREADY);
601
                fw_wrdemo_pipe[21] = fr_wrdemo_pipe[20]
602
                                &&(!S_AXI_AWVALID)
603
                                &&(!S_AXI_WVALID)
604
                                &&(S_AXI_BREADY);
605
                fw_wrdemo_pipe[22] = fr_wrdemo_pipe[21]
606
                                &&(!S_AXI_AWVALID)
607
                                &&(!S_AXI_WVALID)
608
                                &&(S_AXI_BREADY);
609
        end
610
 
611
        always @(posedge S_AXI_ACLK)
612
                fr_wrdemo_pipe <= fw_wrdemo_pipe;
613
 
614
        always @(*)
615
        if (S_AXI_ARESETN)
616
        begin
617
                cover(fw_wrdemo_pipe[0]);
618
                cover(fw_wrdemo_pipe[1]);
619
                cover(fw_wrdemo_pipe[2]);
620
                cover(fw_wrdemo_pipe[3]);
621
                cover(fw_wrdemo_pipe[4]);
622
                cover(fw_wrdemo_pipe[5]);
623
                cover(fw_wrdemo_pipe[6]);
624
                cover(fw_wrdemo_pipe[7]); //
625
                cover(fw_wrdemo_pipe[8]);
626
                cover(fw_wrdemo_pipe[9]);
627
                cover(fw_wrdemo_pipe[10]);
628
                cover(fw_wrdemo_pipe[11]);
629
                cover(fw_wrdemo_pipe[12]);
630
                cover(fw_wrdemo_pipe[13]);
631
                cover(fw_wrdemo_pipe[14]);
632
                cover(fw_wrdemo_pipe[15]);
633
                cover(fw_wrdemo_pipe[16]);
634
                cover(fw_wrdemo_pipe[17]);
635
                cover(fw_wrdemo_pipe[18]);
636
                cover(fw_wrdemo_pipe[19]);
637
                cover(fw_wrdemo_pipe[20]);
638
                cover(fw_wrdemo_pipe[21]);
639
                cover(fw_wrdemo_pipe[22]);
640
        end
641
 
642
        //
643
        // Now let's repeat, but for a read demo
644
        reg     [10:0]   fw_rddemo_pipe, fr_rddemo_pipe;
645
        always @(*)
646
        if (!S_AXI_ARESETN)
647
                fw_rddemo_pipe = 0;
648
        else begin
649
                fw_rddemo_pipe[0] = (S_AXI_ARVALID)
650
                                &&(S_AXI_RREADY);
651
                fw_rddemo_pipe[1] = fr_rddemo_pipe[0]
652
                                &&(!S_AXI_ARVALID)
653
                                &&(S_AXI_RREADY);
654
                fw_rddemo_pipe[2] = fr_rddemo_pipe[1]
655
                                &&(!S_AXI_ARVALID)
656
                                &&(S_AXI_RREADY);
657
                //
658
                //
659
                fw_rddemo_pipe[3] = fr_rddemo_pipe[2]
660
                                &&(S_AXI_ARVALID)
661
                                &&(S_AXI_RREADY);
662
                fw_rddemo_pipe[4] = fr_rddemo_pipe[3]
663
                                &&(S_AXI_ARVALID)
664
                                &&(S_AXI_RREADY);
665
                fw_rddemo_pipe[5] = fr_rddemo_pipe[4]
666
                                &&(S_AXI_ARVALID)
667
                                &&(S_AXI_RREADY);
668
                fw_rddemo_pipe[6] = fr_rddemo_pipe[5]
669
                                &&(S_AXI_ARVALID)
670
                                &&(!S_AXI_RREADY);
671
                fw_rddemo_pipe[7] = fr_rddemo_pipe[6]
672
                                &&(S_AXI_ARVALID)
673
                                &&(S_AXI_RREADY);
674
                fw_rddemo_pipe[8] = fr_rddemo_pipe[7]
675
                                &&(S_AXI_ARVALID)
676
                                &&(S_AXI_RREADY);
677
                fw_rddemo_pipe[9] = fr_rddemo_pipe[8]
678
                                &&(!S_AXI_ARVALID)
679
                                &&(S_AXI_RREADY);
680
                fw_rddemo_pipe[10] = fr_rddemo_pipe[9]
681
                                &&(f_axi_rd_outstanding == 0);
682
        end
683
 
684
        initial fr_rddemo_pipe = 0;
685
        always @(posedge S_AXI_ACLK)
686
                fr_rddemo_pipe <= fw_rddemo_pipe;
687
 
688
        always @(*)
689
        begin
690
                cover(fw_rddemo_pipe[0]);
691
                cover(fw_rddemo_pipe[1]);
692
                cover(fw_rddemo_pipe[2]);
693
                cover(fw_rddemo_pipe[3]);
694
                cover(fw_rddemo_pipe[4]);
695
                cover(fw_rddemo_pipe[5]);
696
                cover(fw_rddemo_pipe[6]);
697
                cover(fw_rddemo_pipe[7]);
698
                cover(fw_rddemo_pipe[8]);
699
                cover(fw_rddemo_pipe[9]);
700
                cover(fw_rddemo_pipe[10]);
701
        end
702
`endif
703
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.