| 1 |
2 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//
|
| 3 |
|
|
// Filename: wbm2axisp.v
|
| 4 |
|
|
//
|
| 5 |
|
|
// Project: Pipelined Wishbone to AXI converter
|
| 6 |
|
|
//
|
| 7 |
|
|
// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as
|
| 8 |
|
|
// one per clock. The AXI bus allows transactions at a speed of
|
| 9 |
|
|
// one read and one write transaction per clock. These capabilities work
|
| 10 |
|
|
// by allowing requests to take place prior to responses, such that the
|
| 11 |
|
|
// requests might go out at once per clock and take several clocks, and
|
| 12 |
|
|
// the responses may start coming back several clocks later. In other
|
| 13 |
|
|
// words, both protocols allow multiple transactions to be "in flight" at
|
| 14 |
|
|
// the same time. Current wishbone to AXI converters, however, handle only
|
| 15 |
|
|
// one transaction at a time: initiating the transaction, and then waiting
|
| 16 |
|
|
// for the transaction to complete before initiating the next.
|
| 17 |
|
|
//
|
| 18 |
|
|
// The purpose of this core is to maintain the speed of both busses, while
|
| 19 |
|
|
// transiting from the Wishbone (as master) to the AXI bus (as slave) and
|
| 20 |
|
|
// back again.
|
| 21 |
|
|
//
|
| 22 |
|
|
// Since the AXI bus allows transactions to be reordered, whereas the
|
| 23 |
|
|
// wishbone does not, this core can be configured to reorder return
|
| 24 |
|
|
// transactions as well.
|
| 25 |
|
|
//
|
| 26 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 27 |
|
|
// Gisselquist Technology, LLC
|
| 28 |
|
|
//
|
| 29 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 30 |
|
|
//
|
| 31 |
|
|
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
| 32 |
|
|
//
|
| 33 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
| 34 |
|
|
// modify it under the terms of the GNU General Public License as published
|
| 35 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
| 36 |
|
|
// your option) any later version.
|
| 37 |
|
|
//
|
| 38 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
| 39 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
| 40 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 41 |
|
|
// for more details.
|
| 42 |
|
|
//
|
| 43 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 44 |
|
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
| 45 |
|
|
// target there if the PDF file isn't present.) If not, see
|
| 46 |
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
| 47 |
|
|
//
|
| 48 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
| 49 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
| 50 |
|
|
//
|
| 51 |
|
|
//
|
| 52 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 53 |
|
|
//
|
| 54 |
|
|
//
|
| 55 |
|
|
module wbm2axisp #(
|
| 56 |
|
|
parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
|
| 57 |
|
|
// This is an int between 1-16
|
| 58 |
|
|
parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
|
| 59 |
|
|
parameter AW = 28, // Wishbone address width
|
| 60 |
|
|
parameter DW = 128 // Wishbone data width
|
| 61 |
|
|
) (
|
| 62 |
|
|
input i_clk, // System clock
|
| 63 |
|
|
input i_reset,// Wishbone reset signal
|
| 64 |
|
|
|
| 65 |
|
|
// AXI write address channel signals
|
| 66 |
|
|
input i_axi_wready, // Slave is ready to accept
|
| 67 |
|
|
output wire [C_AXI_ID_WIDTH-1:0] o_axi_wid, // Write ID
|
| 68 |
|
|
output reg [AW-1:0] o_axi_waddr, // Write address
|
| 69 |
|
|
output wire [7:0] o_axi_wlen, // Write Burst Length
|
| 70 |
|
|
output wire [2:0] o_axi_wsize, // Write Burst size
|
| 71 |
|
|
output wire [1:0] o_axi_wburst, // Write Burst type
|
| 72 |
|
|
output wire [1:0] o_axi_wlock, // Write lock type
|
| 73 |
|
|
output wire [3:0] o_axi_wcache, // Write Cache type
|
| 74 |
|
|
output wire [2:0] o_axi_wprot, // Write Protection type
|
| 75 |
|
|
output reg o_axi_wvalid, // Write address valid
|
| 76 |
|
|
|
| 77 |
|
|
// AXI write data channel signals
|
| 78 |
|
|
input i_axi_wd_wready, // Write data ready
|
| 79 |
|
|
output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag
|
| 80 |
|
|
output reg [DW-1:0] o_axi_wd_data, // Write data
|
| 81 |
|
|
output reg [DW/8-1:0] o_axi_wd_strb, // Write strobes
|
| 82 |
|
|
output wire o_axi_wd_last, // Last write transaction
|
| 83 |
|
|
output reg o_axi_wd_valid, // Write valid
|
| 84 |
|
|
|
| 85 |
|
|
// AXI write response channel signals
|
| 86 |
|
|
input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID
|
| 87 |
|
|
input [1:0] i_axi_wd_bresp, // Write response
|
| 88 |
|
|
input i_axi_wd_bvalid, // Write reponse valid
|
| 89 |
|
|
output wire o_axi_wd_bready, // Response ready
|
| 90 |
|
|
|
| 91 |
|
|
// AXI read address channel signals
|
| 92 |
|
|
input i_axi_rready, // Read address ready
|
| 93 |
|
|
output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid, // Read ID
|
| 94 |
|
|
output wire [AW-1:0] o_axi_raddr, // Read address
|
| 95 |
|
|
output wire [7:0] o_axi_rlen, // Read Burst Length
|
| 96 |
|
|
output wire [2:0] o_axi_rsize, // Read Burst size
|
| 97 |
|
|
output wire [1:0] o_axi_rburst, // Read Burst type
|
| 98 |
|
|
output wire [1:0] o_axi_rlock, // Read lock type
|
| 99 |
|
|
output wire [3:0] o_axi_rcache, // Read Cache type
|
| 100 |
|
|
output wire [2:0] o_axi_rprot, // Read Protection type
|
| 101 |
|
|
output reg o_axi_rvalid, // Read address valid
|
| 102 |
|
|
|
| 103 |
|
|
// AXI read data channel signals
|
| 104 |
|
|
input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID
|
| 105 |
|
|
input [1:0] i_axi_rd_rresp, // Read response
|
| 106 |
|
|
input i_axi_rd_rvalid, // Read reponse valid
|
| 107 |
|
|
input [DW-1:0] i_axi_rd_data, // Read data
|
| 108 |
|
|
input i_axi_rd_last, // Read last
|
| 109 |
|
|
output wire o_axi_rd_rready, // Read Response ready
|
| 110 |
|
|
|
| 111 |
|
|
// We'll share the clock and the reset
|
| 112 |
|
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
| 113 |
|
|
input [AW-1:0] i_wb_addr;
|
| 114 |
|
|
input [DW-1:0] i_wb_data;
|
| 115 |
|
|
output reg o_wb_ack;
|
| 116 |
|
|
output wire o_wb_stall;
|
| 117 |
|
|
output reg [DW-1:0] o_wb_data;
|
| 118 |
|
|
output reg o_wb_err;
|
| 119 |
|
|
);
|
| 120 |
|
|
|
| 121 |
|
|
//*****************************************************************************
|
| 122 |
|
|
// Parameter declarations
|
| 123 |
|
|
//*****************************************************************************
|
| 124 |
|
|
|
| 125 |
|
|
localparam CTL_SIG_WIDTH = 3; // Control signal width
|
| 126 |
|
|
localparam RD_STS_WIDTH = 16; // Read status signal width
|
| 127 |
|
|
localparam WR_STS_WIDTH = 16; // Write status signal width
|
| 128 |
|
|
|
| 129 |
|
|
//*****************************************************************************
|
| 130 |
|
|
// Internal register and wire declarations
|
| 131 |
|
|
//*****************************************************************************
|
| 132 |
|
|
|
| 133 |
|
|
wire cmd_en;
|
| 134 |
|
|
wire [2:0] cmd;
|
| 135 |
|
|
wire [7:0] blen;
|
| 136 |
|
|
wire [31:0] addr;
|
| 137 |
|
|
wire [CTL_SIG_WIDTH-1:0] ctl;
|
| 138 |
|
|
wire cmd_ack;
|
| 139 |
|
|
|
| 140 |
|
|
// User interface write ports
|
| 141 |
|
|
wire wrdata_vld;
|
| 142 |
|
|
wire [C_AXI_DATA_WIDTH-1:0] wrdata;
|
| 143 |
|
|
wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
|
| 144 |
|
|
wire wrdata_cmptd;
|
| 145 |
|
|
wire wrdata_rdy;
|
| 146 |
|
|
wire wrdata_sts_vld;
|
| 147 |
|
|
wire [WR_STS_WIDTH-1:0] wrdata_sts;
|
| 148 |
|
|
|
| 149 |
|
|
// User interface read ports
|
| 150 |
|
|
wire rddata_rdy;
|
| 151 |
|
|
wire rddata_vld;
|
| 152 |
|
|
wire [C_AXI_DATA_WIDTH-1:0] rddata;
|
| 153 |
|
|
wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
|
| 154 |
|
|
wire rddata_cmptd;
|
| 155 |
|
|
wire [RD_STS_WIDTH-1:0] rddata_sts;
|
| 156 |
|
|
reg cmptd_one_wr;
|
| 157 |
|
|
reg cmptd_one_rd;
|
| 158 |
|
|
|
| 159 |
|
|
|
| 160 |
|
|
// Things we're not changing ...
|
| 161 |
|
|
assign o_axi_wlen = 8'h0; // Burst length is one
|
| 162 |
|
|
assign o_axi_wsize = 3'b101; // maximum bytes per burst is 32
|
| 163 |
|
|
assign o_axi_wburst = 2'b01; // Incrementing address (ignored)
|
| 164 |
|
|
assign o_axi_rburst = 2'b01; // Incrementing address (ignored)
|
| 165 |
|
|
assign o_axi_wlock = 2'b00; // Normal signaling
|
| 166 |
|
|
assign o_axi_rlock = 2'b00; // Normal signaling
|
| 167 |
|
|
assign o_axi_wcache = 4'h2; // Normal: no cache, no buffer
|
| 168 |
|
|
assign o_axi_rcache = 4'h2; // Normal: no cache, no buffer
|
| 169 |
|
|
assign o_axi_wprot = 3'h010; // Unpriviledged, unsecure, data access
|
| 170 |
|
|
assign o_axi_rprot = 3'h010; // Unpriviledged, unsecure, data access
|
| 171 |
|
|
|
| 172 |
|
|
// Command logic
|
| 173 |
|
|
assign o_wb_stall = (i_wb_we)&&(~i_axi_wready)
|
| 174 |
|
|
||(~i_wb_we)&&(!i_axi_rready);
|
| 175 |
|
|
// Write address logic
|
| 176 |
|
|
|
| 177 |
|
|
always @(posedge i_clk)
|
| 178 |
|
|
o_axi_wvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
|
| 179 |
|
|
||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
|
| 180 |
|
|
always @(posedge i_clk)
|
| 181 |
|
|
if (!o_wb_stall)
|
| 182 |
|
|
o_axi_waddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
|
| 183 |
|
|
|
| 184 |
|
|
reg [5:0] transaction_id;
|
| 185 |
|
|
always @(posedge i_clk)
|
| 186 |
|
|
if (!i_wb_cyc)
|
| 187 |
|
|
transaction_id <= 6'h00;
|
| 188 |
|
|
else if ((i_wb_stb)&&(~o_wb_stall))
|
| 189 |
|
|
transaction_id <= transaction_id + 6'h01;
|
| 190 |
|
|
assign o_axi_wid = transaction_id;
|
| 191 |
|
|
|
| 192 |
|
|
// Read address logic
|
| 193 |
|
|
assign o_axi_rid = transaction_id;
|
| 194 |
|
|
assign o_axi_raddr = o_axi_waddr;
|
| 195 |
|
|
assign o_axi_rlen = o_axi_wlen;
|
| 196 |
|
|
assign o_axi_rsize = 3'b101; // maximum bytes per burst is 32
|
| 197 |
|
|
always @(posedge i_clk)
|
| 198 |
|
|
o_axi_rvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
|
| 199 |
|
|
||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);
|
| 200 |
|
|
|
| 201 |
|
|
|
| 202 |
|
|
// Write data logic
|
| 203 |
|
|
assign o_axi_wd_wid = transaction_id;
|
| 204 |
|
|
always @(posedge i_clk)
|
| 205 |
|
|
if (!o_wb_stall)
|
| 206 |
|
|
o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wbdata };
|
| 207 |
|
|
always @(posedge i_clk)
|
| 208 |
|
|
if (!o_wb_stall)
|
| 209 |
|
|
case(i_wb_addr[1:0])
|
| 210 |
|
|
2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
|
| 211 |
|
|
2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
|
| 212 |
|
|
2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
|
| 213 |
|
|
2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
|
| 214 |
|
|
endcase
|
| 215 |
|
|
assign o_axi_wd_last = 1'b1;
|
| 216 |
|
|
always @(posedge i_clk)
|
| 217 |
|
|
o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
|
| 218 |
|
|
||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);
|
| 219 |
|
|
|
| 220 |
|
|
// Read data channel / response logic
|
| 221 |
|
|
assign o_axi_rd_rready = 1'b1;
|
| 222 |
|
|
assign o_axi_wd_bready = 1'b1;
|
| 223 |
|
|
|
| 224 |
|
|
wire w_fifo_full;
|
| 225 |
|
|
generate
|
| 226 |
|
|
if (STRICT_ORDER == 0)
|
| 227 |
|
|
begin
|
| 228 |
|
|
// Reorder FIFO
|
| 229 |
|
|
//
|
| 230 |
|
|
localparam LGFIFOLN = C_AXI_ID_WIDTH;
|
| 231 |
|
|
localparam FIFOLN = (1<<LGFIFOLN);
|
| 232 |
|
|
// FIFO reorder buffer
|
| 233 |
|
|
reg [(DW-1):0] reorder_fifo_data [0:(FIFOLN-1)];
|
| 234 |
|
|
reg reorder_fifo_valid[0:(FIFOLN-1)];
|
| 235 |
|
|
reg reorder_fifo_err [0:(FIFOLN-1)];
|
| 236 |
|
|
assign fifo_head = transaction_id;
|
| 237 |
|
|
|
| 238 |
|
|
// Let's do some math to figure out where the FIFO head will
|
| 239 |
|
|
// point to next, but let's also insist that it be LGFIFOLN
|
| 240 |
|
|
// bits in size as well. This'll be part of the fifo_full
|
| 241 |
|
|
// calculation below.
|
| 242 |
|
|
wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
|
| 243 |
|
|
assign n_fifo_head = fifo_head+1'b1;
|
| 244 |
|
|
|
| 245 |
|
|
always @(posedge i_clk)
|
| 246 |
|
|
begin
|
| 247 |
|
|
if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
|
| 248 |
|
|
reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;
|
| 249 |
|
|
if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
|
| 250 |
|
|
begin
|
| 251 |
|
|
reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
|
| 252 |
|
|
reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_resp[1];
|
| 253 |
|
|
end
|
| 254 |
|
|
if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
|
| 255 |
|
|
begin
|
| 256 |
|
|
reorder_fifo_valid[i_axi_wd_bid] = 1'b1;
|
| 257 |
|
|
reorder_fifo_err[i_axi_wd_bid] = i_axi_wd_bresp[1];
|
| 258 |
|
|
end
|
| 259 |
|
|
|
| 260 |
|
|
o_wb_data <= reorder_fifo_data[fifo_tail];
|
| 261 |
|
|
if (reorder_fifo_valid[fifo_tail])
|
| 262 |
|
|
begin
|
| 263 |
|
|
o_wb_ack <= 1'b1;
|
| 264 |
|
|
o_wb_err <= reorder_fifo_err[fifo_tail];
|
| 265 |
|
|
fifo_tail <= fifo_tail + 6'h1;
|
| 266 |
|
|
reorder_fifo_valid[fifo_tail] <= 1'b0;
|
| 267 |
|
|
reorder_fifo_err[fifo_tail] <= 1'b0;
|
| 268 |
|
|
end else begin
|
| 269 |
|
|
o_wb_ack <= 1'b0;
|
| 270 |
|
|
o_wb_err <= 1'b0;
|
| 271 |
|
|
end
|
| 272 |
|
|
|
| 273 |
|
|
if (!i_wb_cyc)
|
| 274 |
|
|
begin
|
| 275 |
|
|
reorder_fifo_valid <= {(FIFOLN){1'b0}};
|
| 276 |
|
|
reorder_fifo_err <= {(FIFOLN){1'b0}};
|
| 277 |
|
|
fifo_tail <= 6'h0;
|
| 278 |
|
|
o_wb_err <= 1'b0;
|
| 279 |
|
|
o_wb_ack <= 1'b0;
|
| 280 |
|
|
end
|
| 281 |
|
|
end
|
| 282 |
|
|
|
| 283 |
|
|
always @(posedge i_clk)
|
| 284 |
|
|
begin
|
| 285 |
|
|
if (!i_wb_cyc)
|
| 286 |
|
|
r_fifo_full <= 1'b0;
|
| 287 |
|
|
else if ((i_wb_stb)&&(~o_wb_stall)
|
| 288 |
|
|
&&(reorder_fifo_valid[fifo_tail]))
|
| 289 |
|
|
r_fifo_full <= (fifo_tail==n_fifo_head);
|
| 290 |
|
|
else if ((i_wb_stb)&&(~o_wb_stall))
|
| 291 |
|
|
r_fifo_full <= (fifo_tail==nn_fifo_head);
|
| 292 |
|
|
else if (reorder_fifo_valid[fifo_tail])
|
| 293 |
|
|
r_fifo_full <= 1'b0;
|
| 294 |
|
|
else
|
| 295 |
|
|
r_fifo_full <= (fifo_tail==n_fifo_head);
|
| 296 |
|
|
end
|
| 297 |
|
|
assign w_fifo_full = r_fifo_full;
|
| 298 |
|
|
end else begin
|
| 299 |
|
|
w_fifo_full = 1'b0;
|
| 300 |
|
|
always @(posedge i_clk)
|
| 301 |
|
|
o_wb_data <= i_axi_rd_data;
|
| 302 |
|
|
always @(posedge i_clk)
|
| 303 |
|
|
o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
|
| 304 |
|
|
||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
|
| 305 |
|
|
always @(posedge i_clk)
|
| 306 |
|
|
o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
|
| 307 |
|
|
||((i_axi_rd_rvalid)&&(i_axi_rd_resp[1]))
|
| 308 |
|
|
||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
|
| 309 |
|
|
end
|
| 310 |
|
|
|
| 311 |
|
|
|
| 312 |
|
|
// Now, the difficult signal ... the stall signal
|
| 313 |
|
|
// Let's build for a single cycle input ... and only stall if something
|
| 314 |
|
|
// outgoing is valid and nothing is ready.
|
| 315 |
|
|
assign o_wb_stall = (i_wb_cyc)&&(
|
| 316 |
|
|
(w_fifo_full)
|
| 317 |
|
|
||((o_axi_wvalid)&&(!i_axi_wready))
|
| 318 |
|
|
||((o_axi_wd_valid)&&(!i_axi_wd_bready))
|
| 319 |
|
|
||((o_axi_rvalid)&&(!i_axi_rready)));
|
| 320 |
|
|
endmodule
|
