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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    wbm2axisp.v
//
// Project:     Pipelined Wishbone to AXI converter
//
// Purpose:     The B4 Wishbone SPEC allows transactions at a speed as fast as
//              one per clock.  The AXI bus allows transactions at a speed of
//      one read and one write transaction per clock.  These capabilities work
//      by allowing requests to take place prior to responses, such that the
//      requests might go out at once per clock and take several clocks, and
//      the responses may start coming back several clocks later.  In other
//      words, both protocols allow multiple transactions to be "in flight" at
//      the same time.  Current wishbone to AXI converters, however, handle only
//      one transaction at a time: initiating the transaction, and then waiting
//      for the transaction to complete before initiating the next.
//
//      The purpose of this core is to maintain the speed of both busses, while
//      transiting from the Wishbone (as master) to the AXI bus (as slave) and
//      back again.
//
//      Since the AXI bus allows transactions to be reordered, whereas the 
//      wishbone does not, this core can be configured to reorder return
//      transactions as well.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbm2axisp #(
        parameter C_AXI_ID_WIDTH        = 6, // The AXI id width used for R&W
                                             // This is an int between 1-16
        parameter C_AXI_DATA_WIDTH      = 128,// Width of the AXI R&W data
        parameter C_AXI_ADDR_WIDTH      = 28,   // AXI Address width
        parameter DW                    = 32,   // Wishbone data width
        parameter AW                    = 26,   // Wishbone address width
        parameter STRICT_ORDER          = 0      // Reorder, or not? 0 -> Reorder
        ) (
        input                           i_clk,  // System clock
        // input                        i_reset,// Wishbone reset signal--unused
 
// AXI write address channel signals
        input                           i_axi_awready, // Slave is ready to accept
        output  reg     [C_AXI_ID_WIDTH-1:0]     o_axi_awid,     // Write ID
        output  reg     [C_AXI_ADDR_WIDTH-1:0]   o_axi_awaddr,   // Write address
        output  wire    [7:0]            o_axi_awlen,    // Write Burst Length
        output  wire    [2:0]            o_axi_awsize,   // Write Burst size
        output  wire    [1:0]            o_axi_awburst,  // Write Burst type
        output  wire    [0:0]             o_axi_awlock,   // Write lock type
        output  wire    [3:0]            o_axi_awcache,  // Write Cache type
        output  wire    [2:0]            o_axi_awprot,   // Write Protection type
        output  wire    [3:0]            o_axi_awqos,    // Write Quality of Svc
        output  reg                     o_axi_awvalid,  // Write address valid
 
// AXI write data channel signals
        input                           i_axi_wready,  // Write data ready
        output  reg     [C_AXI_DATA_WIDTH-1:0]   o_axi_wdata,    // Write data
        output  reg     [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb,    // Write strobes
        output  wire                    o_axi_wlast,    // Last write transaction   
        output  reg                     o_axi_wvalid,   // Write valid
 
// AXI write response channel signals
        input   [C_AXI_ID_WIDTH-1:0]     i_axi_bid,      // Response ID
        input   [1:0]                    i_axi_bresp,    // Write response
        input                           i_axi_bvalid,  // Write reponse valid
        output  wire                    o_axi_bready,  // Response ready
 
// AXI read address channel signals
        input                           i_axi_arready,  // Read address ready
        output  wire    [C_AXI_ID_WIDTH-1:0]     o_axi_arid,     // Read ID
        output  wire    [C_AXI_ADDR_WIDTH-1:0]   o_axi_araddr,   // Read address
        output  wire    [7:0]            o_axi_arlen,    // Read Burst Length
        output  wire    [2:0]            o_axi_arsize,   // Read Burst size
        output  wire    [1:0]            o_axi_arburst,  // Read Burst type
        output  wire    [0:0]             o_axi_arlock,   // Read lock type
        output  wire    [3:0]            o_axi_arcache,  // Read Cache type
        output  wire    [2:0]            o_axi_arprot,   // Read Protection type
        output  wire    [3:0]            o_axi_arqos,    // Read Protection type
        output  reg                     o_axi_arvalid,  // Read address valid
 
// AXI read data channel signals   
        input   [C_AXI_ID_WIDTH-1:0]     i_axi_rid,     // Response ID
        input   [1:0]                    i_axi_rresp,   // Read response
        input                           i_axi_rvalid,  // Read reponse valid
        input   [C_AXI_DATA_WIDTH-1:0]   i_axi_rdata,    // Read data
        input                           i_axi_rlast,    // Read last
        output  wire                    o_axi_rready,  // Read Response ready
 
        // We'll share the clock and the reset
        input                           i_wb_cyc,
        input                           i_wb_stb,
        input                           i_wb_we,
        input           [(AW-1):0]       i_wb_addr,
        input           [(DW-1):0]       i_wb_data,
        input           [(DW/8-1):0]     i_wb_sel,
        output  reg                     o_wb_ack,
        output  wire                    o_wb_stall,
        output  reg     [(DW-1):0]       o_wb_data,
        output  reg                     o_wb_err
);
 
//*****************************************************************************
// Parameter declarations
//*****************************************************************************
 
        localparam      CTL_SIG_WIDTH   = 3;    // Control signal width
        localparam      RD_STS_WIDTH    = 16;   // Read status signal width
        localparam      WR_STS_WIDTH    = 16;   // Write status signal width
 
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
 
// Things we're not changing ...
        assign o_axi_awlen = 8'h0;      // Burst length is one
        assign o_axi_awsize = 3'b101;   // maximum bytes per burst is 32
        assign o_axi_awburst = 2'b01;   // Incrementing address (ignored)
        assign o_axi_arburst = 2'b01;   // Incrementing address (ignored)
        assign o_axi_awlock  = 1'b0;    // Normal signaling
        assign o_axi_arlock  = 1'b0;    // Normal signaling
        assign o_axi_awcache = 4'h2;    // Normal: no cache, no buffer
        assign o_axi_arcache = 4'h2;    // Normal: no cache, no buffer
        assign o_axi_awprot  = 3'b010;  // Unpriviledged, unsecure, data access
        assign o_axi_arprot  = 3'b010;  // Unpriviledged, unsecure, data access
        assign o_axi_awqos  = 4'h0;     // Lowest quality of service (unused)
        assign o_axi_arqos  = 4'h0;     // Lowest quality of service (unused)
 
// Command logic
// Write address logic
 
        always @(posedge i_clk)
                o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
                        ||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
 
        generate
        if (DW == 32)
        begin
                always @(posedge i_clk)
                        if (!o_wb_stall) // 26 bit address becomes 28 bit ...
                                o_axi_awaddr <= { i_wb_addr[AW-1:2], 4'b00 };
        end else if (DW == 128)
        begin
                always @(posedge i_clk)
                        if (!o_wb_stall) // 28 bit address ...
                                o_axi_awaddr <= { i_wb_addr[AW-1:0], 4'b00 };
        end endgenerate
 
        reg     [5:0]    transaction_id;
        always @(posedge i_clk)
                if (!i_wb_cyc)
                        transaction_id <= 6'h00;
                else if ((i_wb_stb)&&(~o_wb_stall))
                        transaction_id <= transaction_id + 6'h01;
        always @(posedge i_clk)
                if ((i_wb_stb)&&(~o_wb_stall))
                        o_axi_awid <= transaction_id;
 
// Read address logic
        assign  o_axi_arid = o_axi_awid;
        assign  o_axi_araddr = o_axi_awaddr;
        assign  o_axi_arlen  = o_axi_awlen;
        assign  o_axi_arsize = 3'b101;  // maximum bytes per burst is 32
        always @(posedge i_clk)
                o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
                        ||(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready);
 
 
// Write data logic
        generate
        if (DW == 32)
        begin
                always @(posedge i_clk)
                        if (!o_wb_stall)
                                o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
                always @(posedge i_clk)
                        if (!o_wb_stall)
                        case(i_wb_addr[1:0])
                        2'b00:o_axi_wstrb<={    4'h0,    4'h0,   4'h0,i_wb_sel};
                        2'b01:o_axi_wstrb<={    4'h0,    4'h0,i_wb_sel,   4'h0};
                        2'b10:o_axi_wstrb<={    4'h0,i_wb_sel,    4'h0,   4'h0};
                        2'b11:o_axi_wstrb<={i_wb_sel,    4'h0,    4'h0,   4'h0};
                        endcase
        end else if (DW == 128)
        begin
                always @(posedge i_clk)
                        if (!o_wb_stall)
                                o_axi_wdata <= i_wb_data;
                always @(posedge i_clk)
                        if (!o_wb_stall)
                                o_axi_wstrb <= i_wb_sel;
        end endgenerate
 
        assign  o_axi_wlast = 1'b1;
        always @(posedge i_clk)
                o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
                        ||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
 
// Read data channel / response logic
        assign  o_axi_rready = 1'b1;
        assign  o_axi_bready = 1'b1;
 
        wire    w_fifo_full;
        generate
        if (STRICT_ORDER == 0)
        begin
                // Reorder FIFO
                //
                localparam      LGFIFOLN = C_AXI_ID_WIDTH;
                localparam      FIFOLN = (1<<LGFIFOLN);
                // FIFO reorder buffer
                reg     [(LGFIFOLN-1):0] fifo_tail;
                reg     [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
                reg     [(FIFOLN-1):0]   reorder_fifo_valid;
                reg     [(FIFOLN-1):0]   reorder_fifo_err;
 
                initial reorder_fifo_valid = 0;
                initial reorder_fifo_err = 0;
 
                if (DW == 32)
                begin
                        reg     [1:0]    reorder_fifo_addr [0:(FIFOLN-1)];
 
 
                        reg     [1:0]    low_addr;
                        always @(posedge i_clk)
                                if ((i_wb_stb)&&(!o_wb_stall))
                                        low_addr <= i_wb_addr[1:0];
                        always @(posedge i_clk)
                                if ((o_axi_arvalid)&&(i_axi_arready))
                                        reorder_fifo_addr[o_axi_arid] <= low_addr;
 
                        always @(posedge i_clk)
                        case(reorder_fifo_addr[fifo_tail][1:0])
                        2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
                        2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
                        2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
                        2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
                        endcase
 
                end else if (DW == 128)
                begin
                        always @(posedge i_clk)
                                o_wb_data <= reorder_fifo_data[fifo_tail];
                end
 
 
                wire    [(LGFIFOLN-1):0] fifo_head;
                assign  fifo_head = transaction_id;
 
                // Let's do some math to figure out where the FIFO head will
                // point to next, but let's also insist that it be LGFIFOLN
                // bits in size as well.  This'll be part of the fifo_full
                // calculation below.
                wire    [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
                assign  n_fifo_head = fifo_head+1'b1;
                assign  nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };
 
                always @(posedge i_clk)
                begin
                        if ((i_axi_rvalid)&&(o_axi_rready))
                                reorder_fifo_data[i_axi_rid]<= i_axi_rdata;
                        if ((i_axi_rvalid)&&(o_axi_rready))
                        begin
                                reorder_fifo_valid[i_axi_rid] <= 1'b1;
                                reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1];
                        end
                        if ((i_axi_bvalid)&&(o_axi_bready))
                        begin
                                reorder_fifo_valid[i_axi_bid] <= 1'b1;
                                reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1];
                        end
 
                        if (reorder_fifo_valid[fifo_tail])
                        begin
                                o_wb_ack <= 1'b1;
                                o_wb_err <= reorder_fifo_err[fifo_tail];
                                fifo_tail <= fifo_tail + 6'h1;
                                reorder_fifo_valid[fifo_tail] <= 1'b0;
                                reorder_fifo_err[fifo_tail]   <= 1'b0;
                        end else begin
                                o_wb_ack <= 1'b0;
                                o_wb_err <= 1'b0;
                        end
 
                        if (!i_wb_cyc)
                        begin
                                reorder_fifo_valid <= {(FIFOLN){1'b0}};
                                reorder_fifo_err   <= {(FIFOLN){1'b0}};
                                fifo_tail <= 6'h0;
                                o_wb_err <= 1'b0;
                                o_wb_ack <= 1'b0;
                        end
                end
 
                reg     r_fifo_full;
                always @(posedge i_clk)
                begin
                        if (!i_wb_cyc)
                                r_fifo_full <= 1'b0;
                        else if ((i_wb_stb)&&(~o_wb_stall)
                                        &&(reorder_fifo_valid[fifo_tail]))
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                        else if ((i_wb_stb)&&(~o_wb_stall))
                                r_fifo_full <= (fifo_tail==nn_fifo_head);
                        else if (reorder_fifo_valid[fifo_tail])
                                r_fifo_full <= 1'b0;
                        else
                                r_fifo_full <= (fifo_tail==n_fifo_head);
                end
                assign w_fifo_full = r_fifo_full;
        end else begin
                //
                // Strict ordering, but can only read every fourth addresses
                //
                assign w_fifo_full = 1'b0;
                always @(posedge i_clk)
                        o_wb_data <= i_axi_rdata[31:0];
                always @(posedge i_clk)
                        o_wb_ack <= (i_wb_cyc)&&(
                                ((i_axi_rvalid)&&(o_axi_rready))
                                  ||((i_axi_bvalid)&&(o_axi_bready)));
                always @(posedge i_clk)
                        o_wb_err <= (i_wb_cyc)&&((o_wb_err)
                                ||((i_axi_rvalid)&&(i_axi_rresp[1]))
                                ||((i_axi_bvalid)&&(i_axi_bresp[1])));
        end endgenerate
 
 
        // Now, the difficult signal ... the stall signal
        // Let's build for a single cycle input ... and only stall if something
        // outgoing is valid and nothing is ready.
        assign  o_wb_stall = (i_wb_cyc)&&(
                                (w_fifo_full)
                                ||((o_axi_awvalid)&&(!i_axi_awready))
                                ||((o_axi_wvalid )&&(!i_axi_wready ))
                                ||((o_axi_arvalid)&&(!i_axi_arready)));
endmodule
 

Line No.	Rev	Author	Line
1	2	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: wbm2axisp.v`
4			`//`
5			`// Project: Pipelined Wishbone to AXI converter`
6			`//`
7			`// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as`
8			`// one per clock. The AXI bus allows transactions at a speed of`
9			`// one read and one write transaction per clock. These capabilities work`
10			`// by allowing requests to take place prior to responses, such that the`
11			`// requests might go out at once per clock and take several clocks, and`
12			`// the responses may start coming back several clocks later. In other`
13			`// words, both protocols allow multiple transactions to be "in flight" at`
14			`// the same time. Current wishbone to AXI converters, however, handle only`
15			`// one transaction at a time: initiating the transaction, and then waiting`
16			`// for the transaction to complete before initiating the next.`
17			`//`
18			`// The purpose of this core is to maintain the speed of both busses, while`
19			`// transiting from the Wishbone (as master) to the AXI bus (as slave) and`
20			`// back again.`
21			`//`
22			`// Since the AXI bus allows transactions to be reordered, whereas the`
23			`// wishbone does not, this core can be configured to reorder return`
24			`// transactions as well.`
25			`//`
26			`// Creator: Dan Gisselquist, Ph.D.`
27			`// Gisselquist Technology, LLC`
28			`//`
29			`////////////////////////////////////////////////////////////////////////////////`
30			`//`
31	3	dgisselq	`// Copyright (C) 2016, Gisselquist Technology, LLC`
32	2	dgisselq	`//`
33			`// This program is free software (firmware): you can redistribute it and/or`
34			`// modify it under the terms of the GNU General Public License as published`
35			`// by the Free Software Foundation, either version 3 of the License, or (at`
36			`// your option) any later version.`
37			`//`
38			`// This program is distributed in the hope that it will be useful, but WITHOUT`
39			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
40			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
41			`// for more details.`
42			`//`
43			`// You should have received a copy of the GNU General Public License along`
44			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
45			`// target there if the PDF file isn't present.) If not, see`
46			`// <http://www.gnu.org/licenses/> for a copy.`
47			`//`
48			`// License: GPL, v3, as defined and found on www.gnu.org,`
49			`// http://www.gnu.org/licenses/gpl.html`
50			`//`
51			`//`
52			`////////////////////////////////////////////////////////////////////////////////`
53			`//`
54			`//`
55			`module wbm2axisp #(`
56			`parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W`
57			`// This is an int between 1-16`
58			`parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data`
59	6	dgisselq	`parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width`
60			`parameter DW = 32, // Wishbone data width`
61			`parameter AW = 26, // Wishbone address width`
62	3	dgisselq	`parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder`
63	2	dgisselq	`) (`
64			`input i_clk, // System clock`
65	6	dgisselq	`// input i_reset,// Wishbone reset signal--unused`
66	2	dgisselq
67			`// AXI write address channel signals`
68	5	dgisselq	`input i_axi_awready, // Slave is ready to accept`
69	6	dgisselq	`output reg [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID`
70			`output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address`
71	5	dgisselq	`output wire [7:0] o_axi_awlen, // Write Burst Length`
72			`output wire [2:0] o_axi_awsize, // Write Burst size`
73			`output wire [1:0] o_axi_awburst, // Write Burst type`
74	6	dgisselq	`output wire [0:0] o_axi_awlock, // Write lock type`
75	5	dgisselq	`output wire [3:0] o_axi_awcache, // Write Cache type`
76			`output wire [2:0] o_axi_awprot, // Write Protection type`
77			`output wire [3:0] o_axi_awqos, // Write Quality of Svc`
78			`output reg o_axi_awvalid, // Write address valid`
79	2	dgisselq
80			`// AXI write data channel signals`
81	5	dgisselq	`input i_axi_wready, // Write data ready`
82			`output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data`
83			`output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes`
84			`output wire o_axi_wlast, // Last write transaction`
85			`output reg o_axi_wvalid, // Write valid`
86	2	dgisselq
87			`// AXI write response channel signals`
88	5	dgisselq	`input [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID`
89			`input [1:0] i_axi_bresp, // Write response`
90			`input i_axi_bvalid, // Write reponse valid`
91			`output wire o_axi_bready, // Response ready`
92	2	dgisselq
93			`// AXI read address channel signals`
94	5	dgisselq	`input i_axi_arready, // Read address ready`
95			`output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID`
96	6	dgisselq	`output wire [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address`
97	5	dgisselq	`output wire [7:0] o_axi_arlen, // Read Burst Length`
98			`output wire [2:0] o_axi_arsize, // Read Burst size`
99			`output wire [1:0] o_axi_arburst, // Read Burst type`
100	6	dgisselq	`output wire [0:0] o_axi_arlock, // Read lock type`
101	5	dgisselq	`output wire [3:0] o_axi_arcache, // Read Cache type`
102			`output wire [2:0] o_axi_arprot, // Read Protection type`
103			`output wire [3:0] o_axi_arqos, // Read Protection type`
104			`output reg o_axi_arvalid, // Read address valid`
105	2	dgisselq
106			`// AXI read data channel signals`
107	5	dgisselq	`input [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID`
108			`input [1:0] i_axi_rresp, // Read response`
109			`input i_axi_rvalid, // Read reponse valid`
110			`input [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data`
111			`input i_axi_rlast, // Read last`
112			`output wire o_axi_rready, // Read Response ready`
113	2	dgisselq
114			`// We'll share the clock and the reset`
115	3	dgisselq	`input i_wb_cyc,`
116			`input i_wb_stb,`
117			`input i_wb_we,`
118	6	dgisselq	`input [(AW-1):0] i_wb_addr,`
119			`input [(DW-1):0] i_wb_data,`
120	4	dgisselq	`input [(DW/8-1):0] i_wb_sel,`
121	3	dgisselq	`output reg o_wb_ack,`
122			`output wire o_wb_stall,`
123	6	dgisselq	`output reg [(DW-1):0] o_wb_data,`
124	3	dgisselq	`output reg o_wb_err`
125	2	dgisselq	`);`
126
127			`//*****************************************************************************`
128			`// Parameter declarations`
129			`//*****************************************************************************`
130
131			`localparam CTL_SIG_WIDTH = 3; // Control signal width`
132			`localparam RD_STS_WIDTH = 16; // Read status signal width`
133			`localparam WR_STS_WIDTH = 16; // Write status signal width`
134
135			`//*****************************************************************************`
136			`// Internal register and wire declarations`
137			`//*****************************************************************************`
138
139			`// Things we're not changing ...`
140	5	dgisselq	`assign o_axi_awlen = 8'h0; // Burst length is one`
141			`assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32`
142			`assign o_axi_awburst = 2'b01; // Incrementing address (ignored)`
143			`assign o_axi_arburst = 2'b01; // Incrementing address (ignored)`
144	6	dgisselq	`assign o_axi_awlock = 1'b0; // Normal signaling`
145			`assign o_axi_arlock = 1'b0; // Normal signaling`
146	5	dgisselq	`assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer`
147			`assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer`
148	6	dgisselq	`assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access`
149			`assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access`
150	5	dgisselq	`assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)`
151			`assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)`
152	2	dgisselq
153			`// Command logic`
154			`// Write address logic`
155
156			`always @(posedge i_clk)`
157	5	dgisselq	`o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)`
158			`\|\|(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);`
159	2	dgisselq
160	6	dgisselq	`generate`
161			`if (DW == 32)`
162			`begin`
163			`always @(posedge i_clk)`
164			`if (!o_wb_stall) // 26 bit address becomes 28 bit ...`
165			`o_axi_awaddr <= { i_wb_addr[AW-1:2], 4'b00 };`
166			`end else if (DW == 128)`
167			`begin`
168			`always @(posedge i_clk)`
169			`if (!o_wb_stall) // 28 bit address ...`
170			`o_axi_awaddr <= { i_wb_addr[AW-1:0], 4'b00 };`
171			`end endgenerate`
172
173	2	dgisselq	`reg [5:0] transaction_id;`
174			`always @(posedge i_clk)`
175			`if (!i_wb_cyc)`
176			`transaction_id <= 6'h00;`
177			`else if ((i_wb_stb)&&(~o_wb_stall))`
178			`transaction_id <= transaction_id + 6'h01;`
179	6	dgisselq	`always @(posedge i_clk)`
180			`if ((i_wb_stb)&&(~o_wb_stall))`
181			`o_axi_awid <= transaction_id;`
182	2	dgisselq
183			`// Read address logic`
184	6	dgisselq	`assign o_axi_arid = o_axi_awid;`
185	5	dgisselq	`assign o_axi_araddr = o_axi_awaddr;`
186			`assign o_axi_arlen = o_axi_awlen;`
187			`assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32`
188	2	dgisselq	`always @(posedge i_clk)`
189	5	dgisselq	`o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)`
190			`\|\|(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready);`
191	2	dgisselq
192
193			`// Write data logic`
194	4	dgisselq	`generate`
195			`if (DW == 32)`
196			`begin`
197			`always @(posedge i_clk)`
198			`if (!o_wb_stall)`
199	5	dgisselq	`o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };`
200	4	dgisselq	`always @(posedge i_clk)`
201			`if (!o_wb_stall)`
202			`case(i_wb_addr[1:0])`
203	6	dgisselq	`2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0,i_wb_sel};`
204			`2'b01:o_axi_wstrb<={ 4'h0, 4'h0,i_wb_sel, 4'h0};`
205			`2'b10:o_axi_wstrb<={ 4'h0,i_wb_sel, 4'h0, 4'h0};`
206			`2'b11:o_axi_wstrb<={i_wb_sel, 4'h0, 4'h0, 4'h0};`
207	4	dgisselq	`endcase`
208			`end else if (DW == 128)`
209			`begin`
210			`always @(posedge i_clk)`
211			`if (!o_wb_stall)`
212	5	dgisselq	`o_axi_wdata <= i_wb_data;`
213	4	dgisselq	`always @(posedge i_clk)`
214			`if (!o_wb_stall)`
215	5	dgisselq	`o_axi_wstrb <= i_wb_sel;`
216	4	dgisselq	`end endgenerate`
217
218	5	dgisselq	`assign o_axi_wlast = 1'b1;`
219	2	dgisselq	`always @(posedge i_clk)`
220	5	dgisselq	`o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))`
221			`\|\|(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);`
222	2	dgisselq
223			`// Read data channel / response logic`
224	5	dgisselq	`assign o_axi_rready = 1'b1;`
225			`assign o_axi_bready = 1'b1;`
226	2	dgisselq
227			`wire w_fifo_full;`
228			`generate`
229			`if (STRICT_ORDER == 0)`
230			`begin`
231			`// Reorder FIFO`
232			`//`
233			`localparam LGFIFOLN = C_AXI_ID_WIDTH;`
234			`localparam FIFOLN = (1<<LGFIFOLN);`
235			`// FIFO reorder buffer`
236	3	dgisselq	`reg [(LGFIFOLN-1):0] fifo_tail;`
237			`reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];`
238			`reg [(FIFOLN-1):0] reorder_fifo_valid;`
239			`reg [(FIFOLN-1):0] reorder_fifo_err;`
240
241	6	dgisselq	`initial reorder_fifo_valid = 0;`
242			`initial reorder_fifo_err = 0;`
243
244	4	dgisselq	`if (DW == 32)`
245			`begin`
246			`reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];`
247	3	dgisselq
248
249	4	dgisselq	`reg [1:0] low_addr;`
250			`always @(posedge i_clk)`
251			`if ((i_wb_stb)&&(!o_wb_stall))`
252			`low_addr <= i_wb_addr[1:0];`
253			`always @(posedge i_clk)`
254	5	dgisselq	`if ((o_axi_arvalid)&&(i_axi_arready))`
255			`reorder_fifo_addr[o_axi_arid] <= low_addr;`
256	3	dgisselq
257	4	dgisselq	`always @(posedge i_clk)`
258	6	dgisselq	`case(reorder_fifo_addr[fifo_tail][1:0])`
259	4	dgisselq	`2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];`
260			`2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];`
261			`2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];`
262			`2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];`
263			`endcase`
264
265			`end else if (DW == 128)`
266			`begin`
267			`always @(posedge i_clk)`
268			`o_wb_data <= reorder_fifo_data[fifo_tail];`
269			`end`
270
271
272	3	dgisselq	`wire [(LGFIFOLN-1):0] fifo_head;`
273	2	dgisselq	`assign fifo_head = transaction_id;`
274
275			`// Let's do some math to figure out where the FIFO head will`
276			`// point to next, but let's also insist that it be LGFIFOLN`
277			`// bits in size as well. This'll be part of the fifo_full`
278			`// calculation below.`
279			`wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;`
280			`assign n_fifo_head = fifo_head+1'b1;`
281	6	dgisselq	`assign nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };`
282	2	dgisselq
283			`always @(posedge i_clk)`
284			`begin`
285	5	dgisselq	`if ((i_axi_rvalid)&&(o_axi_rready))`
286			`reorder_fifo_data[i_axi_rid]<= i_axi_rdata;`
287			`if ((i_axi_rvalid)&&(o_axi_rready))`
288	2	dgisselq	`begin`
289	5	dgisselq	`reorder_fifo_valid[i_axi_rid] <= 1'b1;`
290			`reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1];`
291	2	dgisselq	`end`
292	5	dgisselq	`if ((i_axi_bvalid)&&(o_axi_bready))`
293	2	dgisselq	`begin`
294	5	dgisselq	`reorder_fifo_valid[i_axi_bid] <= 1'b1;`
295			`reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1];`
296	2	dgisselq	`end`
297
298			`if (reorder_fifo_valid[fifo_tail])`
299			`begin`
300			`o_wb_ack <= 1'b1;`
301			`o_wb_err <= reorder_fifo_err[fifo_tail];`
302			`fifo_tail <= fifo_tail + 6'h1;`
303			`reorder_fifo_valid[fifo_tail] <= 1'b0;`
304			`reorder_fifo_err[fifo_tail] <= 1'b0;`
305			`end else begin`
306			`o_wb_ack <= 1'b0;`
307			`o_wb_err <= 1'b0;`
308			`end`
309
310			`if (!i_wb_cyc)`
311			`begin`
312			`reorder_fifo_valid <= {(FIFOLN){1'b0}};`
313			`reorder_fifo_err <= {(FIFOLN){1'b0}};`
314			`fifo_tail <= 6'h0;`
315			`o_wb_err <= 1'b0;`
316			`o_wb_ack <= 1'b0;`
317			`end`
318			`end`
319
320	3	dgisselq	`reg r_fifo_full;`
321	2	dgisselq	`always @(posedge i_clk)`
322			`begin`
323			`if (!i_wb_cyc)`
324			`r_fifo_full <= 1'b0;`
325			`else if ((i_wb_stb)&&(~o_wb_stall)`
326			`&&(reorder_fifo_valid[fifo_tail]))`
327			`r_fifo_full <= (fifo_tail==n_fifo_head);`
328			`else if ((i_wb_stb)&&(~o_wb_stall))`
329			`r_fifo_full <= (fifo_tail==nn_fifo_head);`
330			`else if (reorder_fifo_valid[fifo_tail])`
331			`r_fifo_full <= 1'b0;`
332			`else`
333			`r_fifo_full <= (fifo_tail==n_fifo_head);`
334			`end`
335			`assign w_fifo_full = r_fifo_full;`
336			`end else begin`
337	6	dgisselq	`//`
338			`// Strict ordering, but can only read every fourth addresses`
339			`//`
340	3	dgisselq	`assign w_fifo_full = 1'b0;`
341	2	dgisselq	`always @(posedge i_clk)`
342	6	dgisselq	`o_wb_data <= i_axi_rdata[31:0];`
343	2	dgisselq	`always @(posedge i_clk)`
344	6	dgisselq	`o_wb_ack <= (i_wb_cyc)&&(`
345			`((i_axi_rvalid)&&(o_axi_rready))`
346			`\|\|((i_axi_bvalid)&&(o_axi_bready)));`
347	2	dgisselq	`always @(posedge i_clk)`
348	6	dgisselq	`o_wb_err <= (i_wb_cyc)&&((o_wb_err)`
349	5	dgisselq	`\|\|((i_axi_rvalid)&&(i_axi_rresp[1]))`
350			`\|\|((i_axi_bvalid)&&(i_axi_bresp[1])));`
351	3	dgisselq	`end endgenerate`
352	2	dgisselq
353
354			`// Now, the difficult signal ... the stall signal`
355			`// Let's build for a single cycle input ... and only stall if something`
356			`// outgoing is valid and nothing is ready.`
357			`assign o_wb_stall = (i_wb_cyc)&&(`
358			`(w_fifo_full)`
359	5	dgisselq	`\|\|((o_axi_awvalid)&&(!i_axi_awready))`
360			`\|\|((o_axi_wvalid )&&(!i_axi_wready ))`
361			`\|\|((o_axi_arvalid)&&(!i_axi_arready)));`
362	2	dgisselq	`endmodule`
363	5	dgisselq

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