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[/] [wb2hpi/] [trunk/] [apps/] [pci2dsp/] [syn/] [xilinxISE/] [src/] [xilinx.npl] - Blame information for rev 12

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Line No. Rev Author Line
1 2 gvozden
JDF E
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// Created by ISE ver 1.0
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PROJECT xilinx
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DESIGN xilinx Normal
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DEVKIT xc2s200-5pq208
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DEVFAM spartan2
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FLOW EDIF
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MODULE ..\..\synplify\out\pci2dsp.edn
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MODSTYLE TOP Normal
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[STRATEGY-LIST]
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Normal=True, 1034858003
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[Normal]
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xilxNgdbldUCF=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1038923296, ..\ucf\pci2dsp.ucf
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xilxMapPackRegInto=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1035374944, For Inputs and Outputs
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xilxPAReffortLevel=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, Highest
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xilxPARroutingPasses=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, 0
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xilxPARdelayBasedPasses=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, 0
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mpprStartingPlacerCostTbl=edif, SPARTAN2, Implementation.t_mppr, 1027686417, 20
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mpprPARiterations=edif, SPARTAN2, Implementation.t_mppr, 1027687139, 0
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mpprResultsToSave=edif, SPARTAN2, Implementation.t_mppr, 1027687139, 1
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xilxBitgCfg_GenOpt_MaskFile=edif, SPARTAN2, Implementation.t_bitFile, 1034850741, True

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