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https://opencores.org/ocsvn/wb4pb/wb4pb/trunk
[/] [wb4pb/] [trunk/] [impl/] [avnet_sp3a_eval_uart.ucf] - Blame information for rev 27
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ste.fis |
INST DCM_SP_INST CLK_FEEDBACK = NONE;
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INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
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INST DCM_SP_INST CLKFX_DIVIDE = 8;
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INST DCM_SP_INST CLKFX_MULTIPLY = 25;
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INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
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INST DCM_SP_INST CLKIN_PERIOD = 62.500;
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INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
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INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
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INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
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INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
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INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
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INST DCM_SP_INST FACTORY_JF = C080;
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INST DCM_SP_INST PHASE_SHIFT = 0;
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INST DCM_SP_INST STARTUP_WAIT = FALSE;
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NET CLK_16MHZ TNM_NET = CLK_16MHZ;
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TIMESPEC TS_CLK_16MHZ = PERIOD CLK_16MHZ 62.50 ns;
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NET CLK_16MHZ LOC = C10 | IOSTANDARD = LVCMOS33 ;
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NET FPGA_RESET LOC = H4 | IOSTANDARD = LVCMOS33 ;
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NET LED1 LOC = D14 | IOSTANDARD = LVCMOS33 ;
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25 |
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NET UART_RXD LOC = B3 | IOSTANDARD = LVCMOS33 ;
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NET UART_TXD LOC = A3 | IOSTANDARD = LVCMOS33 ;
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