OpenCores
URL https://opencores.org/ocsvn/wb4pb/wb4pb/trunk

Subversion Repositories wb4pb

[/] [wb4pb/] [trunk/] [impl/] [avnet_sp3a_eval_uart_vlog.v] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 ste.fis
////////////////////////////////////////////////////////////////////////////////
2
// This sourcecode is released under BSD license.
3
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
4
////////////////////////////////////////////////////////////////////////////////
5
//
6
// Copyright (c) 2011, Stefan Fischer <Ste.Fis@OpenCores.org>
7
// All rights reserved.
8
//
9
// Redistribution and use in source and binary forms, with or without 
10
// modification, are permitted provided that the following conditions are met:
11
//
12
//  * Redistributions of source code must retain the above copyright notice, 
13
//    this list of conditions and the following disclaimer.
14
//  * Redistributions in binary form must reproduce the above copyright notice,
15
//    this list of conditions and the following disclaimer in the documentation
16
//    and/or other materials provided with the distribution. 
17
//  * Neither the name of the author nor the names of his contributors may be 
18
//    used to endorse or promote products derived from this software without 
19
//    specific prior written permission.
20
//
21
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
22
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
23
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
24
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
25
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
26
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
27
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
28
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
29
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
30
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
31
// POSSIBILITY OF SUCH DAMAGE.
32
//
33
////////////////////////////////////////////////////////////////////////////////
34
// filename: avnet_sp3a_eval_uart_vlog.v
35
// description: synthesizable PicoBlaze (TM) uart example using wishbone /
36
//              AVNET (R) Sp3A-Eval-Kit version
37
// todo4user: add other modules as needed
38
// version: 0.0.0
39
// changelog: - 0.0.0, initial release
40
//            - ...
41
////////////////////////////////////////////////////////////////////////////////
42
 
43
 
44
module avnet_sp3a_eval_uart_vlog (
45
  FPGA_RESET,
46
  CLK_16MHZ,
47
 
48
  UART_TXD,
49
  UART_RXD,
50
 
51
  LED1
52
);
53
 
54
  input FPGA_RESET;
55
  wire  FPGA_RESET;
56
  input CLK_16MHZ;
57
  wire  CLK_16MHZ;
58
 
59
  input UART_TXD;
60
  wire  UART_TXD;
61
  output UART_RXD;
62
  wire   UART_RXD;
63
 
64
  output LED1;
65
  wire   LED1;
66
 
67
  reg rst;
68
  wire clk;
69
 
70
  wire wb_cyc;
71
  wire wb_stb;
72
  wire wb_we;
73
  wire[7:0] wb_adr;
74
  wire[7:0] wb_dat_m2s;
75
  wire[7:0] wb_dat_s2m;
76
  wire wb_ack;
77
 
78
  wire pb_write_strobe;
79
  wire pb_read_strobe;
80
  wire[7:0] pb_port_id;
81
  wire[7:0] pb_in_port;
82
  wire[7:0] pb_out_port;
83
 
84
  wire[17:0] instruction;
85
  wire[9:0] address;
86
 
87
  wire interrupt;
88
  wire interrupt_ack;
89
 
90
  reg[23:0] timer;
91
 
92
  wire dcm_locked;
93
 
94
  // 50 mhz clock generation
95
  DCM_SP # (
96
    .CLK_FEEDBACK("NONE"),
97
    .CLKDV_DIVIDE(2.0),
98
    .CLKFX_DIVIDE(8),
99
    .CLKFX_MULTIPLY(25),
100
    .CLKIN_DIVIDE_BY_2("FALSE"),
101
    .CLKIN_PERIOD(62.500),
102
    .CLKOUT_PHASE_SHIFT("NONE"),
103
    .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
104
    .DFS_FREQUENCY_MODE("LOW"),
105
    .DLL_FREQUENCY_MODE("LOW"),
106
    .DUTY_CYCLE_CORRECTION("TRUE"),
107
    .FACTORY_JF(16'hC080),
108
    .PHASE_SHIFT(0),
109
    .STARTUP_WAIT("FALSE")
110
  )
111
  DCM_SP_INST (
112
    .CLKFB(1'B0),
113
    .CLKIN(CLK_16MHZ),
114
    .DSSEN(1'B0),
115
    .PSCLK(1'B0),
116
    .PSEN(1'B0),
117
    .PSINCDEC(1'B0),
118
    .RST(FPGA_RESET),
119
    .CLKDV(),
120
    .CLKFX(clk),
121
    .CLKFX180(),
122
    .CLK0(),
123
    .CLK2X(),
124
    .CLK2X180(),
125
    .CLK90(),
126
    .CLK180(),
127
    .CLK270(),
128
    .LOCKED(dcm_locked),
129
    .PSDONE(),
130
    .STATUS()
131
  );
132
 
133
  // reset synchronisation
134
  always@(clk)
135
    rst <= ! dcm_locked;
136
 
137
  // module instances
138
  ///////////////////
139
 
140
  kcpsm3 inst_kcpsm3 (
141
    .address(address),
142
    .instruction(instruction),
143
    .port_id(pb_port_id),
144
    .write_strobe(pb_write_strobe),
145
    .out_port(pb_out_port),
146
    .read_strobe(pb_read_strobe),
147
    .in_port(pb_in_port),
148
    .interrupt(interrupt),
149
    .interrupt_ack(interrupt_ack),
150
    .reset(rst),
151
    .clk(clk)
152
  );
153
 
154
  pbwbuart inst_pbwbuart (
155
    .address(address),
156
    .instruction(instruction),
157
    .clk(clk)
158
  );
159
 
160
  wbm_picoblaze inst_wbm_picoblaze (
161
    .rst(rst),
162
    .clk(clk),
163
 
164
    .wbm_cyc_o(wb_cyc),
165
    .wbm_stb_o(wb_stb),
166
    .wbm_we_o(wb_we),
167
    .wbm_adr_o(wb_adr),
168
    .wbm_dat_m2s_o(wb_dat_m2s),
169
    .wbm_dat_s2m_i(wb_dat_s2m),
170
    .wbm_ack_i(wb_ack),
171
 
172
    .pb_port_id_i(pb_port_id),
173
    .pb_write_strobe_i(pb_write_strobe),
174
    .pb_out_port_i(pb_out_port),
175
    .pb_read_strobe_i(pb_read_strobe),
176
    .pb_in_port_o(pb_in_port)
177
  );
178
 
179
  wbs_uart inst_wbs_uart (
180
    .rst(rst),
181
    .clk(clk),
182
 
183
    .wbs_cyc_i(wb_cyc),
184
    .wbs_stb_i(wb_stb),
185
    .wbs_we_i(wb_we),
186
    .wbs_adr_i(wb_adr),
187
    .wbs_dat_m2s_i(wb_dat_m2s),
188
    .wbs_dat_s2m_o(wb_dat_s2m),
189
    .wbs_ack_o(wb_ack),
190
 
191
    .uart_rx_si_i(UART_TXD),
192
    .uart_tx_so_o(UART_RXD)
193
  );
194
 
195
  assign LED1 = timer[23];
196
 
197
  always@(posedge clk) begin : led_blinker
198
    timer <= timer + 1;
199
    if (rst)
200
      timer <= {24{1'b0}};
201
  end
202
 
203
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.