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[/] [wb4pb/] [trunk/] [impl/] [avnet_sp3a_eval_uart_vlog.v] - Blame information for rev 26

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1 24 ste.fis
////////////////////////////////////////////////////////////////////////////////
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// This sourcecode is released under BSD license.
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// Please see http://www.opensource.org/licenses/bsd-license.php for details!
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011, Stefan Fischer <Ste.Fis@OpenCores.org>
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without 
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// modification, are permitted provided that the following conditions are met:
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//
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//  * Redistributions of source code must retain the above copyright notice, 
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//    this list of conditions and the following disclaimer.
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//  * Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution. 
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//  * Neither the name of the author nor the names of his contributors may be 
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//    used to endorse or promote products derived from this software without 
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//    specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
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// POSSIBILITY OF SUCH DAMAGE.
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//
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////////////////////////////////////////////////////////////////////////////////
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// filename: avnet_sp3a_eval_uart_vlog.v
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// description: synthesizable PicoBlaze (TM) uart example using wishbone /
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//              AVNET (R) Sp3A-Eval-Kit version
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// todo4user: add other modules as needed
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// version: 0.0.0
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// changelog: - 0.0.0, initial release
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//            - ...
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////////////////////////////////////////////////////////////////////////////////
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module avnet_sp3a_eval_uart_vlog (
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  FPGA_RESET,
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  CLK_16MHZ,
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  UART_TXD,
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  UART_RXD,
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  LED1
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);
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  input FPGA_RESET;
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  wire  FPGA_RESET;
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  input CLK_16MHZ;
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  wire  CLK_16MHZ;
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  input UART_TXD;
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  wire  UART_TXD;
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  output UART_RXD;
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  wire   UART_RXD;
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  output LED1;
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  wire   LED1;
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  reg rst;
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  wire clk;
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  wire wb_cyc;
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  wire wb_stb;
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  wire wb_we;
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  wire[7:0] wb_adr;
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  wire[7:0] wb_dat_m2s;
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  wire[7:0] wb_dat_s2m;
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  wire wb_ack;
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  wire pb_write_strobe;
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  wire pb_read_strobe;
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  wire[7:0] pb_port_id;
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  wire[7:0] pb_in_port;
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  wire[7:0] pb_out_port;
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  wire[17:0] instruction;
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  wire[9:0] address;
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  wire interrupt;
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  wire interrupt_ack;
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  reg[23:0] timer;
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  wire dcm_locked;
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  // 50 mhz clock generation
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  DCM_SP # (
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    .CLK_FEEDBACK("NONE"),
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    .CLKDV_DIVIDE(2.0),
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    .CLKFX_DIVIDE(8),
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    .CLKFX_MULTIPLY(25),
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    .CLKIN_DIVIDE_BY_2("FALSE"),
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    .CLKIN_PERIOD(62.500),
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    .CLKOUT_PHASE_SHIFT("NONE"),
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    .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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    .DFS_FREQUENCY_MODE("LOW"),
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    .DLL_FREQUENCY_MODE("LOW"),
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    .DUTY_CYCLE_CORRECTION("TRUE"),
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    .FACTORY_JF(16'hC080),
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    .PHASE_SHIFT(0),
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    .STARTUP_WAIT("FALSE")
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  )
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  DCM_SP_INST (
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    .CLKFB(1'B0),
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    .CLKIN(CLK_16MHZ),
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    .DSSEN(1'B0),
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    .PSCLK(1'B0),
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    .PSEN(1'B0),
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    .PSINCDEC(1'B0),
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    .RST(FPGA_RESET),
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    .CLKDV(),
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    .CLKFX(clk),
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    .CLKFX180(),
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    .CLK0(),
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    .CLK2X(),
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    .CLK2X180(),
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    .CLK90(),
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    .CLK180(),
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    .CLK270(),
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    .LOCKED(dcm_locked),
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    .PSDONE(),
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    .STATUS()
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  );
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  // reset synchronisation
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  always@(clk)
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    rst <= ! dcm_locked;
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  // module instances
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  ///////////////////
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  kcpsm3 inst_kcpsm3 (
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    .address(address),
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    .instruction(instruction),
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    .port_id(pb_port_id),
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    .write_strobe(pb_write_strobe),
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    .out_port(pb_out_port),
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    .read_strobe(pb_read_strobe),
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    .in_port(pb_in_port),
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    .interrupt(interrupt),
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    .interrupt_ack(interrupt_ack),
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    .reset(rst),
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    .clk(clk)
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  );
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  pbwbuart inst_pbwbuart (
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    .address(address),
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    .instruction(instruction),
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    .clk(clk)
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  );
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  wbm_picoblaze inst_wbm_picoblaze (
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    .rst(rst),
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    .clk(clk),
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    .wbm_cyc_o(wb_cyc),
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    .wbm_stb_o(wb_stb),
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    .wbm_we_o(wb_we),
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    .wbm_adr_o(wb_adr),
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    .wbm_dat_m2s_o(wb_dat_m2s),
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    .wbm_dat_s2m_i(wb_dat_s2m),
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    .wbm_ack_i(wb_ack),
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    .pb_port_id_i(pb_port_id),
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    .pb_write_strobe_i(pb_write_strobe),
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    .pb_out_port_i(pb_out_port),
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    .pb_read_strobe_i(pb_read_strobe),
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    .pb_in_port_o(pb_in_port)
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  );
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  wbs_uart inst_wbs_uart (
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    .rst(rst),
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    .clk(clk),
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    .wbs_cyc_i(wb_cyc),
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    .wbs_stb_i(wb_stb),
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    .wbs_we_i(wb_we),
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    .wbs_adr_i(wb_adr),
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    .wbs_dat_m2s_i(wb_dat_m2s),
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    .wbs_dat_s2m_o(wb_dat_s2m),
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    .wbs_ack_o(wb_ack),
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    .uart_rx_si_i(UART_TXD),
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    .uart_tx_so_o(UART_RXD)
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  );
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  assign LED1 = timer[23];
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  always@(posedge clk) begin : led_blinker
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    timer <= timer + 1;
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    if (rst)
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      timer <= {24{1'b0}};
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  end
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endmodule

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