OpenCores
URL https://opencores.org/ocsvn/wb4pb/wb4pb/trunk

Subversion Repositories wb4pb

[/] [wb4pb/] [trunk/] [rtl/] [wbm_picoblaze.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ste.fis
////////////////////////////////////////////////////////////////////////////////
2
// This sourcecode is released under BSD license.
3
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
4
////////////////////////////////////////////////////////////////////////////////
5
//
6
// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
7
// All rights reserved.
8
//
9
// Redistribution and use in source and binary forms, with or without 
10
// modification, are permitted provided that the following conditions are met:
11
//
12
//  * Redistributions of source code must retain the above copyright notice, 
13
//    this list of conditions and the following disclaimer.
14
//  * Redistributions in binary form must reproduce the above copyright notice,
15
//    this list of conditions and the following disclaimer in the documentation
16
//    and/or other materials provided with the distribution. 
17
//  * Neither the name of the author nor the names of his contributors may be 
18
//    used to endorse or promote products derived from this software without 
19
//    specific prior written permission.
20
//
21
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
22
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
23
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
24
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
25
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
26
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
27
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
28
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
29
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
30
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
31
// POSSIBILITY OF SUCH DAMAGE.
32
//
33
////////////////////////////////////////////////////////////////////////////////
34
// filename: wbm_picoblaze.v
35
// description: synthesizable wishbone master adapter for PicoBlaze (TM),
36
//              working together with "wb_wr" and "wb_rd" assembler subroutines
37
// todo4user: module should not be changed!
38
// version: 0.0.0
39
// changelog: - 0.0.0, initial release
40
//            - ...
41
////////////////////////////////////////////////////////////////////////////////
42
 
43
 
44
module wbm_picoblaze (
45
  rst,
46
  clk,
47
 
48
  wbm_cyc_o,
49
  wbm_stb_o,
50
  wbm_we_o,
51
  wbm_adr_o,
52
  wbm_dat_m2s_o,
53
  wbm_dat_s2m_i,
54
  wbm_ack_i,
55
 
56
  pb_port_id_i,
57
  pb_write_strobe_i,
58
  pb_out_port_i,
59
  pb_read_strobe_i,
60
  pb_in_port_o
61
);
62
 
63
  input rst;
64
  wire  rst;
65
  input clk;
66
  wire  clk;
67
 
68
  output wbm_cyc_o;
69
  reg    wbm_cyc_o;
70
  output wbm_stb_o;
71
  reg    wbm_stb_o;
72
  output wbm_we_o;
73
  reg    wbm_we_o;
74
  output[7:0] wbm_adr_o;
75
  reg   [7:0] wbm_adr_o;
76
  output[7:0] wbm_dat_m2s_o;
77
  reg   [7:0] wbm_dat_m2s_o;
78
  input[7:0] wbm_dat_s2m_i;
79
  wire [7:0] wbm_dat_s2m_i;
80
  input wbm_ack_i;
81
  wire  wbm_ack_i;
82
 
83
  input[7:0] pb_port_id_i;
84
  wire [7:0] pb_port_id_i;
85
  input pb_write_strobe_i;
86
  wire  pb_write_strobe_i;
87
  input[7:0] pb_out_port_i;
88
  wire [7:0] pb_out_port_i;
89
  input pb_read_strobe_i;
90
  wire  pb_read_strobe_i;
91
  output[7:0] pb_in_port_o;
92
  reg   [7:0] pb_in_port_o;
93
 
94
  reg[7:0] wb_buffer;
95
 
96
  parameter[7:0] WB_ACK_FLAG = 8'h01;
97
 
98
  parameter[1:0]
99
    S_IDLE = 2'b00,
100
    S_WAIT_ON_WB_ACK = 2'b01,
101
    S_SOFTWARE_HANDSHAKE = 2'b10,
102
    S_SOFTWARE_READ = 2'b11
103
  ;
104
  reg[1:0] state;
105
 
106
  always@(wbm_stb_o) wbm_cyc_o = wbm_stb_o;
107
 
108
  always@(posedge clk) begin
109
 
110
    case(state)
111
      S_IDLE:
112
        // setting up wishbone address, data and control signals from 
113
        // PicoBlaze (TM) signals
114
        if (pb_write_strobe_i) begin
115
          wbm_stb_o <= 1'b1;
116
          wbm_we_o <= 1'b1;
117
          wbm_adr_o <= pb_port_id_i;
118
          wbm_dat_m2s_o <= pb_out_port_i;
119
          state <= S_WAIT_ON_WB_ACK;
120
        end else if (pb_read_strobe_i) begin
121
          wbm_stb_o <= 1'b1;
122
          wbm_we_o <= 1'b0;
123
          wbm_adr_o <= pb_port_id_i;
124
          state <= S_WAIT_ON_WB_ACK;
125
        end
126
      S_WAIT_ON_WB_ACK:
127
        // waiting on slave peripheral to complete wishbone transfer cycle
128
        if (wbm_ack_i) begin
129
          wbm_stb_o <= 1'b0;
130
          wb_buffer <= wbm_dat_s2m_i;
131
          pb_in_port_o <= WB_ACK_FLAG;
132
          state <= S_SOFTWARE_HANDSHAKE;
133
        end
134
      S_SOFTWARE_HANDSHAKE:
135
        // software recognition of wishbone handshake
136
        if (pb_read_strobe_i) begin
137
          // transfer complete for a write access
138
          if (wbm_we_o) begin
139
            pb_in_port_o <= 8'h00;
140
            state <= S_IDLE;
141
          // presenting valid wishbone data to PicoBlaze (TM) port in read 
142
          // access
143
          end else begin
144
            pb_in_port_o <= wb_buffer;
145
            state <= S_SOFTWARE_READ;
146
          end
147
        end
148
      S_SOFTWARE_READ:
149
        // transfer complete for a read access after software recognition of
150
        // wishbone data
151
        if (pb_read_strobe_i) begin
152
          pb_in_port_o <= 8'h00;
153
          state <= S_IDLE;
154
        end
155
      default: ;
156
    endcase
157
 
158
    if (rst) begin
159
      wbm_stb_o <= 1'b0;
160
      pb_in_port_o <= 8'h00;
161
      state <= S_IDLE;
162
    end
163
 
164
  end
165
 
166
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.