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[/] [wb4pb/] [trunk/] [rtl/] [wbs_uart.vhd] - Blame information for rev 20

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1 12 ste.fis
--------------------------------------------------------------------------------
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-- This sourcecode is released under BSD license.
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-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
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--------------------------------------------------------------------------------
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--
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-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without 
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-- modification, are permitted provided that the following conditions are met:
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--
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--  * Redistributions of source code must retain the above copyright notice, 
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--    this list of conditions and the following disclaimer.
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--  * Redistributions in binary form must reproduce the above copyright notice,
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--    this list of conditions and the following disclaimer in the documentation
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--    and/or other materials provided with the distribution. 
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--  * Neither the name of the author nor the names of his contributors may be 
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--    used to endorse or promote products derived from this software without 
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--    specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--------------------------------------------------------------------------------
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-- filename: wbs_uart.vhd
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-- description: synthesizable wishbone slave uart sio module using Xilinx (R)
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--              macros and adding some functionality like a configurable 
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--              baud rate and buffer level checking 
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-- todo4user: add other uart functionality as needed, i. e. interrupt logic or
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--            modem control signals
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-- version: 0.0.0
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-- changelog: - 0.0.0, initial release
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--            - ...
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity wbs_uart is
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  port
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  (
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    rst : in std_logic;
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    clk : in std_logic;
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    wbs_cyc_i : in std_logic;
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    wbs_stb_i : in std_logic;
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    wbs_we_i : in std_logic;
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    wbs_adr_i : in std_logic_vector(7 downto 0);
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    wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
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    wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
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    wbs_ack_o : out std_logic;
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    uart_rx_si_i : in std_logic;
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    uart_tx_so_o : out std_logic
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  );
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end wbs_uart;
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architecture rtl of wbs_uart is
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  signal wbs_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
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  signal wbs_ack : std_logic := '0';
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  signal uart_tx_so : std_logic := '0';
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  signal wb_reg_we : std_logic := '0';
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  constant ADDR_MSB : natural := 1;
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  constant UART_RXTX_ADDR : std_logic_vector(7 downto 0) := x"00";
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  constant UART_SR_ADDR : std_logic_vector(7 downto 0) := x"01";
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  constant UART_SR_RX_F_FLAG : natural := 0;
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  constant UART_SR_RX_HF_FLAG : natural := 1;
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  constant UART_SR_RX_DP_FLAG : natural := 2;
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  constant UART_SR_TX_F_FLAG : natural := 4;
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  constant UART_SR_TX_HF_FLAG : natural := 5;
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  constant UART_BAUD_LO_ADDR : std_logic_vector(7 downto 0) := x"02";
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  constant UART_BAUD_HI_ADDR : std_logic_vector(7 downto 0) := x"03";
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  signal baud_count : std_logic_vector(15 downto 0) := (others => '0');
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  signal baud_limit : std_logic_vector(15 downto 0) := (others => '0');
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  signal en_16_x_baud : std_logic := '0';
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  component uart_rx is
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    port
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    (
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      serial_in : in std_logic;
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      data_out : out std_logic_vector(7 downto 0);
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      read_buffer : in std_logic;
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      reset_buffer : in std_logic;
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      en_16_x_baud : in std_logic;
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      buffer_data_present : out std_logic;
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      buffer_full : out std_logic;
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      buffer_half_full : out std_logic;
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      clk : in std_logic
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    );
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  end component;
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  signal rx_read_buffer : std_logic := '0';
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  signal rx_buffer_full : std_logic := '0';
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  signal rx_buffer_half_full : std_logic := '0';
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  signal rx_buffer_data_present : std_logic := '0';
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  signal rx_data_out : std_logic_vector(7 downto 0) := (others => '0');
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  component uart_tx is
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    port
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    (
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      data_in : in std_logic_vector(7 downto 0);
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      write_buffer : in std_logic;
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      reset_buffer : in std_logic;
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      en_16_x_baud : in std_logic;
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      serial_out : out std_logic;
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      buffer_full : out std_logic;
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      buffer_half_full : out std_logic;
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      clk : in std_logic
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    );
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  end component;
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  signal tx_write_buffer : std_logic := '0';
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  signal tx_buffer_full : std_logic := '0';
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  signal tx_buffer_half_full : std_logic := '0';
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begin
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  wbs_dat_s2m_o <= wbs_dat_s2m;
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  wbs_ack_o <= wbs_ack;
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  uart_tx_so_o <= uart_tx_so;
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  -- internal register write enable signal
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  wb_reg_we <= wbs_cyc_i and wbs_stb_i and wbs_we_i;
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  process(clk)
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  begin
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    if clk'event and clk = '1' then
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      -- baud rate configuration:
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      -- baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
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      -- i. e. 9600 baud at 50 MHz system clock =>
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      -- baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
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      -- baud timer
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      if baud_count = baud_limit then
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        baud_count <= (others => '0');
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        en_16_x_baud <= '1';
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      else
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        baud_count <= std_logic_vector(unsigned(baud_count) + 1);
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        en_16_x_baud <= '0';
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      end if;
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      rx_read_buffer <= '0';
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      tx_write_buffer <= '0';
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      wbs_dat_s2m <= (others => '0');
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      -- registered wishbone slave handshake (default)
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      wbs_ack <= wbs_cyc_i and wbs_stb_i and (not wbs_ack);
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      case wbs_adr_i(ADDR_MSB downto 0) is
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        -- receive/transmit buffer access
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        when UART_RXTX_ADDR(ADDR_MSB downto 0) =>
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          if (wbs_cyc_i and wbs_stb_i) = '1' then
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            -- overwriting wishbone slave handshake for blocking transactions 
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            -- to rx/tx fifos by using buffer status flags
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            if wbs_we_i = '1' then
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              tx_write_buffer <= (not tx_buffer_full) and (not wbs_ack);
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              wbs_ack <= (not tx_buffer_full) and (not wbs_ack);
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            else
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              rx_read_buffer <= rx_buffer_data_present and (not wbs_ack);
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              wbs_ack <= rx_buffer_data_present and (not wbs_ack);
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            end if;
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          end if;
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          wbs_dat_s2m <= rx_data_out;
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        -- status register access
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        when UART_SR_ADDR(ADDR_MSB downto 0) =>
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          wbs_dat_s2m(UART_SR_RX_F_FLAG) <= rx_buffer_full;
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          wbs_dat_s2m(UART_SR_RX_HF_FLAG) <= rx_buffer_half_full;
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          wbs_dat_s2m(UART_SR_RX_DP_FLAG) <= rx_buffer_data_present;
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          wbs_dat_s2m(UART_SR_TX_F_FLAG) <= tx_buffer_full;
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          wbs_dat_s2m(UART_SR_TX_HF_FLAG) <= tx_buffer_half_full;
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        -- baud rate register access / low byte
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        when UART_BAUD_LO_ADDR(ADDR_MSB downto 0) =>
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          if wb_reg_we = '1' then
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            baud_limit(7 downto 0) <= wbs_dat_m2s_i;
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            baud_count <= (others => '0');
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          end if;
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          wbs_dat_s2m <= baud_limit(7 downto 0);
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        -- baud rate register access / high byte
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        when UART_BAUD_HI_ADDR(ADDR_MSB downto 0) =>
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          if wb_reg_we = '1' then
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            baud_limit(15 downto 8) <= wbs_dat_m2s_i;
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            baud_count <= (others => '0');
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          end if;
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          wbs_dat_s2m <= baud_limit(15 downto 8);
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        when others => null;
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      end case;
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      if rst = '1' then
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        wbs_ack <= '0';
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      end if;
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    end if;
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  end process;
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  -- Xilinx (R) uart macro instances
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  ----------------------------------
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  inst_uart_rx : uart_rx
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    port map
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    (
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      serial_in => uart_rx_si_i,
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      data_out => rx_data_out,
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      read_buffer => rx_read_buffer,
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      reset_buffer => rst,
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      en_16_x_baud => en_16_x_baud,
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      buffer_data_present => rx_buffer_data_present,
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      buffer_full => rx_buffer_full,
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      buffer_half_full => rx_buffer_half_full,
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      clk => clk
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    );
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  inst_uart_tx : uart_tx
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    port map
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    (
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      data_in => wbs_dat_m2s_i,
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      write_buffer => tx_write_buffer,
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      reset_buffer => rst,
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      en_16_x_baud => en_16_x_baud,
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      serial_out => uart_tx_so,
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      buffer_full => tx_buffer_full,
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      buffer_half_full => tx_buffer_half_full,
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      clk => clk
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    );
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end rtl;

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