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ste.fis |
################################################################################
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## This sourcecode is released under BSD license.
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## Please see http://www.opensource.org/licenses/bsd-license.php for details!
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################################################################################
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##
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## Copyright (c) 2010, Stefan Fischer
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## All rights reserved.
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##
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## Redistribution and use in source and binary forms, with or without
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## modification, are permitted provided that the following conditions are met:
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##
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## * Redistributions of source code must retain the above copyright notice,
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## this list of conditions and the following disclaimer.
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## * Redistributions in binary form must reproduce the above copyright notice,
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## this list of conditions and the following disclaimer in the documentation
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## and/or other materials provided with the distribution.
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## * Neither the name of the author nor the names of his contributors may be
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## used to endorse or promote products derived from this software without
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## specific prior written permission.
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##
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## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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## POSSIBILITY OF SUCH DAMAGE.
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##
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################################################################################
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## filename: picoblaze_wb_uart_tb.do
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## description: ModelSim (R) do-macro / tcl-script for picoblaze_wb_uart_tb hdl
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## testbench
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## todo4user: modify working directory and hdl variables
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## version: 0.0.0
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## changelog: - 0.0.0, initial release
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## - ...
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################################################################################
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# IMPORTANT NOTICE!
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# Verilog (R) simulation flow requires Xilinx (R) ISE (R) to be installed.
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# user settings: preferred hdl and working directory
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set wd "e:/home_users/ste.fis/projects/wb4pb/trunk/sim"
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set isVHDL yes
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# working directory cannot be changed while simulation is running
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if {![string equal -nocase [pwd] $wd]} {
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quit -sim
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cd $wd
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}
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# creating library work, if not existing
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if {[glob -nocomplain -types d "work"] == {}} {
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vlib work
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}
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# compiling hdl modules and starting simulator
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if {$isVHDL} {
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vcom -check_synthesis "../rtl/picoblaze_wb_uart.vhd"
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vcom -check_synthesis "../rtl/wbm_picoblaze.vhd"
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vcom -check_synthesis "../rtl/wbs_uart.vhd"
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vcom "../rtl/uart_rx.vhd"
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vcom "../rtl/uart_tx.vhd"
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vcom "../rtl/kcuart_rx.vhd"
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vcom "../rtl/kcuart_tx.vhd"
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vcom "../rtl/bbfifo_16x8.vhd"
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vcom "../rtl/kcpsm3.vhd"
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vcom "../asm/pbwbuart.vhd"
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vcom "../sim/hdl/picoblaze_wb_uart_tb.vhd"
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vsim picoblaze_wb_uart_tb behavioral
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} else {
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vlog "../rtl/picoblaze_wb_uart.v"
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vlog "../rtl/wbm_picoblaze.v"
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vlog "../rtl/wbs_uart.v"
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vlog "../rtl/uart_rx.v"
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vlog "../rtl/uart_tx.v"
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vlog "../rtl/kcuart_rx.v"
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vlog "../rtl/kcuart_tx.v"
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vlog "../rtl/bbfifo_16x8.v"
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vlog "../rtl/kcpsm3.v"
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vlog "../asm/pbwbuart.v"
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vlog "../sim/hdl/picoblaze_wb_uart_tb.v"
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vlog "$env(XILINX)/verilog/src/glbl.v"
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vsim picoblaze_wb_uart_tb glbl
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}
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# configuring wave window
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view -undock -x 0 -y 0 -width 1024 -height 640 wave
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# adding signals of interest
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proc add_wave_sys_sig? {on_off_n} {
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if {$on_off_n} {
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add wave -divider "SYSTEM SIGNALS"
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add wave sim:/dut/rst
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add wave sim:/dut/clk
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}
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}
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proc add_wave_wb_sig? {on_off_n} {
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if {$on_off_n} {
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add wave -divider "WISHBONE SIGNALS"
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#add wave sim:/dut/wb_cyc
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add wave sim:/dut/wb_stb
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add wave sim:/dut/wb_we
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add wave -radix hex sim:/dut/wb_adr
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add wave -radix hex sim:/dut/wb_dat_m2s
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add wave -radix hex sim:/dut/wb_dat_s2m
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add wave sim:/dut/wb_ack
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}
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}
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proc add_wave_pbport_sig? {on_off_n} {
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if {$on_off_n} {
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add wave -divider "PICOBLAZE PORT SIGNALS"
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add wave -radix hex sim:/dut/pb_port_id
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add wave sim:/dut/pb_write_strobe
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add wave -radix hex sim:/dut/pb_out_port
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add wave sim:/dut/pb_read_strobe
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add wave -radix hex sim:/dut/pb_in_port
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}
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}
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proc add_wave_pbimem_sig? {on_off_n} {
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if {$on_off_n} {
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add wave -divider "PICOBLAZE INSTRUCTION MEMORY SIGNALS"
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add wave -radix hex sim:/dut/address
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add wave -radix hex sim:/dut/instruction
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}
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}
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proc add_wave_uart_sig? {on_off_n} {
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if {$on_off_n} {
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add wave -divider "UART SIGNALS"
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add wave sim:/uart_rx_si
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#add wave sim:/uart_tx_so
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add wave sim:/dut/inst_wbs_uart/en_16_x_baud
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}
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}
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# selecting active signal groups
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add_wave_sys_sig? yes
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add_wave_wb_sig? yes
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add_wave_pbport_sig? yes
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add_wave_pbimem_sig? no
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add_wave_uart_sig? yes
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# setting simulation runtime
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run 100 us
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# zooming to time area of interest
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wave zoomfull
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