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#!/usr/bin/perl
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#use POSIX;
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use Tk;
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use Time::Local;
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#
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# usage perl wishbone_gui.pl [-nogui] [wishbone.defines]
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#
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#
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# description: users manual
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#
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my $infile = "wishbone.defines";
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my $outfile = wb;
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my $a;
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my $i=0;
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my $j=0;
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# default settings
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my $syscon=syscon;
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my $intercon=intercon;
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my $target="generic";
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my $hdl=vhdl;
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my $ext=".vhd";
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my $signal_groups=0;
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my $comment="--";
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my $dat_size=32;
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my $adr_size=32;
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my $tgd_bits=0;
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my $tga_bits=2;
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my $tgc_bits=3;
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my $rename_tgc="cti";
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my $rename_tga="bte";
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my $rename_tgd="tgd";
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my $classic="000";
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my $endofburst="111";
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my $interconnect="sharedbus";
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my $mux_type="andor";
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my $optimize="speed";
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my $priority="0";
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# keep track of implementation size
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my $masters=0;
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my $slaves=0;
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my $rty_o=0;
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my $rty_i=0;
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my $err_o=0;
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my $err_i=0;
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my $tgc_o=0;
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my $tgc_i=0;
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my $tga_o=0;
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my $tga_i=0;
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# GUI FSM
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my $state='WinGlobal';
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my $next=0;
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my $back=0;
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my $amp=0;
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my $asp=0;
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my $del=0;
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my $i;
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# open input file
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#if (open(FILE,"<$file")) {
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# read in settings from infile
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sub master_init {
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$masters += 1;
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$master[$masters]{"wbm"}=$_[0];
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$master[$masters]{"dat_size"}=$dat_size;
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$master[$masters]{"adr_size"}=$adr_size;
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$master[$masters]{"type"}="rw";
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$master[$masters]{"adr_o_hi"}=31;
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$master[$masters]{"adr_o_lo"}=0;
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$master[$masters]{"lock_o"}=0;
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$master[$masters]{"err_i"}=1;
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$master[$masters]{"rty_i"}=1;
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$master[$masters]{"tga_o"}=0;
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$master[$masters]{"tgd_o"}=0;
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$master[$masters]{"tgc_o"}=0;
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$master[$masters]{"priority"}=1;
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};
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sub slave_init {
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$slaves += 1;
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$slave[$slaves]{"wbs"}=$_[0];
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$slave[$slaves]{"dat_size"}=$dat_size;
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$slave[$slaves]{"type"}="rw";
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$slave[$slaves]{"sel_i"}=1;
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$slave[$slaves]{"adr_i_hi"}=31;
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$slave[$slaves]{"adr_i_lo"}=2;
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$slave[$slaves]{"lock_i"}=0;
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$slave[$slaves]{"tgd_i"}=0;
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$slave[$slaves]{"tga_i"}=0;
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$slave[$slaves]{"tgc_i"}=0;
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$slave[$slaves]{"err_o"}=0;
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$slave[$slaves]{"rty_o"}=0;
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$slave[$slaves]{"baseadr"}="00000000";
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$slave[$slaves]{"size"}="00100000";
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$slave[$slaves]{"baseadr1"}="00000000";
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$slave[$slaves]{"size1"}="ffffffff";
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$slave[$slaves]{"baseadr2"}="00000000";
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$slave[$slaves]{"size2"}="ffffffff";
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$slave[$slaves]{"baseadr3"}="00000000";
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$slave[$slaves]{"size3"}="ffffffff";
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};
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sub read_defines {
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$priority=0;
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$masters=0;
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$slaves=0;
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open(FILE,"<$_[0]") or die "could not read from $file";
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while($a = <FILE>)
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{
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if ($a =~ /^(syscon|intercon|filename)( *)(=)( *)([a-zA-Z0-9_\/\.]+)(;?)$/) {
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if($1 eq "syscon") { $syscon = $5; }
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if($1 eq "intercon") { $intercon = $5; }
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if($1 eq "filename") { $outfile = $5; }
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}
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if ($a =~ /^(target)( *)(=)( *)(generic|xilinx|altera)(;?)$/) {
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$target = $5; };
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if ($a =~ /^(hdl)( *)(=)( *)(vhdl|verilog|perlilog);?$/) {
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$hdl = $5;
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if ($5 eq "vhdl") {
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$comment="--";
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$ext=".vhd";
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} else {
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$comment="//";
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$ext=".v";
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};
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};
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if ($a =~ /^(interconnect)( *)(=)( *)(crossbarswitch|sharedbus)(;?)$/) {
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$interconnect = $5; };
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if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($*)/) {
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$signal_groups = $5; };
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if ($a =~ /^(mux_type)( *)(=)( *)(mux|andor|tristate)(;?)$/) {
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$mux_type = $5; };
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if ($a =~ /^(optimize)( *)(=)( *)(speed|area);?$/) {
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$optimize = $5; };
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if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits)( *)(=)( *)([0-9]+)(;?)($*)/) {
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if ($1 eq "dat_size"){$dat_size = $5};
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if ($1 eq "adr_size"){$adr_size = $5};
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if ($1 eq "tgd_bits"){$tgd_bits = $5};
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if ($1 eq "tga_bits"){$tga_bits = $5};
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if ($1 eq "tgc_bits"){$tgc_bits = $5};
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};
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if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($*)/) {
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if ($3 eq "tga"){$rename_tga=$7};
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if ($3 eq "tgc"){$rename_tgc=$7};
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if ($3 eq "tgd"){$rename_tgd=$7};
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};
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# master port setup
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if ($a =~ /^(master)( *)([A-Za-z0-9_-]+)($*)/) {
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if($1 eq "master") {
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master_init($3);
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};
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$a = <FILE>;
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until ($a =~ /^(end master)($*)/) {
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if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($*)/) {
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$master[$masters]{"$2"}=$7;
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if (($2 eq "rty_i") && ($7 eq 1)) {
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$rty_i++; };
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if (($2 eq "err_i") && ($7 eq 1)) {
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$err_i++; };
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if (($2 eq "tgc_o") && ($7 eq 1)) {
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$tgc_o++; };
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if (($2 eq "tga_o") && ($7 eq 1)) {
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$tga_o++; };
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# priority for shared bus system
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if ($2 eq "priority") {
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$priority += $7; };
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}; #end if
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if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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$master[$masters]{"$2"}=$6; };
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# priority for crossbarswitch
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if ($a =~ /^( *)(priority)(_)([0-9a-zA-Z_]*)( *)(=)( *)([0-9]*)(;?)($*)/) {
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$master[$masters]{("priority_"."$4")}=$8; };
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$a = <FILE>;
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};
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};
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# slave port setup
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if ($a =~ /^(slave)( *)([A-Za-z0-9_-]+)($*)/) {
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if ($1 eq "slave") {
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slave_init($3);
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};
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$a = <FILE>;
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until ($a =~ /^(end slave)($*)/) {
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if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($*)/) {
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$slave[$slaves]{"$2"}=$7;
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if (($2 eq "rty_o") && ($7 eq 1)) {
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$rty_o++; };
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if (($2 eq "err_o") && ($7 eq 1)) {
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$err_o++; };
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if (($2 eq "tgc_i") && ($7 eq 1)) {
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$tgc_i++; };
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if (($2 eq "tga_i") && ($7 eq 1)) {
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$tga_i++; };
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}; #end if
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if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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$slave[$slaves]{"$2"}=$6; };
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$a = <FILE>;
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};
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};
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}; #end while
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close($_[0]);
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}; #end sub
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################################################################################
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# GUI
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my $mw;
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sub WinGlobalExit {
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$mw->destroy();
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};
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# global assignments
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sub WinGlobal {
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$mw = MainWindow->new;
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$mw->title ("Wishbone generator");
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$frame=$mw->Frame(-label=>"Global definitions");
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# define file
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Define file:")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$infile)->pack(-side=>'right');
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# HDL file
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "HDL file :")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$outfile)->pack(-side=>'right');
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# intercon
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "intercon :")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$intercon)->pack(-side=>'right');
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# syscon
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "syscon :")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$syscon)->pack(-side=>'right');
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# target
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Target :")->pack(-side=>'left');
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$a = $frame->Radiobutton ( -variable => \$target, -text => 'Generic', -value => 'generic')->pack(-side=>'left');
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$b = $frame->Radiobutton ( -variable => \$target, -text => 'XILINX', -value => 'xilinx')->pack(-side=>'left');
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$c = $frame->Radiobutton ( -variable => \$target, -text => 'ALTERA', -value => 'altera')->pack(-side=>'left');
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# interconnect
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Interconnection :")->pack(-side=>'left');
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$a = $frame->Radiobutton ( -variable => \$interconnect, -text => 'Shared bus', -value => 'sharedbus')->pack( -side=>'left');
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$b = $frame->Radiobutton ( -variable => \$interconnect, -text => 'Crossbar switch', -value => 'crossbarswitch' )->pack( -side=>'right');
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# mux
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Mux type :")->pack(-side=>'left');
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$a = $frame->Radiobutton ( -variable => \$mux_type, -text => 'mux', -value => 'mux')->pack( -side=>'left');
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$b = $frame->Radiobutton ( -variable => \$mux_type, -text => 'andor', -value => 'andor')->pack( -side=>'left');
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$c = $frame->Radiobutton ( -variable => \$mux_type, -text => 'tristate', -value => 'tristate' )->pack( -side=>'right');
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# hdl
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "HDL type :")->pack(-side=>'left');
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$a = $frame->Radiobutton ( -variable => \$hdl, -text => 'VHDL', -value => 'vhdl')->pack(-side=>'left');
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$b = $frame->Radiobutton ( -variable => \$hdl, -text => 'Verilog', -value => 'verilog')->pack(-side=>'left');
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$c = $frame->Radiobutton ( -variable => \$hdl, -text => 'Perlilog', -value => 'perlilog')->pack(-side=>'left');
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# signalgroups
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Signal groups :")->pack(-side=>'left');
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$a = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'No', -value => 0)->pack( -side=>'left');
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$b = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'Yes', -value => 1 )->pack( -side=>'right');
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# dat size
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
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|
|
$frame->Entry(-textvariable => \$dat_size)->pack(-side=>'right');
|
| 293 |
|
|
# adr size
|
| 294 |
|
|
$frame=$mw->Frame();
|
| 295 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 296 |
|
|
$frame->Label(-text => "Adr bus size :")->pack(-side=>'left');
|
| 297 |
|
|
$frame->Entry(-textvariable => \$adr_size)->pack(-side=>'right');
|
| 298 |
|
|
# tga
|
| 299 |
|
|
$frame=$mw->Frame();
|
| 300 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 301 |
|
|
$frame->Label(-text => "tga bits :")->pack(-side=>'left');
|
| 302 |
|
|
$frame->Entry(-textvariable => \$tga_bits)->pack(-side=>'right');
|
| 303 |
|
|
$frame=$mw->Frame();
|
| 304 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 305 |
|
|
$frame->Label(-text => "tga rename :")->pack(-side=>'left');
|
| 306 |
|
|
$frame->Entry(-textvariable => \$rename_tga)->pack(-side=>'right');
|
| 307 |
|
|
# tgc
|
| 308 |
|
|
$frame=$mw->Frame();
|
| 309 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 310 |
|
|
$frame->Label(-text => "tgc bits :")->pack(-side=>'left');
|
| 311 |
|
|
$frame->Entry(-textvariable => \$tgc_bits)->pack(-side=>'right');
|
| 312 |
|
|
$frame=$mw->Frame();
|
| 313 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 314 |
|
|
$frame->Label(-text => "tgc rename :")->pack(-side=>'left');
|
| 315 |
|
|
$frame->Entry(-textvariable => \$rename_tgc)->pack(-side=>'right');
|
| 316 |
|
|
$frame=$mw->Frame();
|
| 317 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 318 |
|
|
$frame->Label(-text => "classic :")->pack(-side=>'left');
|
| 319 |
|
|
$frame->Entry(-textvariable => \$classic)->pack(-side=>'right');
|
| 320 |
|
|
$frame=$mw->Frame();
|
| 321 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 322 |
|
|
$frame->Label(-text => "end of burst :")->pack(-side=>'left');
|
| 323 |
|
|
$frame->Entry(-textvariable => \$endofburst)->pack(-side=>'right');
|
| 324 |
|
|
# tgd
|
| 325 |
|
|
$frame=$mw->Frame();
|
| 326 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 327 |
|
|
$frame->Label(-text => "tgd bits :")->pack(-side=>'left');
|
| 328 |
|
|
$frame->Entry(-textvariable => \$tgd_bits)->pack(-side=>'right');
|
| 329 |
|
|
$frame=$mw->Frame();
|
| 330 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 331 |
|
|
$frame->Label(-text => "tgd rename :")->pack(-side=>'left');
|
| 332 |
|
|
$frame->Entry(-textvariable => \$rename_tgd)->pack(-side=>'right');
|
| 333 |
|
|
# exit
|
| 334 |
|
|
$frame=$mw->Frame(-label=>"\n");
|
| 335 |
|
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
| 336 |
|
|
$frame->Button(-text => "add master port", -command =>sub {WinGlobalExit(); $amp=1;})->pack (-side => 'left');
|
| 337 |
|
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $asp=1;})->pack (-side => 'left');
|
| 338 |
|
|
if (($masters > 0) && ($slaves > 0)) {
|
| 339 |
|
|
$frame->Button(-text => "set priority", -command =>sub {WinGlobalExit();})->pack (-side => 'left');
|
| 340 |
|
|
};
|
| 341 |
|
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack (-side => 'right');
|
| 342 |
|
|
MainLoop;
|
| 343 |
|
|
};
|
| 344 |
|
|
|
| 345 |
|
|
# add master port
|
| 346 |
|
|
sub WinAddMaster {
|
| 347 |
|
|
master_init("wbm". ($masters+1));
|
| 348 |
|
|
$mw = MainWindow->new;
|
| 349 |
|
|
$mw->title ("Wishbone generator");
|
| 350 |
|
|
$frame=$mw->Frame(-label=>"Add wishbone master port");
|
| 351 |
|
|
# port name
|
| 352 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 353 |
|
|
$frame->Label(-text => "Master port name:")->pack(-side=>'left');
|
| 354 |
|
|
$frame->Entry(-textvariable => \$master[$masters]{"wbm"})->pack(-side=>'right');
|
| 355 |
|
|
# exit
|
| 356 |
|
|
$frame=$mw->Frame(-label=>"\n");
|
| 357 |
|
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
| 358 |
|
|
$frame->Button(-text => "add master port", -command =>sub {WinGlobalExit(); $amp=1;})->pack ( -side => 'left');
|
| 359 |
|
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
| 360 |
|
|
MainLoop;
|
| 361 |
|
|
};
|
| 362 |
|
|
|
| 363 |
|
|
sub WinMaster {
|
| 364 |
|
|
$mw = MainWindow->new;
|
| 365 |
|
|
$mw->title ("Wishbone generator");
|
| 366 |
|
|
$frame=$mw->Frame(-label=>"Master port");
|
| 367 |
|
|
# Master port
|
| 368 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 369 |
|
|
$frame->Label(-text => "Master port :")->pack(-side=>'left');
|
| 370 |
|
|
$frame->Entry(-textvariable => \$master[$i]{"wbm"})->pack(-side=>'right');
|
| 371 |
|
|
# dat_size
|
| 372 |
|
|
$frame=$mw->Frame();
|
| 373 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 374 |
|
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
| 375 |
|
|
$frame->Entry(-textvariable => \$master[$i]{"dat_size"})->pack(-side=>'right');
|
| 376 |
|
|
# adr size
|
| 377 |
|
|
$frame=$mw->Frame();
|
| 378 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 379 |
|
|
$frame->Label(-text => "Adr bus size :")->pack(-side=>'left');
|
| 380 |
|
|
$frame->Entry(-textvariable => \$master[$i]{"adr_size"})->pack(-side=>'right');
|
| 381 |
|
|
# type
|
| 382 |
|
|
$frame=$mw->Frame();
|
| 383 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 384 |
|
|
$frame->Label(-text => "Master type :")->pack(-side=>'left');
|
| 385 |
|
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Read/Write', -value => 'rw')->pack(-side=>'left');
|
| 386 |
|
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Read only', -value => 'ro')->pack(-side=>'left');
|
| 387 |
|
|
$c = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Write only', -value => 'wo')->pack(-side=>'left');
|
| 388 |
|
|
# err_i
|
| 389 |
|
|
$frame=$mw->Frame();
|
| 390 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 391 |
|
|
$frame->Label(-text => "err_i :")->pack(-side=>'left');
|
| 392 |
|
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"err_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 393 |
|
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"err_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 394 |
|
|
# rty_i
|
| 395 |
|
|
$frame=$mw->Frame();
|
| 396 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 397 |
|
|
$frame->Label(-text => "rty_i :")->pack(-side=>'left');
|
| 398 |
|
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"rty_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 399 |
|
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"rty_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 400 |
|
|
# lock_o
|
| 401 |
|
|
$frame=$mw->Frame();
|
| 402 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 403 |
|
|
$frame->Label(-text => "lock_o :")->pack(-side=>'left');
|
| 404 |
|
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"lock_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 405 |
|
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"lock_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 406 |
|
|
# tga_o
|
| 407 |
|
|
$frame=$mw->Frame();
|
| 408 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 409 |
|
|
$frame->Label(-text => "tga_o :")->pack(-side=>'left');
|
| 410 |
|
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tga_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 411 |
|
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tga_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 412 |
|
|
# tgc_o
|
| 413 |
|
|
$frame=$mw->Frame();
|
| 414 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 415 |
|
|
$frame->Label(-text => "tgc_o :")->pack(-side=>'left');
|
| 416 |
|
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tgc_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 417 |
|
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tgc_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 418 |
|
|
# tgd_o
|
| 419 |
|
|
$frame=$mw->Frame();
|
| 420 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 421 |
|
|
$frame->Label(-text => "tgd_o :")->pack(-side=>'left');
|
| 422 |
|
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tgd_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 423 |
|
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tgd_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 424 |
|
|
# exit
|
| 425 |
|
|
$frame=$mw->Frame(-label=>"\n");
|
| 426 |
|
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
| 427 |
|
|
if ($i == $masters) {
|
| 428 |
|
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $am=1;})->pack (-side => 'left');
|
| 429 |
|
|
};
|
| 430 |
|
|
$frame->Button(-text => "delete", -command =>sub {WinGlobalExit(); $del=1;})->pack (-side => 'left');
|
| 431 |
|
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack (-side => 'left');
|
| 432 |
|
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack (-side => 'left');
|
| 433 |
|
|
MainLoop;
|
| 434 |
|
|
};
|
| 435 |
|
|
|
| 436 |
|
|
# add slave port
|
| 437 |
|
|
sub WinAddSlave {
|
| 438 |
|
|
slave_init("wbs" . ($slaves+1));
|
| 439 |
|
|
$mw = MainWindow->new;
|
| 440 |
|
|
$mw->title ("Wishbone generator");
|
| 441 |
|
|
$frame=$mw->Frame(-label=>"Add wishbone slave port");
|
| 442 |
|
|
# port name
|
| 443 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 444 |
|
|
$frame->Label(-text => "Slave port name:")->pack(-side=>'left');
|
| 445 |
|
|
$frame->Entry(-textvariable => \$slave[$slaves]{"wbs"})->pack(-side=>'right');
|
| 446 |
|
|
# exit
|
| 447 |
|
|
$frame=$mw->Frame(-label=>"\n");
|
| 448 |
|
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
| 449 |
|
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $asp=1;})->pack ( -side => 'left');
|
| 450 |
|
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
| 451 |
|
|
MainLoop;
|
| 452 |
|
|
};
|
| 453 |
|
|
|
| 454 |
|
|
# slave port
|
| 455 |
|
|
sub WinSlave {
|
| 456 |
|
|
$mw = MainWindow->new;
|
| 457 |
|
|
$mw->title ("Wishbone generator");
|
| 458 |
|
|
$frame=$mw->Frame(-label=>"Slave port");
|
| 459 |
|
|
# Slave port
|
| 460 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 461 |
|
|
$frame->Label(-text => "Slave port :")->pack(-side=>'left');
|
| 462 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"wbs"})->pack(-side=>'right');
|
| 463 |
|
|
# dat_size
|
| 464 |
|
|
$frame=$mw->Frame();
|
| 465 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 466 |
|
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
| 467 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"dat_size"})->pack(-side=>'right');
|
| 468 |
|
|
# adr
|
| 469 |
|
|
$frame=$mw->Frame();
|
| 470 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 471 |
|
|
$frame->Label(-text => "adr hi :")->pack(-side=>'left');
|
| 472 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"adr_i_hi"})->pack(-side=>'left');
|
| 473 |
|
|
$frame=$mw->Frame();
|
| 474 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 475 |
|
|
$frame->Label(-text => "adr lo :")->pack(-side=>'left');
|
| 476 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"adr_i_lo"})->pack(-side=>'right');
|
| 477 |
|
|
# type
|
| 478 |
|
|
$frame=$mw->Frame();
|
| 479 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 480 |
|
|
$frame->Label(-text => "Slave type :")->pack(-side=>'left');
|
| 481 |
|
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Read/Write', -value => 'rw')->pack(-side=>'left');
|
| 482 |
|
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Read only', -value => 'ro')->pack(-side=>'left');
|
| 483 |
|
|
$c = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Write only', -value => 'wo')->pack(-side=>'left');
|
| 484 |
|
|
# lock_i
|
| 485 |
|
|
$frame=$mw->Frame();
|
| 486 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 487 |
|
|
$frame->Label(-text => "lock_i :")->pack(-side=>'left');
|
| 488 |
|
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 489 |
|
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 490 |
|
|
# tga_i
|
| 491 |
|
|
$frame=$mw->Frame();
|
| 492 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 493 |
|
|
$frame->Label(-text => "tga_i :")->pack(-side=>'left');
|
| 494 |
|
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tga_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 495 |
|
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tga_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 496 |
|
|
# tgc_i
|
| 497 |
|
|
$frame=$mw->Frame();
|
| 498 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 499 |
|
|
$frame->Label(-text => "tgc_i :")->pack(-side=>'left');
|
| 500 |
|
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tgc_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 501 |
|
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tgc_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 502 |
|
|
# tgd_i
|
| 503 |
|
|
$frame=$mw->Frame();
|
| 504 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 505 |
|
|
$frame->Label(-text => "tgd_i :")->pack(-side=>'left');
|
| 506 |
|
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tgd_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 507 |
|
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tgd_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 508 |
|
|
# err_o
|
| 509 |
|
|
$frame=$mw->Frame();
|
| 510 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 511 |
|
|
$frame->Label(-text => "err_o :")->pack(-side=>'left');
|
| 512 |
|
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"err_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 513 |
|
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"err_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 514 |
|
|
# rty_o
|
| 515 |
|
|
$frame=$mw->Frame();
|
| 516 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 517 |
|
|
$frame->Label(-text => "rty_o :")->pack(-side=>'left');
|
| 518 |
|
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"rty_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
| 519 |
|
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"rty_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
| 520 |
|
|
# ss
|
| 521 |
|
|
$frame=$mw->Frame();
|
| 522 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 523 |
|
|
$frame->Label(-text => "Base_adr :")->pack(-side=>'left');
|
| 524 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr"})->pack(-side=>'right');
|
| 525 |
|
|
$frame=$mw->Frame();
|
| 526 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 527 |
|
|
$frame->Label(-text => "Size :")->pack(-side=>'left');
|
| 528 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"size"})->pack(-side=>'right');
|
| 529 |
|
|
$frame=$mw->Frame();
|
| 530 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 531 |
|
|
$frame->Label(-text => "Base_adr1 :")->pack(-side=>'left');
|
| 532 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr1"})->pack(-side=>'right');
|
| 533 |
|
|
$frame=$mw->Frame();
|
| 534 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 535 |
|
|
$frame->Label(-text => "Size1 :")->pack(-side=>'left');
|
| 536 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"size1"})->pack(-side=>'right');
|
| 537 |
|
|
$frame=$mw->Frame();
|
| 538 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 539 |
|
|
$frame->Label(-text => "Base_adr2 :")->pack(-side=>'left');
|
| 540 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr2"})->pack(-side=>'right');
|
| 541 |
|
|
$frame=$mw->Frame();
|
| 542 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 543 |
|
|
$frame->Label(-text => "Size2 :")->pack(-side=>'left');
|
| 544 |
|
|
$frame->Entry(-textvariable => \$slave[$i]{"size2"})->pack(-side=>'right');
|
| 545 |
|
|
|
| 546 |
|
|
# exit
|
| 547 |
|
|
$frame=$mw->Frame(-label=>"\n");
|
| 548 |
|
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
| 549 |
|
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
| 550 |
|
|
$frame->Button(-text => "delete", -command =>sub {WinGlobalExit(); $del=1;})->pack ( -side => 'left');
|
| 551 |
|
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
| 552 |
|
|
MainLoop;
|
| 553 |
|
|
};
|
| 554 |
|
|
|
| 555 |
|
|
# Prio shared bus
|
| 556 |
|
|
sub WinPrioshb {
|
| 557 |
|
|
$mw = MainWindow->new;
|
| 558 |
|
|
$mw->title ("Wishbone generator");
|
| 559 |
|
|
$frame=$mw->Frame(-label=>"Priority for shared bus system")->pack();
|
| 560 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 561 |
|
|
$frame=$mw->Frame();
|
| 562 |
|
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
| 563 |
|
|
$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
|
| 564 |
|
|
$frame->Entry(-textvariable => \$master[$i]{"priority"})->pack(-side=>'right');
|
| 565 |
|
|
};
|
| 566 |
|
|
# exit
|
| 567 |
|
|
$frame=$mw->Frame(-label=>"\n");
|
| 568 |
|
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
| 569 |
|
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
| 570 |
|
|
$frame->Button(-text => "generate", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
| 571 |
|
|
MainLoop;
|
| 572 |
|
|
};
|
| 573 |
|
|
|
| 574 |
|
|
# Prio cross bar switch
|
| 575 |
|
|
sub WinPriocbs {
|
| 576 |
|
|
my $tmp="";
|
| 577 |
|
|
$mw = MainWindow->new;
|
| 578 |
|
|
$mw->title ("Wishbone generator");
|
| 579 |
|
|
$frame=$mw->Frame(-label=>"Priority for crossbar switch bus system")->pack();
|
| 580 |
|
|
$frame=$mw->Frame();
|
| 581 |
|
|
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
|
| 582 |
|
|
$frame->Entry(-textvariable => \$tmp)->pack(-side=>'left');
|
| 583 |
|
|
for ($j=1; $j le $slaves; $j++) {
|
| 584 |
|
|
$frame->Entry(-textvariable => \$slave[$j]{"wbs"})->pack(-side=>'left');
|
| 585 |
|
|
};
|
| 586 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 587 |
|
|
$frame=$mw->Frame();
|
| 588 |
|
|
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
|
| 589 |
|
|
#$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
|
| 590 |
|
|
$frame->Entry(-textvariable => \$master[$i]{"wbm"})->pack(-side=>'left');
|
| 591 |
|
|
for ($j=1; $j le $slaves; $j++) {
|
| 592 |
|
|
#$frame->Label(-text => $master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
|
| 593 |
|
|
$frame->Entry(-textvariable => \$master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
|
| 594 |
|
|
};
|
| 595 |
|
|
};
|
| 596 |
|
|
# exit
|
| 597 |
|
|
$frame=$mw->Frame(-label=>"\n");
|
| 598 |
|
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
| 599 |
|
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
| 600 |
|
|
$frame->Button(-text => "generate", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
| 601 |
|
|
MainLoop;
|
| 602 |
|
|
};
|
| 603 |
|
|
|
| 604 |
|
|
# delete wishbone master
|
| 605 |
|
|
sub wbm_del {
|
| 606 |
|
|
my $i;
|
| 607 |
|
|
if ($_[0] != $masters) {
|
| 608 |
|
|
for ($i=$_[0]; $i lt $masters; $i++) {
|
| 609 |
|
|
$master[$i]=$master[$i+1];
|
| 610 |
|
|
};
|
| 611 |
|
|
};
|
| 612 |
|
|
$masters--;
|
| 613 |
|
|
};
|
| 614 |
|
|
|
| 615 |
|
|
# delete wishbone slave
|
| 616 |
|
|
sub wbs_del {
|
| 617 |
|
|
my $i;
|
| 618 |
|
|
if ($_[0] != $slaves) {
|
| 619 |
|
|
for ($i=$_[0]; $i lt $slaves; $i++) {
|
| 620 |
|
|
$slave[$i]=$slave[$i+1];
|
| 621 |
|
|
};
|
| 622 |
|
|
};
|
| 623 |
|
|
$slaves--;
|
| 624 |
|
|
};
|
| 625 |
|
|
|
| 626 |
|
|
# GUI FSM
|
| 627 |
|
|
sub gui_fsm {
|
| 628 |
|
|
$i=1;
|
| 629 |
|
|
until ($state eq "bye") {
|
| 630 |
|
|
$amp=0; $asp=0; $back=0; $next=0; $del=0;
|
| 631 |
|
|
if ($state eq 'WinGlobal') {
|
| 632 |
|
|
WinGlobal;
|
| 633 |
|
|
if ($amp == 1) {
|
| 634 |
|
|
$state='WinAddMaster';
|
| 635 |
|
|
} elsif ($asp == 1) {
|
| 636 |
|
|
$state='WinAddSlave';
|
| 637 |
|
|
} elsif ($next == 1) {
|
| 638 |
|
|
$i=1;
|
| 639 |
|
|
if ($masters == 0) {
|
| 640 |
|
|
$state='WinAddMaster';
|
| 641 |
|
|
} else {
|
| 642 |
|
|
$state='WinMaster';
|
| 643 |
|
|
};
|
| 644 |
|
|
} else {
|
| 645 |
|
|
$state='WinPrio';
|
| 646 |
|
|
};
|
| 647 |
|
|
} elsif ($state eq 'WinAddMaster') {
|
| 648 |
|
|
WinAddMaster;
|
| 649 |
|
|
if ($next == 1) {
|
| 650 |
|
|
$i=1;
|
| 651 |
|
|
$state='WinMaster';
|
| 652 |
|
|
};
|
| 653 |
|
|
} elsif ($state eq 'WinMaster') {
|
| 654 |
|
|
WinMaster;
|
| 655 |
|
|
if ($del == 1) {
|
| 656 |
|
|
wbm_del($i);
|
| 657 |
|
|
$state='WinGlobal';
|
| 658 |
|
|
$i=1;
|
| 659 |
|
|
} elsif ($asp == 1) {
|
| 660 |
|
|
$state='WinAddSlave';
|
| 661 |
|
|
} elsif ($next == 1) {
|
| 662 |
|
|
if ($i == $masters) {
|
| 663 |
|
|
$i=1;
|
| 664 |
|
|
if ($slaves == 0) {
|
| 665 |
|
|
$state='WinAddSlave';
|
| 666 |
|
|
} else {
|
| 667 |
|
|
$state='WinSlave';
|
| 668 |
|
|
};
|
| 669 |
|
|
} else {
|
| 670 |
|
|
$i++
|
| 671 |
|
|
};
|
| 672 |
|
|
} else {
|
| 673 |
|
|
if ($i == 1) {
|
| 674 |
|
|
$state='WinGlobal';
|
| 675 |
|
|
} else {
|
| 676 |
|
|
$i--;
|
| 677 |
|
|
}
|
| 678 |
|
|
};
|
| 679 |
|
|
} elsif ($state eq 'WinAddSlave') {
|
| 680 |
|
|
WinAddSlave;
|
| 681 |
|
|
if ($next == 1) {
|
| 682 |
|
|
$i=1;
|
| 683 |
|
|
$state='WinSlave';
|
| 684 |
|
|
};
|
| 685 |
|
|
} elsif ($state eq 'WinSlave') {
|
| 686 |
|
|
WinSlave;
|
| 687 |
|
|
if ($del == 1) {
|
| 688 |
|
|
wbs_del($i);
|
| 689 |
|
|
$i=1;
|
| 690 |
|
|
$state='WinGlobal';
|
| 691 |
|
|
} elsif ($next == 1) {
|
| 692 |
|
|
if ($i eq $slaves) {
|
| 693 |
|
|
$state='WinPrio';
|
| 694 |
|
|
} else {
|
| 695 |
|
|
$i++
|
| 696 |
|
|
};
|
| 697 |
|
|
} else {
|
| 698 |
|
|
if ($i == 1) {
|
| 699 |
|
|
$state='WinGlobal';
|
| 700 |
|
|
} else {
|
| 701 |
|
|
$i--;
|
| 702 |
|
|
}
|
| 703 |
|
|
};
|
| 704 |
|
|
} elsif ($state eq 'WinPrio') {
|
| 705 |
|
|
if ($interconnect eq "sharedbus") {
|
| 706 |
|
|
WinPrioshb;
|
| 707 |
|
|
} else {
|
| 708 |
|
|
WinPriocbs;
|
| 709 |
|
|
};
|
| 710 |
|
|
if ($next == 1) {
|
| 711 |
|
|
$state='bye';
|
| 712 |
|
|
} else {
|
| 713 |
|
|
$state='WinGlobal';
|
| 714 |
|
|
};
|
| 715 |
|
|
};
|
| 716 |
|
|
};
|
| 717 |
|
|
};
|
| 718 |
|
|
|
| 719 |
|
|
sub generate_defines {
|
| 720 |
|
|
open(OUTFILE,"> $_[0]") or die "could not open $infile for writing";
|
| 721 |
|
|
printf OUTFILE "# Generated by PERL program wishbone.pl.\n";
|
| 722 |
|
|
printf OUTFILE "# File used as input for wishbone arbiter generation\n";
|
| 723 |
|
|
$tmp=localtime(time);
|
| 724 |
|
|
printf OUTFILE "# Generated %s\n\n",$tmp;
|
| 725 |
|
|
printf OUTFILE "filename=%s\n",$outfile;
|
| 726 |
|
|
printf OUTFILE "intercon=%s\n",$intercon;
|
| 727 |
|
|
printf OUTFILE "syscon=%s\n",$syscon;
|
| 728 |
|
|
printf OUTFILE "target=%s\n",$target;
|
| 729 |
|
|
printf OUTFILE "hdl=%s\n",$hdl;
|
| 730 |
|
|
printf OUTFILE "signal_groups=%s\n",$signal_groups;
|
| 731 |
|
|
printf OUTFILE "tga_bits=%s\n",$tga_bits;
|
| 732 |
|
|
printf OUTFILE "tgc_bits=%s\n",$tgc_bits;
|
| 733 |
|
|
printf OUTFILE "tgd_bits=%s\n",$tgd_bits;
|
| 734 |
|
|
printf OUTFILE "rename_tga=%s\n",$rename_tga;
|
| 735 |
|
|
printf OUTFILE "rename_tgc=%s\n",$rename_tgc;
|
| 736 |
|
|
printf OUTFILE "rename_tgd=%s\n",$rename_tgd;
|
| 737 |
|
|
printf OUTFILE "classic=%s\n",$classic;
|
| 738 |
|
|
printf OUTFILE "endofburst=%s\n",$endofburst;
|
| 739 |
|
|
printf OUTFILE "dat_size=%s\n",$dat_size;
|
| 740 |
|
|
printf OUTFILE "adr_size=%s\n",$adr_size;
|
| 741 |
|
|
printf OUTFILE "mux_type=%s\n",$mux_type;
|
| 742 |
|
|
printf OUTFILE "interconnect=%s\n",$interconnect;
|
| 743 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 744 |
|
|
printf OUTFILE "\nmaster %s\n",$master[$i]{"wbm"};
|
| 745 |
|
|
printf OUTFILE " type=%s\n",$master[$i]{"type"};
|
| 746 |
|
|
printf OUTFILE " lock_o=%s\n",$master[$i]{"lock_o"};
|
| 747 |
|
|
printf OUTFILE " tga_o=%s\n",$master[$i]{"tga_o"};
|
| 748 |
|
|
printf OUTFILE " tgc_o=%s\n",$master[$i]{"tgc_o"};
|
| 749 |
|
|
printf OUTFILE " tgd_o=%s\n",$master[$i]{"tgd_o"};
|
| 750 |
|
|
printf OUTFILE " err_i=%s\n",$master[$i]{"err_i"};
|
| 751 |
|
|
printf OUTFILE " rty_i=%s\n",$master[$i]{"rty_i"};
|
| 752 |
13 |
unneback |
if ($interconnect eq "sharedbus") {
|
| 753 |
2 |
unneback |
printf OUTFILE " priority=%s\n",$master[$i]{"priority"};
|
| 754 |
|
|
} else {
|
| 755 |
|
|
for ($j=1; $j le $slaves; $j++) {
|
| 756 |
|
|
printf OUTFILE " priority_%s=%s\n",$slave[$j]{"wbs"},$master[$i]{"priority_".($slave[$j]{"wbs"})};
|
| 757 |
|
|
};
|
| 758 |
|
|
};
|
| 759 |
|
|
printf OUTFILE "end master %s\n",$master[$i]{"wbm"};
|
| 760 |
|
|
};
|
| 761 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 762 |
|
|
printf OUTFILE "\nslave %s\n",$slave[$i]{"wbs"};
|
| 763 |
|
|
printf OUTFILE " type=%s\n",$slave[$i]{"type"};
|
| 764 |
|
|
printf OUTFILE " adr_i_hi=%s\n",$slave[$i]{"adr_i_hi"};
|
| 765 |
|
|
printf OUTFILE " adr_i_lo=%s\n",$slave[$i]{"adr_i_lo"};
|
| 766 |
|
|
printf OUTFILE " tga_i=%s\n",$slave[$i]{"tga_i"};
|
| 767 |
|
|
printf OUTFILE " tgc_i=%s\n",$slave[$i]{"tgc_i"};
|
| 768 |
|
|
printf OUTFILE " tgd_i=%s\n",$slave[$i]{"tgd_i"};
|
| 769 |
|
|
printf OUTFILE " lock_i=%s\n",$slave[$i]{"lock_i"};
|
| 770 |
|
|
printf OUTFILE " err_o=%s\n",$slave[$i]{"err_o"};
|
| 771 |
|
|
printf OUTFILE " rty_o=%s\n",$slave[$i]{"rty_o"};
|
| 772 |
|
|
printf OUTFILE " baseadr=0x%s\n",$slave[$i]{"baseadr"};
|
| 773 |
|
|
printf OUTFILE " size=0x%s\n",$slave[$i]{"size"};
|
| 774 |
|
|
printf OUTFILE " baseadr1=0x%s\n",$slave[$i]{"baseadr1"};
|
| 775 |
|
|
printf OUTFILE " size1=0x%s\n",$slave[$i]{"size1"};
|
| 776 |
|
|
printf OUTFILE " baseadr2=0x%s\n",$slave[$i]{"baseadr2"};
|
| 777 |
|
|
printf OUTFILE " size2=0x%s\n",$slave[$i]{"size2"};
|
| 778 |
|
|
printf OUTFILE "end slave %s\n",$slave[$i]{"wbs"};
|
| 779 |
|
|
};
|
| 780 |
|
|
close(OUTFILE);
|
| 781 |
|
|
};
|
| 782 |
|
|
|
| 783 |
|
|
# print header
|
| 784 |
|
|
sub gen_header {
|
| 785 |
|
|
printf OUTFILE "%s Generated by PERL program wishbone.pl. Do not edit this file.\n%s\n",$comment,$comment;
|
| 786 |
|
|
printf OUTFILE "%s For defines see %s\n%s\n",$comment,$infile,$comment;
|
| 787 |
|
|
$tmp=localtime(time);
|
| 788 |
|
|
printf OUTFILE "%s Generated %s\n%s\n",$comment,$tmp,$comment;
|
| 789 |
|
|
printf OUTFILE "%s Wishbone masters:\n",$comment;
|
| 790 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 791 |
|
|
printf OUTFILE "%s %s\n",$comment,$master[$i]{"wbm"}; };
|
| 792 |
|
|
printf OUTFILE "%s\n%s Wishbone slaves:\n",$comment,$comment;
|
| 793 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 794 |
|
|
printf OUTFILE "%s %s\n",$comment,$slave[$i]{"wbs"};
|
| 795 |
|
|
if ($slave[$i]{"size"} ne ffffffff) {
|
| 796 |
|
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr"},$slave[$i]{"size"}};
|
| 797 |
|
|
if ($slave[$i]{"size1"} ne ffffffff) {
|
| 798 |
|
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr1"},$slave[$i]{"size1"}};
|
| 799 |
|
|
if ($slave[$i]{"size2"} ne ffffffff) {
|
| 800 |
|
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr2"},$slave[$i]{"size2"}};
|
| 801 |
|
|
if ($slave[$i]{"size3"} ne ffffffff) {
|
| 802 |
|
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr3"},$slave[$i]{"size3"}};
|
| 803 |
|
|
};
|
| 804 |
|
|
};
|
| 805 |
|
|
|
| 806 |
|
|
sub gen_vhdl_package {
|
| 807 |
|
|
printf OUTFILE "-----------------------------------------------------------------------------------------\n";
|
| 808 |
|
|
printf OUTFILE "library IEEE;\nuse IEEE.std_logic_1164.all;\n\n";
|
| 809 |
|
|
printf OUTFILE "package %s_package is\n\n",$intercon;
|
| 810 |
|
|
|
| 811 |
|
|
# records ?
|
| 812 |
|
|
if ($signal_groups eq 1) {
|
| 813 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 814 |
|
|
# input record
|
| 815 |
|
|
printf OUTFILE "type %s_wbm_i_type is record\n",$master[$i]{"wbm"};
|
| 816 |
|
|
if ($master[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;};
|
| 817 |
|
|
if ($master[$i]{"err_i"} eq 1) { printf OUTFILE " err_i : std_logic;\n";};
|
| 818 |
|
|
if ($master[$i]{"rty_i"} eq 1) { printf OUTFILE " rty_i : std_logic;\n";};
|
| 819 |
|
|
printf OUTFILE " ack_i : std_logic;\n";
|
| 820 |
|
|
printf OUTFILE "end record;\n";
|
| 821 |
|
|
# output record
|
| 822 |
|
|
printf OUTFILE "type %s_wbm_o_type is record\n",$master[$i]{"wbm"};
|
| 823 |
|
|
if ($master[$i]{"type"} =~ /(wo|rw)/) {
|
| 824 |
|
|
printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;
|
| 825 |
|
|
printf OUTFILE " we_o : std_logic;\n"; };
|
| 826 |
|
|
if ($dat_size eq 8) {
|
| 827 |
|
|
printf OUTFILE " sel_o : std_logic;\n";
|
| 828 |
|
|
} else {
|
| 829 |
|
|
printf OUTFILE " sel_o : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
|
| 830 |
|
|
printf OUTFILE " adr_o : std_logic_vector(%s downto 0);\n",$adr_size-1;
|
| 831 |
|
|
if ($master[$i]{"lock_o"} eq 1) { printf OUTFILE " lock_o : std_logic;\n";};
|
| 832 |
|
|
if ($master[$i]{"tga_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tga, $tga_bits-1;};
|
| 833 |
|
|
if ($master[$i]{"tgc_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tgc, $tgc_bits-1;};
|
| 834 |
|
|
printf OUTFILE " cyc_o : std_logic;\n";
|
| 835 |
|
|
printf OUTFILE " stb_o : std_logic;\n";
|
| 836 |
|
|
printf OUTFILE "end record;\n\n";
|
| 837 |
|
|
}; #end for
|
| 838 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 839 |
|
|
# input record
|
| 840 |
|
|
printf OUTFILE "type %s_wbs_i_type is record\n",$slave[$i]{"wbs"};
|
| 841 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 842 |
4 |
unneback |
printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1;
|
| 843 |
2 |
unneback |
printf OUTFILE " we_i : std_logic;\n"; };
|
| 844 |
|
|
if ($dat_size eq 8) {
|
| 845 |
|
|
printf OUTFILE " sel_i : std_logic;\n";
|
| 846 |
|
|
} else {
|
| 847 |
|
|
printf OUTFILE " sel_i : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
|
| 848 |
|
|
if ($slave[$i]{"adr_i_hi"} gt 0) { printf OUTFILE " adr_i : std_logic_vector(%s downto %s);\n",$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};};
|
| 849 |
|
|
if ($slave[$i]{"tga_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tga,$tga_bits-1; };
|
| 850 |
|
|
if ($slave[$i]{"tgc_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tgc,$tgc_bits-1; };
|
| 851 |
|
|
printf OUTFILE " cyc_i : std_logic;\n";
|
| 852 |
|
|
printf OUTFILE " stb_i : std_logic;\n";
|
| 853 |
|
|
printf OUTFILE "end record;\n";
|
| 854 |
|
|
# output record
|
| 855 |
|
|
printf OUTFILE "type %s_wbs_o_type is record\n",$slave[$i]{"wbs"};
|
| 856 |
4 |
unneback |
if ($slave[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1 };
|
| 857 |
2 |
unneback |
if ($slave[$i]{"rty_o"} eq 1) { printf OUTFILE " rty_o : std_logic;\n" };
|
| 858 |
|
|
if ($slave[$i]{"err_o"} eq 1) { printf OUTFILE " err_o : std_logic;\n" };
|
| 859 |
|
|
printf OUTFILE " ack_o : std_logic;\n";
|
| 860 |
|
|
printf OUTFILE "end record;\n";
|
| 861 |
|
|
}; #end for
|
| 862 |
|
|
}; #end if signal groups
|
| 863 |
|
|
|
| 864 |
|
|
# overload of "and"
|
| 865 |
|
|
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector;\n";
|
| 866 |
|
|
printf OUTFILE "end %s_package;\n",$intercon;
|
| 867 |
|
|
printf OUTFILE "package body %s_package is\n",$intercon;
|
| 868 |
|
|
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector is\n";
|
| 869 |
|
|
printf OUTFILE " variable result : std_logic_vector(l'range);\n";
|
| 870 |
|
|
printf OUTFILE "begin -- \"and\"\n for i in l'range loop\n result(i) := l(i) and r;\nend loop; -- i\nreturn result;\nend \"and\";\n";
|
| 871 |
|
|
printf OUTFILE "end %s_package;\n",$intercon;
|
| 872 |
|
|
};
|
| 873 |
|
|
|
| 874 |
|
|
sub gen_trafic_ctrl {
|
| 875 |
|
|
if ($hdl eq "vhdl") {
|
| 876 |
|
|
if ($target eq "xilinx") {
|
| 877 |
|
|
print OUTFILE <<EOP;
|
| 878 |
|
|
|
| 879 |
|
|
library IEEE;
|
| 880 |
|
|
use IEEE.std_logic_1164.all;
|
| 881 |
|
|
|
| 882 |
|
|
entity trafic_supervision is
|
| 883 |
|
|
|
| 884 |
|
|
generic (
|
| 885 |
10 |
unneback |
priority : integer := 1;
|
| 886 |
|
|
tot_priority : integer := 2);
|
| 887 |
2 |
unneback |
|
| 888 |
|
|
port (
|
| 889 |
|
|
bg : in std_logic; -- bus grant
|
| 890 |
|
|
ce : in std_logic; -- clock enable
|
| 891 |
|
|
trafic_limit : out std_logic;
|
| 892 |
|
|
clk : in std_logic;
|
| 893 |
|
|
reset : in std_logic);
|
| 894 |
|
|
|
| 895 |
|
|
end trafic_supervision;
|
| 896 |
|
|
|
| 897 |
|
|
architecture rtl of trafic_supervision is
|
| 898 |
|
|
|
| 899 |
|
|
signal shreg : std_logic_vector(tot_priority-1 downto 0);
|
| 900 |
|
|
signal cntr : integer range 0 to tot_priority;
|
| 901 |
|
|
|
| 902 |
|
|
begin -- rtl
|
| 903 |
|
|
|
| 904 |
|
|
-- purpose: holds information of usage of latest cycles
|
| 905 |
|
|
-- type : sequential
|
| 906 |
|
|
-- inputs : clk, reset, ce, bg
|
| 907 |
|
|
-- outputs: shreg('left)
|
| 908 |
|
|
sh_reg: process (clk)
|
| 909 |
|
|
begin -- process shreg
|
| 910 |
|
|
if clk'event and clk = '1' then -- rising clock edge
|
| 911 |
|
|
if ce='1' then
|
| 912 |
|
|
shreg <= shreg(tot_priority-2 downto 0) & bg;
|
| 913 |
|
|
end if;
|
| 914 |
|
|
end if;
|
| 915 |
|
|
end process sh_reg;
|
| 916 |
|
|
|
| 917 |
|
|
-- purpose: keeps track of used cycles
|
| 918 |
|
|
-- type : sequential
|
| 919 |
|
|
-- inputs : clk, reset, shreg('left), bg, ce
|
| 920 |
|
|
-- outputs: trafic_limit
|
| 921 |
|
|
counter: process (clk, reset)
|
| 922 |
|
|
begin -- process counter
|
| 923 |
|
|
if reset = '1' then -- asynchronous reset (active hi)
|
| 924 |
|
|
cntr <= 0;
|
| 925 |
|
|
trafic_limit <= '0';
|
| 926 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
| 927 |
|
|
if ce='1' then
|
| 928 |
4 |
unneback |
if bg='1' and shreg(tot_priority-1)/='1' then
|
| 929 |
2 |
unneback |
cntr <= cntr + 1;
|
| 930 |
|
|
if cntr=priority-1 then
|
| 931 |
|
|
trafic_limit <= '1';
|
| 932 |
|
|
end if;
|
| 933 |
|
|
elsif bg='0' and shreg(tot_priority-1)='1' then
|
| 934 |
|
|
cntr <= cntr - 1;
|
| 935 |
|
|
if cntr=priority then
|
| 936 |
|
|
trafic_limit <= '0';
|
| 937 |
|
|
end if;
|
| 938 |
|
|
end if;
|
| 939 |
|
|
end if;
|
| 940 |
|
|
end if;
|
| 941 |
|
|
end process counter;
|
| 942 |
|
|
|
| 943 |
|
|
end rtl;
|
| 944 |
|
|
EOP
|
| 945 |
|
|
} else {
|
| 946 |
|
|
print OUTFILE<<EOP;
|
| 947 |
|
|
library IEEE;
|
| 948 |
|
|
use IEEE.std_logic_1164.all;
|
| 949 |
|
|
|
| 950 |
|
|
entity trafic_supervision is
|
| 951 |
|
|
|
| 952 |
|
|
generic (
|
| 953 |
11 |
unneback |
priority : integer := 1;
|
| 954 |
|
|
tot_priority : integer := 2);
|
| 955 |
2 |
unneback |
|
| 956 |
|
|
port (
|
| 957 |
|
|
bg : in std_logic; -- bus grant
|
| 958 |
|
|
ce : in std_logic; -- clock enable
|
| 959 |
|
|
trafic_limit : out std_logic;
|
| 960 |
|
|
clk : in std_logic;
|
| 961 |
|
|
reset : in std_logic);
|
| 962 |
|
|
|
| 963 |
|
|
end trafic_supervision;
|
| 964 |
|
|
|
| 965 |
|
|
architecture rtl of trafic_supervision is
|
| 966 |
|
|
|
| 967 |
|
|
signal shreg : std_logic_vector(tot_priority-1 downto 0);
|
| 968 |
|
|
signal cntr : integer range 0 to tot_priority;
|
| 969 |
|
|
|
| 970 |
|
|
begin -- rtl
|
| 971 |
|
|
|
| 972 |
|
|
-- purpose: holds information of usage of latest cycles
|
| 973 |
|
|
-- type : sequential
|
| 974 |
|
|
-- inputs : clk, reset, ce, bg
|
| 975 |
|
|
-- outputs: shreg('left)
|
| 976 |
|
|
sh_reg: process (clk,reset)
|
| 977 |
|
|
begin -- process shreg
|
| 978 |
|
|
if reset = '1' then -- asynchronous reset (active hi)
|
| 979 |
|
|
shreg <= (others=>'0');
|
| 980 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
| 981 |
|
|
if ce='1' then
|
| 982 |
|
|
shreg <= shreg(tot_priority-2 downto 0) & bg;
|
| 983 |
|
|
end if;
|
| 984 |
|
|
end if;
|
| 985 |
|
|
end process sh_reg;
|
| 986 |
|
|
|
| 987 |
|
|
-- purpose: keeps track of used cycles
|
| 988 |
|
|
-- type : sequential
|
| 989 |
|
|
-- inputs : clk, reset, shreg('left), bg, ce
|
| 990 |
|
|
-- outputs: trafic_limit
|
| 991 |
|
|
counter: process (clk, reset)
|
| 992 |
|
|
begin -- process counter
|
| 993 |
|
|
if reset = '1' then -- asynchronous reset (active hi)
|
| 994 |
|
|
cntr <= 0;
|
| 995 |
|
|
trafic_limit <= '0';
|
| 996 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
| 997 |
|
|
if ce='1' then
|
| 998 |
|
|
if bg='1' and shreg(tot_priority-1)='0' then
|
| 999 |
|
|
cntr <= cntr + 1;
|
| 1000 |
|
|
if cntr=priority-1 then
|
| 1001 |
|
|
trafic_limit <= '1';
|
| 1002 |
|
|
end if;
|
| 1003 |
|
|
elsif bg='0' and shreg(tot_priority-1)='1' then
|
| 1004 |
|
|
cntr <= cntr - 1;
|
| 1005 |
|
|
if cntr=priority then
|
| 1006 |
|
|
trafic_limit <= '0';
|
| 1007 |
|
|
end if;
|
| 1008 |
|
|
end if;
|
| 1009 |
|
|
end if;
|
| 1010 |
|
|
end if;
|
| 1011 |
|
|
end process counter;
|
| 1012 |
|
|
|
| 1013 |
|
|
end rtl;
|
| 1014 |
|
|
EOP
|
| 1015 |
|
|
};
|
| 1016 |
|
|
} else {
|
| 1017 |
|
|
|
| 1018 |
|
|
};
|
| 1019 |
|
|
};
|
| 1020 |
|
|
|
| 1021 |
|
|
sub gen_entity {
|
| 1022 |
|
|
# library usage
|
| 1023 |
|
|
printf OUTFILE "\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n";
|
| 1024 |
|
|
printf OUTFILE "use work.%s_package.all;\n",$intercon;
|
| 1025 |
|
|
|
| 1026 |
|
|
# entity intercon
|
| 1027 |
|
|
printf OUTFILE "\nentity %s is\n port (\n",$intercon;
|
| 1028 |
|
|
# records
|
| 1029 |
|
|
if ($signal_groups eq 1) {
|
| 1030 |
|
|
# master port(s)
|
| 1031 |
|
|
printf OUTFILE " -- wishbone master port(s)\n";
|
| 1032 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1033 |
|
|
printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
|
| 1034 |
|
|
printf OUTFILE " %s_wbm_i : out %s_wbm_i_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1035 |
|
|
printf OUTFILE " %s_wbm_o : in %s_wbm_o_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1036 |
|
|
}; #end for
|
| 1037 |
|
|
# slave port(s)
|
| 1038 |
|
|
printf OUTFILE " -- wishbone slave port(s)\n";
|
| 1039 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1040 |
|
|
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
|
| 1041 |
|
|
printf OUTFILE " %s_wbs_i : out %s_wbs_i_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1042 |
|
|
printf OUTFILE " %s_wbs_o : in %s_wbs_o_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1043 |
|
|
};
|
| 1044 |
|
|
# separate signals
|
| 1045 |
|
|
} else {
|
| 1046 |
|
|
printf OUTFILE " -- wishbone master port(s)\n";
|
| 1047 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1048 |
|
|
printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
|
| 1049 |
|
|
if ($master[$i]{"type"} ne "wo") {
|
| 1050 |
|
|
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1; };
|
| 1051 |
|
|
printf OUTFILE " %s_ack_i : out std_logic;\n",$master[$i]{"wbm"};
|
| 1052 |
|
|
if ($master[$i]{"err_i"} eq 1) {
|
| 1053 |
|
|
printf OUTFILE " %s_err_i : out std_logic;\n",$master[$i]{"wbm"}; };
|
| 1054 |
|
|
if ($master[$i]{"rty_i"} eq 1) {
|
| 1055 |
|
|
printf OUTFILE " %s_rty_i : out std_logic;\n",$master[$i]{"wbm"}; };
|
| 1056 |
|
|
if ($master[$i]{"type"} ne "ro") {
|
| 1057 |
|
|
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1;
|
| 1058 |
|
|
printf OUTFILE " %s_we_o : in std_logic;\n",$master[$i]{"wbm"};
|
| 1059 |
|
|
};
|
| 1060 |
|
|
if ($dat_size ge 16) {
|
| 1061 |
|
|
printf OUTFILE " %s_sel_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size/8-1; };
|
| 1062 |
|
|
printf OUTFILE " %s_adr_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$adr_size-1;
|
| 1063 |
|
|
if ($master[$i]{"tgc_o"} eq 1) {
|
| 1064 |
|
|
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tgc,$tgc_bits-1; };
|
| 1065 |
|
|
if ($master[$i]{"tga_o"} eq 1) {
|
| 1066 |
|
|
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tga,$tga_bits-1; };
|
| 1067 |
|
|
printf OUTFILE " %s_cyc_o : in std_logic;\n",$master[$i]{"wbm"};
|
| 1068 |
|
|
printf OUTFILE " %s_stb_o : in std_logic;\n",$master[$i]{"wbm"};
|
| 1069 |
|
|
};
|
| 1070 |
|
|
printf OUTFILE " -- wishbone slave port(s)\n";
|
| 1071 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1072 |
|
|
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
|
| 1073 |
|
|
if ($slave[$i]{"type"} ne "wo") {
|
| 1074 |
|
|
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1; };
|
| 1075 |
|
|
printf OUTFILE " %s_ack_o : in std_logic;\n",$slave[$i]{"wbs"};
|
| 1076 |
|
|
if ($slave[$i]{"err_o"} eq 1) {
|
| 1077 |
|
|
printf OUTFILE " %s_err_o : in std_logic;\n",$slave[$i]{"wbs"}; };
|
| 1078 |
|
|
if ($slave[$i]{"rty_o"} eq 1) {
|
| 1079 |
|
|
printf OUTFILE " %s_rty_o : in std_logic;\n",$slave[$i]{"wbs"}; };
|
| 1080 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 1081 |
|
|
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1;
|
| 1082 |
|
|
printf OUTFILE " %s_we_i : out std_logic;\n",$slave[$i]{"wbs"};
|
| 1083 |
|
|
};
|
| 1084 |
|
|
if ($dat_size ge 16) {
|
| 1085 |
|
|
printf OUTFILE " %s_sel_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size/8-1; };
|
| 1086 |
|
|
printf OUTFILE " %s_adr_i : out std_logic_vector(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
|
| 1087 |
|
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
| 1088 |
|
|
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tgc,$tgc_bits-1; };
|
| 1089 |
|
|
if ($slave[$i]{"tga_i"} eq 1) {
|
| 1090 |
|
|
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tga,$tga_bits-1; };
|
| 1091 |
|
|
printf OUTFILE " %s_cyc_i : out std_logic;\n",$slave[$i]{"wbs"};
|
| 1092 |
|
|
printf OUTFILE " %s_stb_i : out std_logic;\n",$slave[$i]{"wbs"};
|
| 1093 |
|
|
};
|
| 1094 |
|
|
};
|
| 1095 |
|
|
# clock and reset
|
| 1096 |
|
|
printf OUTFILE " -- clock and reset\n";
|
| 1097 |
|
|
printf OUTFILE " clk : in std_logic;\n";
|
| 1098 |
|
|
printf OUTFILE " reset : in std_logic);\n";
|
| 1099 |
|
|
printf OUTFILE "end %s;\n",$intercon;
|
| 1100 |
|
|
};
|
| 1101 |
|
|
|
| 1102 |
|
|
|
| 1103 |
|
|
# generate signals for remapping (for records)
|
| 1104 |
|
|
sub gen_sig_remap {
|
| 1105 |
|
|
sub gen_sig_dec {
|
| 1106 |
|
|
if ($_[1] gt 0) {
|
| 1107 |
|
|
printf OUTFILE " signal %s : std_logic_vector(%s downto %s);\n",$_[0],$_[1]-1,$_[2];
|
| 1108 |
|
|
} else {
|
| 1109 |
|
|
printf OUTFILE " signal %s : std_logic;\n",$_[0];
|
| 1110 |
|
|
};
|
| 1111 |
|
|
};
|
| 1112 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1113 |
|
|
if ($master[$i]{"type"} ne "wo") {
|
| 1114 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_dat_i',$dat_size,0); };
|
| 1115 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_ack_i');
|
| 1116 |
|
|
if ($master[$i]{"err_i"} eq 1) {
|
| 1117 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_err_i'); };
|
| 1118 |
|
|
if ($master[$i]{"rty_i"} eq 1) {
|
| 1119 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_rty_i') };
|
| 1120 |
|
|
if ($master[$i]{"type"} ne "ro") {
|
| 1121 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_dat_o',$dat_size,0);
|
| 1122 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_we_o ');
|
| 1123 |
|
|
};
|
| 1124 |
|
|
if ($dat_size > 8) {
|
| 1125 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_sel_o',$dat_size/8,0); };
|
| 1126 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_adr_o',$adr_size,0);
|
| 1127 |
|
|
if ($master[$i]{"tga_o"} eq 1) {
|
| 1128 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tga.'_o',$tga_bits,0); };
|
| 1129 |
|
|
if ($master[$i]{"tgc_o"} eq 1) {
|
| 1130 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgc.'_o',$tgc_bits,0); };
|
| 1131 |
|
|
if ($master[$i]{"tgd_o"} eq 1) {
|
| 1132 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgd.'_o',$tgd_bits,0); };
|
| 1133 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_cyc_o');
|
| 1134 |
|
|
gen_sig_dec($master[$i]{"wbm"}.'_stb_o');
|
| 1135 |
|
|
};
|
| 1136 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1137 |
|
|
if ($slave[$i]{"type"} ne "wo") {
|
| 1138 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_dat_o',$dat_size,0); };
|
| 1139 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_ack_o');
|
| 1140 |
|
|
if ($slave[$i]{"err_o"} eq 1) {
|
| 1141 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_err_o'); };
|
| 1142 |
|
|
if ($slave[$i]{"rty_o"} eq 1) {
|
| 1143 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_rty_o'); };
|
| 1144 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 1145 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_dat_i',$dat_size,0);
|
| 1146 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_we_i ');
|
| 1147 |
|
|
};
|
| 1148 |
|
|
if ($dat_size > 8) {
|
| 1149 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_sel_i',$dat_size/8,0); };
|
| 1150 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_adr_i',$slave[$i]{"adr_i_hi"}+1,$slave[$i]{"adr_i_lo"});
|
| 1151 |
|
|
if ($slave[$i]{"tga_i"} eq 1) {
|
| 1152 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tga.'_i',$tga_bits,0); };
|
| 1153 |
|
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
| 1154 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgc.'_i',$tgc_bits,0); };
|
| 1155 |
|
|
if ($slave[$i]{"tgd_i"} eq 1) {
|
| 1156 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgd.'_i',$tgd_bits,0); };
|
| 1157 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_cyc_i');
|
| 1158 |
|
|
gen_sig_dec($slave[$i]{"wbs"}.'_stb_i');
|
| 1159 |
|
|
};
|
| 1160 |
|
|
};
|
| 1161 |
|
|
|
| 1162 |
|
|
sub gen_global_signals {
|
| 1163 |
|
|
# single master
|
| 1164 |
|
|
if ($masters eq 1) {
|
| 1165 |
|
|
# slave select for generation of stb_i to slaves
|
| 1166 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1167 |
|
|
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
|
| 1168 |
|
|
# shared bus
|
| 1169 |
|
|
} elsif ($interconnect eq "sharedbus") {
|
| 1170 |
|
|
# bus grant
|
| 1171 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1172 |
|
|
printf OUTFILE " signal %s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"}; };
|
| 1173 |
|
|
# slave select for generation of stb_i to slaves
|
| 1174 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1175 |
|
|
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
|
| 1176 |
|
|
# crossbarswitch
|
| 1177 |
|
|
} else {
|
| 1178 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1179 |
|
|
for ($j=1; $j le $slaves; $j++) {
|
| 1180 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1181 |
|
|
printf OUTFILE " signal %s_%s_ss : std_logic; -- slave select\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1182 |
|
|
printf OUTFILE " signal %s_%s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1183 |
|
|
};
|
| 1184 |
|
|
};
|
| 1185 |
|
|
};
|
| 1186 |
|
|
};
|
| 1187 |
|
|
};
|
| 1188 |
|
|
|
| 1189 |
|
|
sub gen_arbiter {
|
| 1190 |
|
|
# out: wbm_bg (bus grant)
|
| 1191 |
|
|
if ($masters eq 1) {
|
| 1192 |
|
|
# ack_i
|
| 1193 |
|
|
# cyc_i
|
| 1194 |
|
|
# printf OUTFILE "%s_bg <= %s_cyc_o;\n",$master[1]{"wbm"},$master[1]{"wbm"};
|
| 1195 |
|
|
# sharedbus
|
| 1196 |
|
|
} elsif ($interconnect eq "sharedbus") {
|
| 1197 |
|
|
printf OUTFILE "arbiter_sharedbus: block\n";
|
| 1198 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1199 |
|
|
printf OUTFILE " signal %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1200 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1201 |
|
|
printf OUTFILE " signal %s_trafic_ctrl_limit : std_logic;\n",$master[$i]{"wbm"}; };
|
| 1202 |
|
|
printf OUTFILE " signal ack, ce, idle :std_logic;\n";
|
| 1203 |
|
|
printf OUTFILE "begin -- arbiter\n";
|
| 1204 |
|
|
printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
|
| 1205 |
|
|
for ($i=2; $i le $slaves; $i++) {
|
| 1206 |
|
|
printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
|
| 1207 |
|
|
printf OUTFILE ";\n";
|
| 1208 |
|
|
# instantiate trafic_supervision(s)
|
| 1209 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1210 |
|
|
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
|
| 1211 |
|
|
printf OUTFILE "generic map(\n";
|
| 1212 |
|
|
printf OUTFILE " priority => %s,\n",$master[$i]{"priority"};
|
| 1213 |
|
|
printf OUTFILE " tot_priority => %s)\n",$priority;
|
| 1214 |
|
|
printf OUTFILE "port map(\n";
|
| 1215 |
|
|
printf OUTFILE " bg => %s_bg,\n",$master[$i]{"wbm"};
|
| 1216 |
|
|
printf OUTFILE " ce => ce,\n";
|
| 1217 |
|
|
printf OUTFILE " trafic_limit => %s_trafic_ctrl_limit,\n",$master[$i]{"wbm"};
|
| 1218 |
|
|
printf OUTFILE " clk => clk,\n";
|
| 1219 |
|
|
printf OUTFILE " reset => reset);\n"; };
|
| 1220 |
|
|
# _bg_q
|
| 1221 |
|
|
# bg eq 1 => set
|
| 1222 |
|
|
# end of cycle => reset
|
| 1223 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1224 |
|
|
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
|
| 1225 |
|
|
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
|
| 1226 |
|
|
printf OUTFILE "elsif clk'event and clk='1' then\n";
|
| 1227 |
|
|
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
|
| 1228 |
|
|
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1229 |
|
|
printf OUTFILE "elsif ack='1'";
|
| 1230 |
|
|
if ($master[$i]{"tgc_o"} eq 1) {
|
| 1231 |
|
|
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
|
| 1232 |
|
|
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
|
| 1233 |
|
|
}; # end for
|
| 1234 |
|
|
# _bg
|
| 1235 |
|
|
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[1]{"wbm"};
|
| 1236 |
|
|
for ($i=2; $i le $masters; $i++) {
|
| 1237 |
|
|
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"}; };
|
| 1238 |
|
|
printf OUTFILE " else '0';\n";
|
| 1239 |
|
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' else '0';\n",$master[1]{"wbm"},$master[1]{"wbm"},$master[1]{"wbm"};
|
| 1240 |
7 |
unneback |
$depend = $master[1]{"wbm"}."_bg_1='0'";
|
| 1241 |
2 |
unneback |
for ($i=2; $i le $masters; $i++) {
|
| 1242 |
7 |
unneback |
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' and (%s) else '0';\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$depend;
|
| 1243 |
|
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
|
| 1244 |
|
|
};
|
| 1245 |
|
|
|
| 1246 |
|
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[1]{"wbm"},$depend,$master[1]{"wbm"};
|
| 1247 |
|
|
$depend = $depend." and ".$master[1]{"wbm"}."_bg_2='0'";
|
| 1248 |
2 |
unneback |
for ($i=2; $i le $masters; $i++) {
|
| 1249 |
7 |
unneback |
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"};
|
| 1250 |
|
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
|
| 1251 |
|
|
};
|
| 1252 |
2 |
unneback |
for ($i=1; $i le $masters; $i++) {
|
| 1253 |
7 |
unneback |
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1254 |
2 |
unneback |
# ce
|
| 1255 |
|
|
printf OUTFILE "ce <= %s_cyc_o",$master[1]{"wbm"};
|
| 1256 |
|
|
for ($i=2; $i le $masters; $i++) {
|
| 1257 |
|
|
printf OUTFILE " or %s_cyc_o",$master[$i]{"wbm"}; };
|
| 1258 |
|
|
printf OUTFILE " when idle='1' else '0';\n\n";
|
| 1259 |
|
|
# thats it
|
| 1260 |
|
|
printf OUTFILE "end block arbiter_sharedbus;\n\n";
|
| 1261 |
|
|
# interconnect crossbarswitch
|
| 1262 |
|
|
} else {
|
| 1263 |
|
|
for ($j=1; $j le $slaves; $j++) {
|
| 1264 |
|
|
# single master ?
|
| 1265 |
|
|
$tmp=0;
|
| 1266 |
|
|
for ($l=1; $l le $masters; $l++) {
|
| 1267 |
|
|
if ($master[$l]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1268 |
|
|
$only_master = $l;
|
| 1269 |
|
|
$tmp++;
|
| 1270 |
|
|
};
|
| 1271 |
|
|
};
|
| 1272 |
|
|
if ($tmp == 1) {
|
| 1273 |
|
|
printf OUTFILE "%s_%s_bg <= %s_%s_ss and %s_cyc_o;\n",$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"};
|
| 1274 |
|
|
} else {
|
| 1275 |
|
|
printf OUTFILE "arbiter_%s : block\n",$slave[$j]{"wbs"};
|
| 1276 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1277 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1278 |
|
|
printf OUTFILE " signal %s_bg, %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1279 |
|
|
printf OUTFILE " signal %s_trafic_limit : std_logic;\n",$master[$i]{"wbm"};
|
| 1280 |
|
|
};
|
| 1281 |
|
|
};
|
| 1282 |
|
|
printf OUTFILE " signal ce, idle, ack : std_logic;\n";
|
| 1283 |
|
|
printf OUTFILE "begin\n";
|
| 1284 |
|
|
printf OUTFILE "ack <= %s_ack_o;\n",$slave[$j]{"wbs"};
|
| 1285 |
|
|
# instantiate trafic_supervision(s)
|
| 1286 |
|
|
# calc tot priority per slave
|
| 1287 |
|
|
$priority = 0;
|
| 1288 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1289 |
|
|
$priority += $master[$i]{("priority_".($slave[$j]{"wbs"}))}; };
|
| 1290 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1291 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1292 |
|
|
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
|
| 1293 |
|
|
printf OUTFILE "generic map(\n";
|
| 1294 |
|
|
printf OUTFILE " priority => %s,\n",$master[$i]{("priority_".($slave[$j]{"wbs"}))};
|
| 1295 |
|
|
printf OUTFILE " tot_priority => %s)\n",$priority;
|
| 1296 |
|
|
printf OUTFILE "port map(\n";
|
| 1297 |
|
|
printf OUTFILE " bg => %s_%s_bg,\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1298 |
|
|
printf OUTFILE " ce => ce,\n";
|
| 1299 |
|
|
printf OUTFILE " trafic_limit => %s_trafic_limit,\n",$master[$i]{"wbm"};
|
| 1300 |
|
|
printf OUTFILE " clk => clk,\n";
|
| 1301 |
|
|
printf OUTFILE " reset => reset);\n";
|
| 1302 |
|
|
};
|
| 1303 |
|
|
};
|
| 1304 |
|
|
# _bg_q
|
| 1305 |
|
|
# bg eq 1 => set
|
| 1306 |
|
|
# end of cycle => reset
|
| 1307 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1308 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1309 |
|
|
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
|
| 1310 |
|
|
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
|
| 1311 |
|
|
printf OUTFILE "elsif clk'event and clk='1' then\n";
|
| 1312 |
|
|
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
|
| 1313 |
|
|
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1314 |
|
|
printf OUTFILE "elsif ack='1'";
|
| 1315 |
|
|
if ($master[$i]{"tgc_o"} eq 1) {
|
| 1316 |
|
|
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
|
| 1317 |
|
|
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
|
| 1318 |
|
|
};
|
| 1319 |
|
|
}; # end for
|
| 1320 |
|
|
# _bg
|
| 1321 |
7 |
unneback |
$depend = "";
|
| 1322 |
2 |
unneback |
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
|
| 1323 |
|
|
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[$tmp]{"wbm"};
|
| 1324 |
|
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
| 1325 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1326 |
|
|
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"};
|
| 1327 |
|
|
};
|
| 1328 |
|
|
};
|
| 1329 |
|
|
printf OUTFILE " else '0';\n";
|
| 1330 |
|
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"},$master[$tmp]{"wbm"};
|
| 1331 |
7 |
unneback |
$depend = $master[$tmp]{"wbm"}."_bg_1='0'",;
|
| 1332 |
2 |
unneback |
for ($i=$tmp+1; $i le $masters; $i++) {
|
| 1333 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1334 |
7 |
unneback |
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};;
|
| 1335 |
|
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
|
| 1336 |
2 |
unneback |
};
|
| 1337 |
|
|
};
|
| 1338 |
7 |
unneback |
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$tmp]{"wbm"},$depend,$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
|
| 1339 |
|
|
$depend = $depend." and ".$master[$tmp]{"wbm"}."_bg_2='0'";
|
| 1340 |
2 |
unneback |
$tmp1 = $tmp;
|
| 1341 |
|
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
| 1342 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1343 |
7 |
unneback |
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1344 |
|
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
|
| 1345 |
2 |
unneback |
};
|
| 1346 |
|
|
};
|
| 1347 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1348 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1349 |
|
|
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1350 |
|
|
};
|
| 1351 |
|
|
};
|
| 1352 |
|
|
# ce
|
| 1353 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
|
| 1354 |
|
|
printf OUTFILE "ce <= (%s_cyc_o and %s_%s_ss)",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
|
| 1355 |
|
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
| 1356 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1357 |
|
|
printf OUTFILE " or (%s_cyc_o and %s_%s_ss)",$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1358 |
|
|
};
|
| 1359 |
|
|
};
|
| 1360 |
|
|
printf OUTFILE " when idle='1' else '0';\n";
|
| 1361 |
|
|
# global bg
|
| 1362 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1363 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1364 |
|
|
printf OUTFILE "%s_%s_bg <= %s_bg;\n",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};
|
| 1365 |
|
|
};
|
| 1366 |
|
|
};
|
| 1367 |
|
|
printf OUTFILE "end block arbiter_%s;\n",$slave[$j]{"wbs"};
|
| 1368 |
|
|
};
|
| 1369 |
|
|
};
|
| 1370 |
|
|
}; #end if
|
| 1371 |
|
|
};
|
| 1372 |
|
|
|
| 1373 |
|
|
sub gen_adr_decoder{
|
| 1374 |
|
|
printf OUTFILE "decoder:block\n";
|
| 1375 |
|
|
if ($interconnect eq "sharedbus") {
|
| 1376 |
|
|
printf OUTFILE " signal adr : std_logic_vector(%s downto 0);\n",$adr_size-1;
|
| 1377 |
|
|
printf OUTFILE "begin\n";
|
| 1378 |
|
|
# adr
|
| 1379 |
|
|
printf OUTFILE "adr <= (%s_adr_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
| 1380 |
|
|
if ($masters gt 1){
|
| 1381 |
|
|
for ($i=2; $i le $masters; $i++) {
|
| 1382 |
|
|
printf OUTFILE " or (%s_adr_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1383 |
|
|
};
|
| 1384 |
|
|
printf OUTFILE ";\n";
|
| 1385 |
|
|
# slave select
|
| 1386 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1387 |
|
|
printf OUTFILE "%s_ss <= '1' when adr(%s downto %s)=\"",$slave[$i]{"wbs"}, $adr_size-1,log(hex($slave[$i]{"size"}))/log(2);
|
| 1388 |
|
|
$slave[$i]{"baseadr"}=hex($slave[$i]{"baseadr"});
|
| 1389 |
|
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size"}))/log(2)); $j--) {
|
| 1390 |
|
|
if (($slave[$i]{"baseadr"}) >= (2**$j)) {
|
| 1391 |
|
|
$slave[$i]{"baseadr"} -= 2**$j;
|
| 1392 |
|
|
printf OUTFILE "1";
|
| 1393 |
|
|
} else {
|
| 1394 |
|
|
printf OUTFILE "0";
|
| 1395 |
|
|
};
|
| 1396 |
|
|
};
|
| 1397 |
|
|
printf OUTFILE "\"";
|
| 1398 |
|
|
# 1
|
| 1399 |
|
|
if ($slave[$i]{"size1"} ne "ffffffff") {
|
| 1400 |
|
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size1"}))/log(2);
|
| 1401 |
|
|
$slave[$i]{"baseadr1"}=hex($slave[$i]{"baseadr1"});
|
| 1402 |
|
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size1"}))/log(2)); $j--) {
|
| 1403 |
|
|
if (($slave[$i]{"baseadr1"}) >= (2**$j)) {
|
| 1404 |
|
|
$slave[$i]{"baseadr1"} -= 2**$j;
|
| 1405 |
|
|
printf OUTFILE "1";
|
| 1406 |
|
|
} else {
|
| 1407 |
|
|
printf OUTFILE "0";
|
| 1408 |
|
|
}; # end if
|
| 1409 |
|
|
}; # end for
|
| 1410 |
|
|
printf OUTFILE "\"";
|
| 1411 |
|
|
};
|
| 1412 |
|
|
# 2
|
| 1413 |
|
|
if ($slave[$i]{"size2"} ne "ffffffff") {
|
| 1414 |
|
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size2"}))/log(2);
|
| 1415 |
|
|
$slave[$i]{"baseadr2"}=hex($slave[$i]{"baseadr2"});
|
| 1416 |
|
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size2"}))/log(2)); $j--) {
|
| 1417 |
|
|
if (($slave[$i]{"baseadr2"}) >= (2**$j)) {
|
| 1418 |
|
|
$slave[$i]{"baseadr2"} -= 2**$j;
|
| 1419 |
|
|
printf OUTFILE "1";
|
| 1420 |
|
|
} else {
|
| 1421 |
|
|
printf OUTFILE "0";
|
| 1422 |
|
|
};
|
| 1423 |
|
|
};
|
| 1424 |
|
|
printf OUTFILE "\"";
|
| 1425 |
|
|
};
|
| 1426 |
|
|
# 3
|
| 1427 |
|
|
if ($slave[$i]{"size3"} ne "ffffffff") {
|
| 1428 |
|
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size3"}))/log(2);
|
| 1429 |
|
|
$slave[$i]{"baseadr3"}=hex($slave[$i]{"baseadr3"});
|
| 1430 |
|
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size3"}))/log(2)); $j--) {
|
| 1431 |
|
|
if (($slave[$i]{"baseadr3"}) >= (2**$j)) {
|
| 1432 |
|
|
$slave[$i]{"baseadr3"} -= 2**$j;
|
| 1433 |
|
|
printf OUTFILE "1";
|
| 1434 |
|
|
} else {
|
| 1435 |
|
|
printf OUTFILE "0";
|
| 1436 |
|
|
};
|
| 1437 |
|
|
};
|
| 1438 |
|
|
printf OUTFILE "\"";
|
| 1439 |
|
|
};
|
| 1440 |
|
|
printf OUTFILE " else\n'0';\n";
|
| 1441 |
|
|
# adr to slaves
|
| 1442 |
|
|
};
|
| 1443 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1444 |
|
|
printf OUTFILE "%s_adr_i <= adr(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"}; };
|
| 1445 |
|
|
# crossbar switch
|
| 1446 |
|
|
} else {
|
| 1447 |
|
|
printf OUTFILE "begin\n";
|
| 1448 |
|
|
# master_slave_ss
|
| 1449 |
|
|
# $j=0;
|
| 1450 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1451 |
|
|
$slave[$j]{"baseadr"}=hex($slave[$j]{"baseadr"});
|
| 1452 |
|
|
for ($j=1; $j le $slaves; $j++) {
|
| 1453 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1454 |
|
|
printf OUTFILE "%s_%s_ss <= '1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size"}))/log(2);
|
| 1455 |
|
|
$tmp=hex($slave[$j]{"baseadr"});
|
| 1456 |
|
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size"}))/log(2)); $k--) {
|
| 1457 |
|
|
if ($tmp >= (2**$k)) {
|
| 1458 |
|
|
$tmp -= 2**$k;
|
| 1459 |
|
|
printf OUTFILE "1";
|
| 1460 |
|
|
} else {
|
| 1461 |
|
|
printf OUTFILE "0";
|
| 1462 |
|
|
};
|
| 1463 |
|
|
};
|
| 1464 |
|
|
printf OUTFILE "\"";
|
| 1465 |
|
|
# 2?
|
| 1466 |
|
|
if ($slave[$j]{"size1"} ne "ffffffff") {
|
| 1467 |
|
|
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size1"}))/log(2);
|
| 1468 |
|
|
$tmp=hex($slave[$j]{"baseadr1"});
|
| 1469 |
|
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size1"}))/log(2)); $k--) {
|
| 1470 |
|
|
if ($tmp >= (2**$k)) {
|
| 1471 |
|
|
$tmp -= 2**$k;
|
| 1472 |
|
|
printf OUTFILE "1";
|
| 1473 |
|
|
} else {
|
| 1474 |
|
|
printf OUTFILE "0";
|
| 1475 |
|
|
};
|
| 1476 |
|
|
};
|
| 1477 |
|
|
printf OUTFILE "\"";
|
| 1478 |
|
|
};
|
| 1479 |
|
|
# 3?
|
| 1480 |
|
|
if ($slave[$j]{"size2"} ne "ffffffff") {
|
| 1481 |
|
|
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size2"}))/log(2);
|
| 1482 |
|
|
$tmp=hex($slave[$j]{"baseadr2"});
|
| 1483 |
|
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size2"}))/log(2)); $k--) {
|
| 1484 |
|
|
if ($tmp >= (2**$k)) {
|
| 1485 |
|
|
$tmp -= 2**$k;
|
| 1486 |
|
|
printf OUTFILE "1";
|
| 1487 |
|
|
} else {
|
| 1488 |
|
|
printf OUTFILE "0";
|
| 1489 |
|
|
};
|
| 1490 |
|
|
};
|
| 1491 |
|
|
printf OUTFILE "\"";
|
| 1492 |
|
|
};
|
| 1493 |
|
|
printf OUTFILE " else \n'0';\n";
|
| 1494 |
|
|
}; #if
|
| 1495 |
|
|
};
|
| 1496 |
|
|
};
|
| 1497 |
|
|
# _adr_o
|
| 1498 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1499 |
|
|
# mux ?
|
| 1500 |
|
|
$tmp=0;
|
| 1501 |
|
|
for ($l=1; $l le $masters; $l++) {
|
| 1502 |
|
|
if ($master[$l]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1503 |
|
|
$tmp++;
|
| 1504 |
|
|
};
|
| 1505 |
|
|
};
|
| 1506 |
|
|
if ($tmp eq 1) {
|
| 1507 |
|
|
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
|
| 1508 |
|
|
printf OUTFILE "%s_adr_i <= %s_adr_o(%s downto %s);\n",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
|
| 1509 |
|
|
} else {
|
| 1510 |
|
|
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
|
| 1511 |
|
|
printf OUTFILE "%s_adr_i <= (%s_adr_o(%s downto %s) and %s_%s_bg)",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$k]{"wbm"},$slave[$i]{"wbs"};
|
| 1512 |
|
|
for ($j=$k+1; $j le $masters; $j++) {
|
| 1513 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1514 |
|
|
printf OUTFILE " or (%s_adr_o(%s downto %s) and %s_%s_bg)",$master[$j]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1515 |
|
|
};
|
| 1516 |
|
|
};
|
| 1517 |
|
|
printf OUTFILE ";\n";
|
| 1518 |
|
|
};
|
| 1519 |
|
|
};
|
| 1520 |
|
|
};
|
| 1521 |
|
|
printf OUTFILE "end block decoder;\n\n";
|
| 1522 |
|
|
};
|
| 1523 |
|
|
|
| 1524 |
|
|
sub gen_muxshb{
|
| 1525 |
|
|
printf OUTFILE "mux: block\n";
|
| 1526 |
|
|
printf OUTFILE " signal cyc, stb, we, ack : std_logic;\n";
|
| 1527 |
|
|
if (($rty_i gt 0) && ($rty_o gt 1)) {
|
| 1528 |
|
|
printf OUTFILE " signal rty : std_logic;\n"; };
|
| 1529 |
|
|
if (($err_i gt 0) && ($err_o gt 1)) {
|
| 1530 |
|
|
printf OUTFILE " signal err : std_logic;\n"; };
|
| 1531 |
|
|
if ($dat_size eq 8) {
|
| 1532 |
|
|
printf OUTFILE " signal sel : std_logic;\n";
|
| 1533 |
|
|
} else {
|
| 1534 |
|
|
printf OUTFILE " signal sel : std_logic_vector(%s downto 0);\n",$dat_size/8-1;
|
| 1535 |
|
|
};
|
| 1536 |
|
|
printf OUTFILE " signal dat_m2s, dat_s2m : std_logic_vector(%s downto 0);\n",$dat_size-1;
|
| 1537 |
|
|
if (($tgc_o gt 0) && ($tgc_i gt 0)) {
|
| 1538 |
|
|
printf OUTFILE " signal tgc : std_logic_vector(%s downto 0);\n",$tgc_bits-1; };
|
| 1539 |
|
|
if (($tga_o gt 0) && ($tga_i gt 0)) {
|
| 1540 |
|
|
printf OUTFILE " signal tga : std_logic_vector(%s downto 0);\n",$tga_bits-1; };
|
| 1541 |
|
|
printf OUTFILE "begin\n";
|
| 1542 |
|
|
# cyc
|
| 1543 |
|
|
printf OUTFILE "cyc <= (%s_cyc_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
| 1544 |
|
|
if ($masters gt 1) {
|
| 1545 |
|
|
for ($i=2; $i le $masters; $i++) {
|
| 1546 |
|
|
printf OUTFILE " or (%s_cyc_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1547 |
|
|
};
|
| 1548 |
|
|
printf OUTFILE ";\n";
|
| 1549 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1550 |
|
|
printf OUTFILE "%s_cyc_i <= %s_ss and cyc;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
| 1551 |
|
|
# stb
|
| 1552 |
|
|
printf OUTFILE "stb <= (%s_stb_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
| 1553 |
|
|
if ($masters gt 1) {
|
| 1554 |
|
|
for ($i=2; $i le $masters; $i++) {
|
| 1555 |
|
|
printf OUTFILE " or (%s_stb_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1556 |
|
|
};
|
| 1557 |
|
|
printf OUTFILE ";\n";
|
| 1558 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1559 |
|
|
printf OUTFILE "%s_stb_i <= stb;\n",$slave[$i]{"wbs"}; };
|
| 1560 |
|
|
# we
|
| 1561 |
|
|
$i=1; until ($master[$i]{"type"} ne "ro") {$i++};
|
| 1562 |
|
|
printf OUTFILE "we <= (%s_we_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1563 |
|
|
if ($i lt $masters) {
|
| 1564 |
|
|
for ($j=$i+1; $j le $masters; $j++) {
|
| 1565 |
|
|
if ($master[$j]{"type"} ne "ro") {
|
| 1566 |
|
|
printf OUTFILE " or (%s_we_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
|
| 1567 |
|
|
};
|
| 1568 |
|
|
};
|
| 1569 |
|
|
};
|
| 1570 |
|
|
printf OUTFILE ";\n";
|
| 1571 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1572 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 1573 |
|
|
printf OUTFILE "%s_we_i <= we;\n",$slave[$i]{"wbs"};
|
| 1574 |
|
|
};
|
| 1575 |
|
|
};
|
| 1576 |
|
|
# ack
|
| 1577 |
|
|
printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
|
| 1578 |
|
|
for ($i=2; $i le $slaves; $i++) {
|
| 1579 |
|
|
printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
|
| 1580 |
|
|
printf OUTFILE ";\n";
|
| 1581 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1582 |
|
|
printf OUTFILE "%s_ack_i <= ack and %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1583 |
|
|
# rty
|
| 1584 |
|
|
if (($rty_o eq 0) && ($rty_i gt 0)) {
|
| 1585 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1586 |
|
|
if ($master[$i]{"rty_i"} eq 1) {
|
| 1587 |
|
|
printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
|
| 1588 |
|
|
};
|
| 1589 |
|
|
};
|
| 1590 |
|
|
} elsif (($rty_o eq 1) && ($rty_i gt 0)) {
|
| 1591 |
|
|
$i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
|
| 1592 |
|
|
for ($j=1; $j le $masters; $j++) {
|
| 1593 |
|
|
if ($master[$j]{"rty_i"} eq 1) {
|
| 1594 |
|
|
printf OUTFILE "%s_rty_i <= %s_rty_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1595 |
|
|
};
|
| 1596 |
|
|
};
|
| 1597 |
|
|
} elsif (($rty_o gt 1) && ($rty_i gt 0)) {
|
| 1598 |
|
|
$i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
|
| 1599 |
|
|
printf OUTFILE "rty <= %s_rty_o",$slave[$i]{"wbs"};
|
| 1600 |
|
|
for ($j=$i+1; $j le $slaves; $j++) {
|
| 1601 |
|
|
if ($slave[$j]{"rty_o"} eq 1) {
|
| 1602 |
|
|
printf OUTFILE " or %s_rty_o",$slave[$j]{"wbs"};
|
| 1603 |
|
|
};
|
| 1604 |
|
|
};
|
| 1605 |
|
|
printf OUTFILE ";\n";
|
| 1606 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1607 |
|
|
if ($master[$i]{"rty_i"} eq 1) {
|
| 1608 |
|
|
printf OUTFILE "%s_rty_i <= rty;\n",$master[$i]{"wbm"};
|
| 1609 |
|
|
};
|
| 1610 |
|
|
};
|
| 1611 |
|
|
};
|
| 1612 |
|
|
# err
|
| 1613 |
|
|
if (($err_o eq 0) && ($err_i gt 0)) {
|
| 1614 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1615 |
|
|
if ($master[$i]{"err_i"} eq 1) {
|
| 1616 |
|
|
printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
|
| 1617 |
|
|
};
|
| 1618 |
|
|
};
|
| 1619 |
|
|
} elsif (($err_o eq 1) && ($err_i gt 0)) {
|
| 1620 |
|
|
$i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
|
| 1621 |
|
|
for ($j=1; $j le $masters; $j++) {
|
| 1622 |
|
|
if ($master[$j]{"err_i"} eq 1) {
|
| 1623 |
|
|
printf OUTFILE "%s_err_i <= %s_err_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1624 |
|
|
};
|
| 1625 |
|
|
};
|
| 1626 |
|
|
} elsif (($err_o gt 1) && ($err_i gt 0)) {
|
| 1627 |
|
|
$i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
|
| 1628 |
|
|
printf OUTFILE "err <= %s_err_o",$slave[$i]{"wbs"};
|
| 1629 |
|
|
for ($j=$i+1; $j le $slaves; $j++) {
|
| 1630 |
|
|
if ($slave[$j]{"err_o"} eq 1) {
|
| 1631 |
|
|
printf OUTFILE " or %s_err_o",$slave[$j]{"wbs"};
|
| 1632 |
|
|
};
|
| 1633 |
|
|
};
|
| 1634 |
|
|
printf OUTFILE ";\n";
|
| 1635 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1636 |
|
|
if ($master[$i]{"err_i"} eq 1) {
|
| 1637 |
|
|
printf OUTFILE "%s_err_i <= err;\n",$master[$i]{"wbm"};
|
| 1638 |
|
|
};
|
| 1639 |
|
|
};
|
| 1640 |
|
|
};
|
| 1641 |
|
|
# sel
|
| 1642 |
|
|
printf OUTFILE "sel <= (%s_sel_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
| 1643 |
|
|
if ($masters gt 1) {
|
| 1644 |
|
|
for ($i=2; $i le $masters; $i++) {
|
| 1645 |
|
|
printf OUTFILE " or (%s_sel_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1646 |
|
|
};
|
| 1647 |
|
|
};
|
| 1648 |
|
|
printf OUTFILE ";\n";
|
| 1649 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1650 |
|
|
printf OUTFILE "%s_sel_i <= sel;\n",$slave[$i]{"wbs"}; };
|
| 1651 |
|
|
# data m2s
|
| 1652 |
|
|
$i=1; until ($master[$i]{"type"} ne "ro") {$i++};
|
| 1653 |
|
|
printf OUTFILE "dat_m2s <= (%s_dat_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1654 |
|
|
if ($i lt $masters) {
|
| 1655 |
|
|
for ($j=$i+1; $j le $masters; $j++) {
|
| 1656 |
|
|
printf OUTFILE " or (%s_dat_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
|
| 1657 |
|
|
};
|
| 1658 |
|
|
};
|
| 1659 |
|
|
printf OUTFILE ";\n";
|
| 1660 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1661 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 1662 |
|
|
printf OUTFILE "%s_dat_i <= dat_m2s;\n",$slave[$i]{"wbs"};
|
| 1663 |
|
|
};
|
| 1664 |
|
|
};
|
| 1665 |
|
|
# data s2m
|
| 1666 |
|
|
$i=1; until ($slave[$i]{"type"} ne "wo") {$i++};
|
| 1667 |
|
|
printf OUTFILE "dat_s2m <= (%s_dat_o and %s_ss)",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1668 |
|
|
if ($i lt $slaves) {
|
| 1669 |
|
|
for ($j=$i+1; $j le $slaves; $j++) {
|
| 1670 |
|
|
printf OUTFILE " or (%s_dat_o and %s_ss)",$slave[$j]{"wbs"},$slave[$j]{"wbs"};
|
| 1671 |
|
|
};
|
| 1672 |
|
|
};
|
| 1673 |
|
|
printf OUTFILE ";\n";
|
| 1674 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1675 |
|
|
if ($master[$i]{"type"} ne "wo") {
|
| 1676 |
|
|
printf OUTFILE "%s_dat_i <= dat_s2m;\n",$master[$i]{"wbm"};
|
| 1677 |
|
|
};
|
| 1678 |
|
|
};
|
| 1679 |
|
|
# tgc
|
| 1680 |
|
|
if (($tgc_o eq 0) && ($tgc_i gt 0)) {
|
| 1681 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1682 |
|
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
| 1683 |
|
|
printf OUTFILE "%s_%s_i <= %s;\n",$slave[$i]{"wbs"},$rename_tgc,$classic;
|
| 1684 |
|
|
};
|
| 1685 |
|
|
};
|
| 1686 |
|
|
} elsif (($tgc_o gt 0) && ($tgc_i gt 0)) {
|
| 1687 |
|
|
$i=1; until ($master[$i]{"tgc_o"} eq 1) {$i++};
|
| 1688 |
|
|
printf OUTFILE "tgc <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"};
|
| 1689 |
|
|
for ($j=$i+1; $j le $masters; $j++) {
|
| 1690 |
|
|
if ($master[$j]{"tgc_o"} eq 1) {
|
| 1691 |
|
|
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"};
|
| 1692 |
|
|
};
|
| 1693 |
|
|
};
|
| 1694 |
|
|
printf OUTFILE ";\n";
|
| 1695 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1696 |
|
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
| 1697 |
|
|
printf OUTFILE "%s_%s_i <= tgc;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"};
|
| 1698 |
|
|
};
|
| 1699 |
|
|
};
|
| 1700 |
|
|
};
|
| 1701 |
|
|
# tga
|
| 1702 |
|
|
if (($tga_o eq 0) && ($tga_i gt 0)) {
|
| 1703 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1704 |
|
|
if ($slave[$i]{"tga_i"} eq 1) {
|
| 1705 |
|
|
printf OUTFILE "%s_%s_i <= (others=>'0');\n",$slave[$i]{"wbs"},$rename_tga;
|
| 1706 |
|
|
};
|
| 1707 |
|
|
};
|
| 1708 |
|
|
} elsif (($tga_o gt 0) && ($tga_i gt 0)) {
|
| 1709 |
|
|
$i=1; until ($master[$i]{"tga_o"} eq 1) {$i++};
|
| 1710 |
|
|
printf OUTFILE "tga <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"};
|
| 1711 |
|
|
for ($j=$i+1; $j le $masters; $j++) {
|
| 1712 |
|
|
if ($master[$j]{"tga_o"} eq 1) {
|
| 1713 |
|
|
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"};
|
| 1714 |
|
|
};
|
| 1715 |
|
|
};
|
| 1716 |
|
|
printf OUTFILE ";\n";
|
| 1717 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1718 |
|
|
if ($slave[$i]{"tga_i"} eq 1) {
|
| 1719 |
|
|
printf OUTFILE "%s_%s_i <= tga;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"};
|
| 1720 |
|
|
};
|
| 1721 |
|
|
};
|
| 1722 |
|
|
};
|
| 1723 |
|
|
# end block
|
| 1724 |
|
|
printf OUTFILE "end block mux;\n\n";
|
| 1725 |
|
|
};
|
| 1726 |
|
|
|
| 1727 |
|
|
sub gen_muxcbs{
|
| 1728 |
|
|
# cyc
|
| 1729 |
|
|
printf OUTFILE "-- cyc_i(s)\n";
|
| 1730 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1731 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
| 1732 |
|
|
printf OUTFILE "%s_cyc_i <= (%s_cyc_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
| 1733 |
|
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
| 1734 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1735 |
|
|
printf OUTFILE " or (%s_cyc_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1736 |
|
|
};
|
| 1737 |
|
|
};
|
| 1738 |
|
|
printf OUTFILE ";\n";
|
| 1739 |
|
|
};
|
| 1740 |
|
|
# stb
|
| 1741 |
|
|
printf OUTFILE "-- stb_i(s)\n";
|
| 1742 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1743 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
| 1744 |
|
|
printf OUTFILE "%s_stb_i <= (%s_stb_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
| 1745 |
|
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
| 1746 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1747 |
|
|
printf OUTFILE " or (%s_stb_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1748 |
|
|
};
|
| 1749 |
|
|
};
|
| 1750 |
|
|
printf OUTFILE ";\n";
|
| 1751 |
|
|
};
|
| 1752 |
|
|
# we
|
| 1753 |
|
|
printf OUTFILE "-- we_i(s)\n";
|
| 1754 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1755 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 1756 |
|
|
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
|
| 1757 |
|
|
printf OUTFILE "%s_we_i <= (%s_we_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
| 1758 |
|
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
| 1759 |
|
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
| 1760 |
|
|
printf OUTFILE " or (%s_we_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1761 |
|
|
};
|
| 1762 |
|
|
};
|
| 1763 |
|
|
printf OUTFILE ";\n";
|
| 1764 |
|
|
};
|
| 1765 |
|
|
};
|
| 1766 |
|
|
# ack
|
| 1767 |
|
|
printf OUTFILE "-- ack_i(s)\n";
|
| 1768 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1769 |
|
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
| 1770 |
|
|
printf OUTFILE "%s_ack_i <= (%s_ack_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
| 1771 |
|
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
| 1772 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1773 |
|
|
printf OUTFILE " or (%s_ack_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1774 |
|
|
};
|
| 1775 |
|
|
};
|
| 1776 |
|
|
printf OUTFILE ";\n";
|
| 1777 |
|
|
};
|
| 1778 |
|
|
# rty
|
| 1779 |
|
|
printf OUTFILE "-- rty_i(s)\n";
|
| 1780 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1781 |
|
|
if ($master[$i]{"rty_i"} eq 1) {
|
| 1782 |
|
|
$rty_o=0;
|
| 1783 |
|
|
for ($j=1; $j le $masters; $j++) {
|
| 1784 |
|
|
if (($slave[$j]{"rty_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
|
| 1785 |
|
|
$rty_o+=1;
|
| 1786 |
|
|
};
|
| 1787 |
|
|
};
|
| 1788 |
|
|
if ($rty_o eq 0) {
|
| 1789 |
|
|
printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
|
| 1790 |
|
|
} else {
|
| 1791 |
8 |
unneback |
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
| 1792 |
2 |
unneback |
printf OUTFILE "%s_rty_i <= (%s_rty_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
| 1793 |
|
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
| 1794 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1795 |
|
|
printf OUTFILE " or (%s_rty_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1796 |
|
|
};
|
| 1797 |
|
|
};
|
| 1798 |
|
|
printf OUTFILE ";\n";
|
| 1799 |
|
|
};
|
| 1800 |
|
|
};
|
| 1801 |
|
|
};
|
| 1802 |
|
|
# err
|
| 1803 |
|
|
printf OUTFILE "-- err_i(s)\n";
|
| 1804 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1805 |
|
|
if ($master[$i]{"err_i"} eq 1) {
|
| 1806 |
8 |
unneback |
$err_o=0;
|
| 1807 |
2 |
unneback |
for ($j=1; $j le $masters; $j++) {
|
| 1808 |
|
|
if (($slave[$j]{"err_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
|
| 1809 |
|
|
$err_o+=1;
|
| 1810 |
|
|
};
|
| 1811 |
|
|
};
|
| 1812 |
|
|
if ($err_o eq 0) {
|
| 1813 |
|
|
printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
|
| 1814 |
|
|
} else {
|
| 1815 |
8 |
unneback |
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
| 1816 |
2 |
unneback |
printf OUTFILE "%s_err_i <= (%s_err_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
| 1817 |
|
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
| 1818 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1819 |
|
|
printf OUTFILE " or (%s_err_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1820 |
|
|
};
|
| 1821 |
|
|
};
|
| 1822 |
|
|
printf OUTFILE ";\n";
|
| 1823 |
|
|
};
|
| 1824 |
|
|
};
|
| 1825 |
|
|
};
|
| 1826 |
|
|
# sel
|
| 1827 |
|
|
printf OUTFILE "-- sel_i(s)\n";
|
| 1828 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1829 |
|
|
if ($dat_size >= 16) {
|
| 1830 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
| 1831 |
|
|
printf OUTFILE "%s_sel_i <= (%s_sel_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
| 1832 |
|
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
| 1833 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1834 |
|
|
printf OUTFILE " or (%s_sel_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1835 |
|
|
};
|
| 1836 |
|
|
};
|
| 1837 |
|
|
printf OUTFILE ";\n";
|
| 1838 |
|
|
};
|
| 1839 |
|
|
};
|
| 1840 |
|
|
# dat
|
| 1841 |
|
|
printf OUTFILE "-- slave dat_i(s)\n";
|
| 1842 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1843 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 1844 |
|
|
$tmp=0;
|
| 1845 |
|
|
for ($j=1; $j le $masters; $j++) {
|
| 1846 |
|
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
| 1847 |
|
|
$tmp+=1;
|
| 1848 |
|
|
};
|
| 1849 |
|
|
};
|
| 1850 |
|
|
if ($tmp eq 1) {
|
| 1851 |
|
|
$j=1; until (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {$j++};
|
| 1852 |
|
|
printf OUTFILE "%s_dat_i <= %s_dat_o;\n",$slave[$i]{"wbs"},$master[$j]{"wbm"};
|
| 1853 |
|
|
} elsif ($tmp >= 1) {
|
| 1854 |
|
|
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
|
| 1855 |
|
|
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
| 1856 |
|
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
| 1857 |
|
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
| 1858 |
|
|
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1859 |
|
|
};
|
| 1860 |
|
|
};
|
| 1861 |
|
|
printf OUTFILE ";\n";
|
| 1862 |
|
|
};
|
| 1863 |
|
|
};
|
| 1864 |
|
|
};
|
| 1865 |
|
|
printf OUTFILE "-- master dat_i(s)\n";
|
| 1866 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1867 |
|
|
if ($master[$i]{"type"} ne "wo") {
|
| 1868 |
|
|
$tmp=0;
|
| 1869 |
|
|
for ($j=1; $j le $slaves; $j++) {
|
| 1870 |
|
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
| 1871 |
|
|
$tmp+=1;
|
| 1872 |
|
|
};
|
| 1873 |
|
|
};
|
| 1874 |
|
|
if ($tmp eq 1) {
|
| 1875 |
|
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
| 1876 |
|
|
printf OUTFILE "%s_dat_i <= %s_dat_o",$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
| 1877 |
|
|
} else {
|
| 1878 |
|
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
| 1879 |
|
|
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
| 1880 |
|
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
| 1881 |
4 |
unneback |
if (($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) && ($master[$i]{"type"} ne "wo")) {
|
| 1882 |
2 |
unneback |
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
| 1883 |
|
|
};
|
| 1884 |
|
|
};
|
| 1885 |
|
|
};
|
| 1886 |
|
|
printf OUTFILE ";\n";
|
| 1887 |
|
|
};
|
| 1888 |
|
|
};
|
| 1889 |
|
|
# tgc
|
| 1890 |
|
|
printf OUTFILE "-- tgc_i\n";
|
| 1891 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1892 |
|
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
| 1893 |
|
|
$tmp=0;
|
| 1894 |
|
|
for ($j=1; $j le $masters; $j++) {
|
| 1895 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1896 |
|
|
$tmp+=1;
|
| 1897 |
|
|
};
|
| 1898 |
|
|
};
|
| 1899 |
|
|
if ($tmp eq 1) {
|
| 1900 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
| 1901 |
|
|
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc;
|
| 1902 |
|
|
} else {
|
| 1903 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
| 1904 |
4 |
unneback |
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
| 1905 |
2 |
unneback |
for ($j=$tmp+1; $j le $masters; $j++) {
|
| 1906 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1907 |
5 |
unneback |
if ($master[$j]{"tga_o"} eq 1) {
|
| 1908 |
6 |
unneback |
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1909 |
5 |
unneback |
} else {
|
| 1910 |
6 |
unneback |
if ($classic ne "000") {
|
| 1911 |
|
|
printf OUTFILE " or \"%s\"",$classic;
|
| 1912 |
|
|
};
|
| 1913 |
5 |
unneback |
};
|
| 1914 |
|
|
|
| 1915 |
2 |
unneback |
};
|
| 1916 |
|
|
};
|
| 1917 |
|
|
};
|
| 1918 |
|
|
printf OUTFILE ";\n";
|
| 1919 |
|
|
};
|
| 1920 |
|
|
};
|
| 1921 |
|
|
# tga
|
| 1922 |
|
|
printf OUTFILE "-- tga_i\n";
|
| 1923 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1924 |
|
|
if ($slave[$i]{"tga_i"} eq 1) {
|
| 1925 |
|
|
$tmp=0;
|
| 1926 |
|
|
for ($j=1; $j le $masters; $j++) {
|
| 1927 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1928 |
|
|
$tmp+=1;
|
| 1929 |
|
|
};
|
| 1930 |
|
|
};
|
| 1931 |
|
|
if ($tmp eq 1) {
|
| 1932 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
| 1933 |
|
|
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga;
|
| 1934 |
|
|
} else {
|
| 1935 |
|
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
| 1936 |
9 |
unneback |
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
| 1937 |
2 |
unneback |
for ($j=$tmp+1; $j le $masters; $j++) {
|
| 1938 |
|
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
| 1939 |
5 |
unneback |
if ($master[$j]{"tga_o"} eq 1) {
|
| 1940 |
|
|
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
| 1941 |
|
|
};
|
| 1942 |
2 |
unneback |
};
|
| 1943 |
|
|
};
|
| 1944 |
|
|
};
|
| 1945 |
|
|
printf OUTFILE ";\n";
|
| 1946 |
|
|
};
|
| 1947 |
|
|
};
|
| 1948 |
|
|
};
|
| 1949 |
|
|
|
| 1950 |
|
|
sub gen_remap{
|
| 1951 |
|
|
for ($i=1; $i le $masters; $i++) {
|
| 1952 |
|
|
if ($master[$i]{"type"} ne "wo") {
|
| 1953 |
|
|
printf OUTFILE "%s_wbm_i.dat_i <= %s_dat_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1954 |
|
|
printf OUTFILE "%s_wbm_i.ack_i <= %s_ack_i ;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1955 |
|
|
if ($master[$i]{"err_i"} eq 1) {
|
| 1956 |
|
|
printf OUTFILE "%s_wbm_i.err_i <= %s_err_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1957 |
|
|
if ($master[$i]{"rty_i"} eq 1) {
|
| 1958 |
|
|
printf OUTFILE "%s_wbm_i.rty_i <= %s_rty_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
| 1959 |
|
|
if ($master[$i]{"type"} ne "ro") {
|
| 1960 |
|
|
printf OUTFILE "%s_dat_o <= %s_wbm_o.dat_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1961 |
|
|
printf OUTFILE "%s_we_o <= %s_wbm_o.we_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1962 |
|
|
};
|
| 1963 |
|
|
printf OUTFILE "%s_sel_o <= %s_wbm_o.sel_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1964 |
|
|
printf OUTFILE "%s_adr_o <= %s_wbm_o.adr_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1965 |
|
|
if ($master[$i]{"tgc_o"} eq 1) {
|
| 1966 |
|
|
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"},$rename_tgc; };
|
| 1967 |
|
|
if ($master[$i]{"tga_o"} eq 1) {
|
| 1968 |
|
|
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"},$rename_tga; };
|
| 1969 |
|
|
printf OUTFILE "%s_cyc_o <= %s_wbm_o.cyc_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1970 |
|
|
printf OUTFILE "%s_stb_o <= %s_wbm_o.stb_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
| 1971 |
|
|
};
|
| 1972 |
|
|
for ($i=1; $i le $slaves; $i++) {
|
| 1973 |
|
|
if ($slave[$i]{"type"} ne "wo") {
|
| 1974 |
|
|
printf OUTFILE "%s_dat_o <= %s_wbs_o.dat_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
| 1975 |
|
|
printf OUTFILE "%s_ack_o <= %s_wbs_o.ack_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1976 |
|
|
if ($slave[$i]{"err_o"} eq 1) {
|
| 1977 |
|
|
printf OUTFILE "%s_err_o <= %s_wbs_o.err_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
| 1978 |
|
|
if ($slave[$i]{"rty_o"} eq 1) {
|
| 1979 |
|
|
printf OUTFILE "%s_rty_o <= %s_wbs_o.rty_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
| 1980 |
|
|
if ($slave[$i]{"type"} ne "ro") {
|
| 1981 |
|
|
printf OUTFILE "%s_wbs_i.dat_i <= %s_dat_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1982 |
|
|
printf OUTFILE "%s_wbs_i.we_i <= %s_we_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1983 |
|
|
};
|
| 1984 |
|
|
printf OUTFILE "%s_wbs_i.sel_i <= %s_sel_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1985 |
|
|
printf OUTFILE "%s_wbs_i.adr_i <= %s_adr_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1986 |
|
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
| 1987 |
|
|
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"},$rename_tgc; };
|
| 1988 |
|
|
if ($slave[$i]{"tga_i"} eq 1) {
|
| 1989 |
|
|
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"},$rename_tga; };
|
| 1990 |
|
|
printf OUTFILE "%s_wbs_i.cyc_i <= %s_cyc_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1991 |
|
|
printf OUTFILE "%s_wbs_i.stb_i <= %s_stb_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
| 1992 |
|
|
};
|
| 1993 |
|
|
};
|
| 1994 |
|
|
|
| 1995 |
|
|
# GUI
|
| 1996 |
|
|
$tmp=shift;
|
| 1997 |
|
|
if ($tmp eq "-nogui") {
|
| 1998 |
|
|
$infile = shift;
|
| 1999 |
|
|
read_defines($infile);
|
| 2000 |
|
|
} else {
|
| 2001 |
|
|
if ($tmp ne <undef>) {
|
| 2002 |
|
|
$infile=$tmp;
|
| 2003 |
|
|
read_defines($infile);
|
| 2004 |
|
|
};
|
| 2005 |
|
|
gui_fsm;
|
| 2006 |
|
|
generate_defines($infile);
|
| 2007 |
14 |
unneback |
read_defines($infile);
|
| 2008 |
2 |
unneback |
};
|
| 2009 |
|
|
|
| 2010 |
|
|
# main
|
| 2011 |
|
|
open(OUTFILE,">$outfile$ext") or die "could not write to $outfile$ext";
|
| 2012 |
|
|
gen_header;
|
| 2013 |
|
|
if ($hdl eq 'vhdl') {
|
| 2014 |
|
|
gen_vhdl_package;
|
| 2015 |
|
|
gen_trafic_ctrl;
|
| 2016 |
|
|
gen_entity;
|
| 2017 |
|
|
printf OUTFILE "architecture rtl of %s is\n",$intercon;
|
| 2018 |
|
|
if ($signal_groups == 1) { gen_sig_remap; };
|
| 2019 |
|
|
gen_global_signals;
|
| 2020 |
|
|
printf OUTFILE "begin -- rtl\n";
|
| 2021 |
|
|
gen_arbiter;
|
| 2022 |
|
|
gen_adr_decoder;
|
| 2023 |
|
|
if ($interconnect eq 'sharedbus') {
|
| 2024 |
|
|
gen_muxshb;
|
| 2025 |
|
|
} else {
|
| 2026 |
|
|
gen_muxcbs;
|
| 2027 |
|
|
};
|
| 2028 |
|
|
if ($signal_groups == 1) { gen_remap; };
|
| 2029 |
|
|
printf OUTFILE "end rtl;";
|
| 2030 |
|
|
} else {
|
| 2031 |
|
|
|
| 2032 |
|
|
};
|
| 2033 |
|
|
close(OUTFILE);
|
