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[/] [wb_builder/] [trunk/] [rtl/] [vhdl/] [wb.vhd] - Blame information for rev 8

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1 2 unneback 
-- Generated by PERL program wishbone.pl. Do not edit this file.
2 
--
3 
-- For defines see wishbone.defines
4 
--
5 8 unneback 
-- Generated Thu Jun 24 14:29:34 2004
6 2 unneback 
--
7 
-- Wishbone masters:
8 
--   or32_i
9 
--   or32_d
10 8 unneback 
--   debug
11 
--   ethernetm
12 2 unneback 
--
13 
-- Wishbone slaves:
14 
--   uart
15 8 unneback 
--     baseadr 0x90000000 - size 0x01000000
16 
--   sdram_ctrl1
17 
--     baseadr 0x00000000 - size 0x10000000
18 
--   sdram_ctrl2
19 
--     baseadr 0x10000000 - size 0x10000000
20 2 unneback 
--   bootRAM
21 8 unneback 
--     baseadr 0xf0000000 - size 0x10000000
22 
--   ethernets
23 
--     baseadr 0x92000000 - size 0x01000000
24 2 unneback 
-----------------------------------------------------------------------------------------
25 
library IEEE;
26 
use IEEE.std_logic_1164.all;
27 
 
28 
package intercon_package is
29 
 
30 
type or32_i_wbm_i_type is record
31 
  dat_i : std_logic_vector(31 downto 0);
32 
  err_i : std_logic;
33 
  rty_i : std_logic;
34 
  ack_i : std_logic;
35 
end record;
36 
type or32_i_wbm_o_type is record
37 
  sel_o : std_logic_vector(3 downto 0);
38 
  adr_o : std_logic_vector(31 downto 0);
39 
  bte_o : std_logic_vector(1 downto 0);
40 
  cti_o : std_logic_vector(2 downto 0);
41 
  cyc_o : std_logic;
42 
  stb_o : std_logic;
43 
end record;
44 
 
45 
type or32_d_wbm_i_type is record
46 
  dat_i : std_logic_vector(31 downto 0);
47 
  err_i : std_logic;
48 
  rty_i : std_logic;
49 
  ack_i : std_logic;
50 
end record;
51 
type or32_d_wbm_o_type is record
52 
  dat_o : std_logic_vector(31 downto 0);
53 
  we_o  : std_logic;
54 
  sel_o : std_logic_vector(3 downto 0);
55 
  adr_o : std_logic_vector(31 downto 0);
56 
  bte_o : std_logic_vector(1 downto 0);
57 
  cti_o : std_logic_vector(2 downto 0);
58 
  cyc_o : std_logic;
59 
  stb_o : std_logic;
60 
end record;
61 
 
62 8 unneback 
type debug_wbm_i_type is record
63 
  dat_i : std_logic_vector(31 downto 0);
64 
  err_i : std_logic;
65 
  rty_i : std_logic;
66 
  ack_i : std_logic;
67 
end record;
68 
type debug_wbm_o_type is record
69 
  dat_o : std_logic_vector(31 downto 0);
70 
  we_o  : std_logic;
71 
  sel_o : std_logic_vector(3 downto 0);
72 
  adr_o : std_logic_vector(31 downto 0);
73 
  cyc_o : std_logic;
74 
  stb_o : std_logic;
75 
end record;
76 
 
77 
type ethernetm_wbm_i_type is record
78 
  dat_i : std_logic_vector(31 downto 0);
79 
  err_i : std_logic;
80 
  ack_i : std_logic;
81 
end record;
82 
type ethernetm_wbm_o_type is record
83 
  dat_o : std_logic_vector(31 downto 0);
84 
  we_o  : std_logic;
85 
  sel_o : std_logic_vector(3 downto 0);
86 
  adr_o : std_logic_vector(31 downto 0);
87 
  bte_o : std_logic_vector(1 downto 0);
88 
  cti_o : std_logic_vector(2 downto 0);
89 
  cyc_o : std_logic;
90 
  stb_o : std_logic;
91 
end record;
92 
 
93 2 unneback 
type uart_wbs_i_type is record
94 
  dat_i : std_logic_vector(31 downto 0);
95 
  we_i  : std_logic;
96 
  sel_i : std_logic_vector(3 downto 0);
97 
  adr_i : std_logic_vector(4 downto 0);
98 
  cyc_i : std_logic;
99 
  stb_i : std_logic;
100 
end record;
101 
type uart_wbs_o_type is record
102 
  dat_o : std_logic_vector(31 downto 0);
103 
  ack_o : std_logic;
104 
end record;
105 8 unneback 
type sdram_ctrl1_wbs_i_type is record
106 2 unneback 
  dat_i : std_logic_vector(31 downto 0);
107 
  we_i  : std_logic;
108 
  sel_i : std_logic_vector(3 downto 0);
109 8 unneback 
  adr_i : std_logic_vector(23 downto 2);
110 
  cti_i : std_logic_vector(2 downto 0);
111 
  cyc_i : std_logic;
112 
  stb_i : std_logic;
113 
end record;
114 
type sdram_ctrl1_wbs_o_type is record
115 
  dat_o : std_logic_vector(31 downto 0);
116 
  ack_o : std_logic;
117 
end record;
118 
type sdram_ctrl2_wbs_i_type is record
119 
  dat_i : std_logic_vector(31 downto 0);
120 
  we_i  : std_logic;
121 
  sel_i : std_logic_vector(3 downto 0);
122 
  adr_i : std_logic_vector(23 downto 2);
123 
  cti_i : std_logic_vector(2 downto 0);
124 
  cyc_i : std_logic;
125 
  stb_i : std_logic;
126 
end record;
127 
type sdram_ctrl2_wbs_o_type is record
128 
  dat_o : std_logic_vector(31 downto 0);
129 
  ack_o : std_logic;
130 
end record;
131 
type bootRAM_wbs_i_type is record
132 
  sel_i : std_logic_vector(3 downto 0);
133 2 unneback 
  adr_i : std_logic_vector(11 downto 2);
134 
  cyc_i : std_logic;
135 
  stb_i : std_logic;
136 
end record;
137 
type bootRAM_wbs_o_type is record
138 
  dat_o : std_logic_vector(31 downto 0);
139 
  ack_o : std_logic;
140 
end record;
141 8 unneback 
type ethernets_wbs_i_type is record
142 
  dat_i : std_logic_vector(31 downto 0);
143 
  we_i  : std_logic;
144 
  sel_i : std_logic_vector(3 downto 0);
145 
  adr_i : std_logic_vector(11 downto 2);
146 
  cyc_i : std_logic;
147 
  stb_i : std_logic;
148 
end record;
149 
type ethernets_wbs_o_type is record
150 
  dat_o : std_logic_vector(31 downto 0);
151 
  err_o : std_logic;
152 
  ack_o : std_logic;
153 
end record;
154 2 unneback 
 
155 
function "and" (
156 
  l : std_logic_vector;
157 
  r : std_logic)
158 
return std_logic_vector;
159 
end intercon_package;
160 
package body intercon_package is
161 
 
162 
function "and" (
163 
  l : std_logic_vector;
164 
  r : std_logic)
165 
return std_logic_vector is
166 
  variable result : std_logic_vector(l'range);
167 
begin  -- "and"
168 
  for i in l'range loop
169 
  result(i) := l(i) and r;
170 
end loop;  -- i
171 
return result;
172 
end "and";
173 
end intercon_package;
174 
library IEEE;
175 
use IEEE.std_logic_1164.all;
176 
 
177 
entity trafic_supervision is
178 
 
179 
  generic (
180 
    priority     : integer;
181 
    tot_priority : integer);
182 
 
183 
  port (
184 
    bg           : in  std_logic;       -- bus grant
185 
    ce           : in  std_logic;       -- clock enable
186 
    trafic_limit : out std_logic;
187 
    clk          : in  std_logic;
188 
    reset        : in  std_logic);
189 
 
190 
end trafic_supervision;
191 
 
192 
architecture rtl of trafic_supervision is
193 
 
194 
  signal shreg : std_logic_vector(tot_priority-1 downto 0);
195 
  signal cntr : integer range 0 to tot_priority;
196 
 
197 
begin  -- rtl
198 
 
199 
  -- purpose: holds information of usage of latest cycles
200 
  -- type   : sequential
201 
  -- inputs : clk, reset, ce, bg
202 
  -- outputs: shreg('left)
203 
  sh_reg: process (clk,reset)
204 
  begin  -- process shreg
205 
    if reset = '1' then                 -- asynchronous reset (active hi)
206 
      shreg <= (others=>'0');
207 
    elsif clk'event and clk = '1' then  -- rising clock edge
208 
      if ce='1' then
209 
        shreg <= shreg(tot_priority-2 downto 0) & bg;
210 
      end if;
211 
    end if;
212 
  end process sh_reg;
213 
 
214 
  -- purpose: keeps track of used cycles
215 
  -- type   : sequential
216 
  -- inputs : clk, reset, shreg('left), bg, ce
217 
  -- outputs: trafic_limit
218 
  counter: process (clk, reset)
219 
  begin  -- process counter
220 
    if reset = '1' then                 -- asynchronous reset (active hi)
221 
      cntr <= 0;
222 
      trafic_limit <= '0';
223 
    elsif clk'event and clk = '1' then  -- rising clock edge
224 
      if ce='1' then
225 
        if bg='1' and shreg(tot_priority-1)='0' then
226 
          cntr <= cntr + 1;
227 
          if cntr=priority-1 then
228 
            trafic_limit <= '1';
229 
          end if;
230 
        elsif bg='0' and shreg(tot_priority-1)='1' then
231 
          cntr <= cntr - 1;
232 
          if cntr=priority then
233 
            trafic_limit <= '0';
234 
          end if;
235 
        end if;
236 
      end if;
237 
    end if;
238 
  end process counter;
239 
 
240 
end rtl;
241 
 
242 
library IEEE;
243 
use IEEE.std_logic_1164.all;
244 
use work.intercon_package.all;
245 
 
246 
entity intercon is
247 
  port (
248 
  -- wishbone master port(s)
249 
  -- or32_i
250 
  or32_i_wbm_i : out or32_i_wbm_i_type;
251 
  or32_i_wbm_o : in  or32_i_wbm_o_type;
252 
  -- or32_d
253 
  or32_d_wbm_i : out or32_d_wbm_i_type;
254 
  or32_d_wbm_o : in  or32_d_wbm_o_type;
255 8 unneback 
  -- debug
256 
  debug_wbm_i : out debug_wbm_i_type;
257 
  debug_wbm_o : in  debug_wbm_o_type;
258 
  -- ethernetm
259 
  ethernetm_wbm_i : out ethernetm_wbm_i_type;
260 
  ethernetm_wbm_o : in  ethernetm_wbm_o_type;
261 2 unneback 
  -- wishbone slave port(s)
262 
  -- uart
263 
  uart_wbs_i : out uart_wbs_i_type;
264 
  uart_wbs_o : in uart_wbs_o_type;
265 8 unneback 
  -- sdram_ctrl1
266 
  sdram_ctrl1_wbs_i : out sdram_ctrl1_wbs_i_type;
267 
  sdram_ctrl1_wbs_o : in sdram_ctrl1_wbs_o_type;
268 
  -- sdram_ctrl2
269 
  sdram_ctrl2_wbs_i : out sdram_ctrl2_wbs_i_type;
270 
  sdram_ctrl2_wbs_o : in sdram_ctrl2_wbs_o_type;
271 2 unneback 
  -- bootRAM
272 
  bootRAM_wbs_i : out bootRAM_wbs_i_type;
273 
  bootRAM_wbs_o : in bootRAM_wbs_o_type;
274 8 unneback 
  -- ethernets
275 
  ethernets_wbs_i : out ethernets_wbs_i_type;
276 
  ethernets_wbs_o : in ethernets_wbs_o_type;
277 2 unneback 
  -- clock and reset
278 
  clk   : in std_logic;
279 
  reset : in std_logic);
280 
end intercon;
281 
architecture rtl of intercon is
282 
  signal or32_i_dat_i : std_logic_vector(31 downto 0);
283 
  signal or32_i_ack_i : std_logic;
284 
  signal or32_i_err_i : std_logic;
285 
  signal or32_i_rty_i : std_logic;
286 
  signal or32_i_sel_o : std_logic_vector(3 downto 0);
287 
  signal or32_i_adr_o : std_logic_vector(31 downto 0);
288 
  signal or32_i_bte_o : std_logic_vector(1 downto 0);
289 
  signal or32_i_cti_o : std_logic_vector(2 downto 0);
290 
  signal or32_i_cyc_o : std_logic;
291 
  signal or32_i_stb_o : std_logic;
292 
  signal or32_d_dat_i : std_logic_vector(31 downto 0);
293 
  signal or32_d_ack_i : std_logic;
294 
  signal or32_d_err_i : std_logic;
295 
  signal or32_d_rty_i : std_logic;
296 
  signal or32_d_dat_o : std_logic_vector(31 downto 0);
297 
  signal or32_d_we_o  : std_logic;
298 
  signal or32_d_sel_o : std_logic_vector(3 downto 0);
299 
  signal or32_d_adr_o : std_logic_vector(31 downto 0);
300 
  signal or32_d_bte_o : std_logic_vector(1 downto 0);
301 
  signal or32_d_cti_o : std_logic_vector(2 downto 0);
302 
  signal or32_d_cyc_o : std_logic;
303 
  signal or32_d_stb_o : std_logic;
304 8 unneback 
  signal debug_dat_i : std_logic_vector(31 downto 0);
305 
  signal debug_ack_i : std_logic;
306 
  signal debug_err_i : std_logic;
307 
  signal debug_rty_i : std_logic;
308 
  signal debug_dat_o : std_logic_vector(31 downto 0);
309 
  signal debug_we_o  : std_logic;
310 
  signal debug_sel_o : std_logic_vector(3 downto 0);
311 
  signal debug_adr_o : std_logic_vector(31 downto 0);
312 
  signal debug_cyc_o : std_logic;
313 
  signal debug_stb_o : std_logic;
314 
  signal ethernetm_dat_i : std_logic_vector(31 downto 0);
315 
  signal ethernetm_ack_i : std_logic;
316 
  signal ethernetm_err_i : std_logic;
317 
  signal ethernetm_dat_o : std_logic_vector(31 downto 0);
318 
  signal ethernetm_we_o  : std_logic;
319 
  signal ethernetm_sel_o : std_logic_vector(3 downto 0);
320 
  signal ethernetm_adr_o : std_logic_vector(31 downto 0);
321 
  signal ethernetm_bte_o : std_logic_vector(1 downto 0);
322 
  signal ethernetm_cti_o : std_logic_vector(2 downto 0);
323 
  signal ethernetm_cyc_o : std_logic;
324 
  signal ethernetm_stb_o : std_logic;
325 2 unneback 
  signal uart_dat_o : std_logic_vector(31 downto 0);
326 
  signal uart_ack_o : std_logic;
327 
  signal uart_dat_i : std_logic_vector(31 downto 0);
328 
  signal uart_we_i  : std_logic;
329 
  signal uart_sel_i : std_logic_vector(3 downto 0);
330 
  signal uart_adr_i : std_logic_vector(4 downto 0);
331 
  signal uart_cyc_i : std_logic;
332 
  signal uart_stb_i : std_logic;
333 8 unneback 
  signal sdram_ctrl1_dat_o : std_logic_vector(31 downto 0);
334 
  signal sdram_ctrl1_ack_o : std_logic;
335 
  signal sdram_ctrl1_dat_i : std_logic_vector(31 downto 0);
336 
  signal sdram_ctrl1_we_i  : std_logic;
337 
  signal sdram_ctrl1_sel_i : std_logic_vector(3 downto 0);
338 
  signal sdram_ctrl1_adr_i : std_logic_vector(23 downto 2);
339 
  signal sdram_ctrl1_cti_i : std_logic_vector(2 downto 0);
340 
  signal sdram_ctrl1_cyc_i : std_logic;
341 
  signal sdram_ctrl1_stb_i : std_logic;
342 
  signal sdram_ctrl2_dat_o : std_logic_vector(31 downto 0);
343 
  signal sdram_ctrl2_ack_o : std_logic;
344 
  signal sdram_ctrl2_dat_i : std_logic_vector(31 downto 0);
345 
  signal sdram_ctrl2_we_i  : std_logic;
346 
  signal sdram_ctrl2_sel_i : std_logic_vector(3 downto 0);
347 
  signal sdram_ctrl2_adr_i : std_logic_vector(23 downto 2);
348 
  signal sdram_ctrl2_cti_i : std_logic_vector(2 downto 0);
349 
  signal sdram_ctrl2_cyc_i : std_logic;
350 
  signal sdram_ctrl2_stb_i : std_logic;
351 2 unneback 
  signal bootRAM_dat_o : std_logic_vector(31 downto 0);
352 
  signal bootRAM_ack_o : std_logic;
353 
  signal bootRAM_sel_i : std_logic_vector(3 downto 0);
354 
  signal bootRAM_adr_i : std_logic_vector(11 downto 2);
355 
  signal bootRAM_cyc_i : std_logic;
356 
  signal bootRAM_stb_i : std_logic;
357 8 unneback 
  signal ethernets_dat_o : std_logic_vector(31 downto 0);
358 
  signal ethernets_ack_o : std_logic;
359 
  signal ethernets_err_o : std_logic;
360 
  signal ethernets_dat_i : std_logic_vector(31 downto 0);
361 
  signal ethernets_we_i  : std_logic;
362 
  signal ethernets_sel_i : std_logic_vector(3 downto 0);
363 
  signal ethernets_adr_i : std_logic_vector(11 downto 2);
364 
  signal ethernets_cyc_i : std_logic;
365 
  signal ethernets_stb_i : std_logic;
366 
  signal or32_i_sdram_ctrl1_ss : std_logic; -- slave select
367 
  signal or32_i_sdram_ctrl1_bg : std_logic; -- bus grant
368 
  signal or32_i_sdram_ctrl2_ss : std_logic; -- slave select
369 
  signal or32_i_sdram_ctrl2_bg : std_logic; -- bus grant
370 2 unneback 
  signal or32_i_bootRAM_ss : std_logic; -- slave select
371 
  signal or32_i_bootRAM_bg : std_logic; -- bus grant
372 
  signal or32_d_uart_ss : std_logic; -- slave select
373 
  signal or32_d_uart_bg : std_logic; -- bus grant
374 8 unneback 
  signal or32_d_sdram_ctrl1_ss : std_logic; -- slave select
375 
  signal or32_d_sdram_ctrl1_bg : std_logic; -- bus grant
376 
  signal or32_d_sdram_ctrl2_ss : std_logic; -- slave select
377 
  signal or32_d_sdram_ctrl2_bg : std_logic; -- bus grant
378 2 unneback 
  signal or32_d_bootRAM_ss : std_logic; -- slave select
379 
  signal or32_d_bootRAM_bg : std_logic; -- bus grant
380 8 unneback 
  signal or32_d_ethernets_ss : std_logic; -- slave select
381 
  signal or32_d_ethernets_bg : std_logic; -- bus grant
382 
  signal debug_sdram_ctrl1_ss : std_logic; -- slave select
383 
  signal debug_sdram_ctrl1_bg : std_logic; -- bus grant
384 
  signal debug_sdram_ctrl2_ss : std_logic; -- slave select
385 
  signal debug_sdram_ctrl2_bg : std_logic; -- bus grant
386 
  signal debug_bootRAM_ss : std_logic; -- slave select
387 
  signal debug_bootRAM_bg : std_logic; -- bus grant
388 
  signal ethernetm_sdram_ctrl1_ss : std_logic; -- slave select
389 
  signal ethernetm_sdram_ctrl1_bg : std_logic; -- bus grant
390 
  signal ethernetm_sdram_ctrl2_ss : std_logic; -- slave select
391 
  signal ethernetm_sdram_ctrl2_bg : std_logic; -- bus grant
392 2 unneback 
begin  -- rtl
393 
or32_d_uart_bg <= or32_d_uart_ss and or32_d_cyc_o;
394 8 unneback 
arbiter_sdram_ctrl1 : block
395 
  signal or32_i_bg, or32_i_bg_1, or32_i_bg_2, or32_i_bg_q : std_logic;
396 
  signal or32_i_trafic_limit : std_logic;
397 
  signal or32_d_bg, or32_d_bg_1, or32_d_bg_2, or32_d_bg_q : std_logic;
398 
  signal or32_d_trafic_limit : std_logic;
399 
  signal debug_bg, debug_bg_1, debug_bg_2, debug_bg_q : std_logic;
400 
  signal debug_trafic_limit : std_logic;
401 
  signal ethernetm_bg, ethernetm_bg_1, ethernetm_bg_2, ethernetm_bg_q : std_logic;
402 
  signal ethernetm_trafic_limit : std_logic;
403 
  signal ce, idle, ack : std_logic;
404 
begin
405 
ack <= sdram_ctrl1_ack_o;
406 
 
407 
trafic_supervision_1 : entity work.trafic_supervision
408 
generic map(
409 
  priority => 3,
410 
  tot_priority => 6)
411 
port map(
412 
  bg => or32_i_sdram_ctrl1_bg,
413 
  ce => ce,
414 
  trafic_limit => or32_i_trafic_limit,
415 
  clk => clk,
416 
  reset => reset);
417 
 
418 
trafic_supervision_2 : entity work.trafic_supervision
419 
generic map(
420 
  priority => 1,
421 
  tot_priority => 6)
422 
port map(
423 
  bg => or32_d_sdram_ctrl1_bg,
424 
  ce => ce,
425 
  trafic_limit => or32_d_trafic_limit,
426 
  clk => clk,
427 
  reset => reset);
428 
 
429 
trafic_supervision_3 : entity work.trafic_supervision
430 
generic map(
431 
  priority => 1,
432 
  tot_priority => 6)
433 
port map(
434 
  bg => debug_sdram_ctrl1_bg,
435 
  ce => ce,
436 
  trafic_limit => debug_trafic_limit,
437 
  clk => clk,
438 
  reset => reset);
439 
 
440 
trafic_supervision_4 : entity work.trafic_supervision
441 
generic map(
442 
  priority => 1,
443 
  tot_priority => 6)
444 
port map(
445 
  bg => ethernetm_sdram_ctrl1_bg,
446 
  ce => ce,
447 
  trafic_limit => ethernetm_trafic_limit,
448 
  clk => clk,
449 
  reset => reset);
450 
 
451 
process(clk,reset)
452 
begin
453 
if reset='1' then
454 
  or32_i_bg_q <= '0';
455 
elsif clk'event and clk='1' then
456 
if or32_i_bg_q='0' then
457 
  or32_i_bg_q <= or32_i_bg;
458 
elsif ack='1' and (or32_i_cti_o="000" or or32_i_cti_o="111") then
459 
  or32_i_bg_q <= '0';
460 
end if;
461 
end if;
462 
end process;
463 
 
464 
process(clk,reset)
465 
begin
466 
if reset='1' then
467 
  or32_d_bg_q <= '0';
468 
elsif clk'event and clk='1' then
469 
if or32_d_bg_q='0' then
470 
  or32_d_bg_q <= or32_d_bg;
471 
elsif ack='1' and (or32_d_cti_o="000" or or32_d_cti_o="111") then
472 
  or32_d_bg_q <= '0';
473 
end if;
474 
end if;
475 
end process;
476 
 
477 
process(clk,reset)
478 
begin
479 
if reset='1' then
480 
  debug_bg_q <= '0';
481 
elsif clk'event and clk='1' then
482 
if debug_bg_q='0' then
483 
  debug_bg_q <= debug_bg;
484 
elsif ack='1' then
485 
  debug_bg_q <= '0';
486 
end if;
487 
end if;
488 
end process;
489 
 
490 
process(clk,reset)
491 
begin
492 
if reset='1' then
493 
  ethernetm_bg_q <= '0';
494 
elsif clk'event and clk='1' then
495 
if ethernetm_bg_q='0' then
496 
  ethernetm_bg_q <= ethernetm_bg;
497 
elsif ack='1' and (ethernetm_cti_o="000" or ethernetm_cti_o="111") then
498 
  ethernetm_bg_q <= '0';
499 
end if;
500 
end if;
501 
end process;
502 
 
503 
idle <= '1' when or32_i_bg_q='0' and or32_d_bg_q='0' and debug_bg_q='0' and ethernetm_bg_q='0' else '0';
504 
or32_i_bg_1 <= '1' when idle='1' and or32_i_cyc_o='1' and or32_i_sdram_ctrl1_ss='1' and or32_i_trafic_limit='0' else '0';
505 
or32_d_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl1_ss='1' and or32_d_trafic_limit='0' else '0';
506 
debug_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0') and debug_cyc_o='1' and debug_sdram_ctrl1_ss='1' and debug_trafic_limit='0' else '0';
507 
ethernetm_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl1_ss='1' and ethernetm_trafic_limit='0' else '0';
508 
or32_i_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0') and or32_i_cyc_o='1' and or32_i_sdram_ctrl1_ss='1' else '0';
509 
or32_d_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl1_ss='1' else '0';
510 
debug_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0') and debug_cyc_o='1' and debug_sdram_ctrl1_ss='1' else '0';
511 
ethernetm_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0' and debug_bg_2='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl1_ss='1' else '0';
512 
or32_i_bg <= or32_i_bg_q or or32_i_bg_1 or or32_i_bg_2;
513 
or32_d_bg <= or32_d_bg_q or or32_d_bg_1 or or32_d_bg_2;
514 
debug_bg <= debug_bg_q or debug_bg_1 or debug_bg_2;
515 
ethernetm_bg <= ethernetm_bg_q or ethernetm_bg_1 or ethernetm_bg_2;
516 
ce <= (or32_i_cyc_o and or32_i_sdram_ctrl1_ss) or (or32_d_cyc_o and or32_d_sdram_ctrl1_ss) or (debug_cyc_o and debug_sdram_ctrl1_ss) or (ethernetm_cyc_o and ethernetm_sdram_ctrl1_ss) when idle='1' else '0';
517 
or32_i_sdram_ctrl1_bg <= or32_i_bg;
518 
or32_d_sdram_ctrl1_bg <= or32_d_bg;
519 
debug_sdram_ctrl1_bg <= debug_bg;
520 
ethernetm_sdram_ctrl1_bg <= ethernetm_bg;
521 
end block arbiter_sdram_ctrl1;
522 
arbiter_sdram_ctrl2 : block
523 
  signal or32_i_bg, or32_i_bg_1, or32_i_bg_2, or32_i_bg_q : std_logic;
524 
  signal or32_i_trafic_limit : std_logic;
525 
  signal or32_d_bg, or32_d_bg_1, or32_d_bg_2, or32_d_bg_q : std_logic;
526 
  signal or32_d_trafic_limit : std_logic;
527 
  signal debug_bg, debug_bg_1, debug_bg_2, debug_bg_q : std_logic;
528 
  signal debug_trafic_limit : std_logic;
529 
  signal ethernetm_bg, ethernetm_bg_1, ethernetm_bg_2, ethernetm_bg_q : std_logic;
530 
  signal ethernetm_trafic_limit : std_logic;
531 
  signal ce, idle, ack : std_logic;
532 
begin
533 
ack <= sdram_ctrl2_ack_o;
534 
 
535 
trafic_supervision_1 : entity work.trafic_supervision
536 
generic map(
537 
  priority => 1,
538 
  tot_priority => 6)
539 
port map(
540 
  bg => or32_i_sdram_ctrl2_bg,
541 
  ce => ce,
542 
  trafic_limit => or32_i_trafic_limit,
543 
  clk => clk,
544 
  reset => reset);
545 
 
546 
trafic_supervision_2 : entity work.trafic_supervision
547 
generic map(
548 
  priority => 3,
549 
  tot_priority => 6)
550 
port map(
551 
  bg => or32_d_sdram_ctrl2_bg,
552 
  ce => ce,
553 
  trafic_limit => or32_d_trafic_limit,
554 
  clk => clk,
555 
  reset => reset);
556 
 
557 
trafic_supervision_3 : entity work.trafic_supervision
558 
generic map(
559 
  priority => 1,
560 
  tot_priority => 6)
561 
port map(
562 
  bg => debug_sdram_ctrl2_bg,
563 
  ce => ce,
564 
  trafic_limit => debug_trafic_limit,
565 
  clk => clk,
566 
  reset => reset);
567 
 
568 
trafic_supervision_4 : entity work.trafic_supervision
569 
generic map(
570 
  priority => 1,
571 
  tot_priority => 6)
572 
port map(
573 
  bg => ethernetm_sdram_ctrl2_bg,
574 
  ce => ce,
575 
  trafic_limit => ethernetm_trafic_limit,
576 
  clk => clk,
577 
  reset => reset);
578 
 
579 
process(clk,reset)
580 
begin
581 
if reset='1' then
582 
  or32_i_bg_q <= '0';
583 
elsif clk'event and clk='1' then
584 
if or32_i_bg_q='0' then
585 
  or32_i_bg_q <= or32_i_bg;
586 
elsif ack='1' and (or32_i_cti_o="000" or or32_i_cti_o="111") then
587 
  or32_i_bg_q <= '0';
588 
end if;
589 
end if;
590 
end process;
591 
 
592 
process(clk,reset)
593 
begin
594 
if reset='1' then
595 
  or32_d_bg_q <= '0';
596 
elsif clk'event and clk='1' then
597 
if or32_d_bg_q='0' then
598 
  or32_d_bg_q <= or32_d_bg;
599 
elsif ack='1' and (or32_d_cti_o="000" or or32_d_cti_o="111") then
600 
  or32_d_bg_q <= '0';
601 
end if;
602 
end if;
603 
end process;
604 
 
605 
process(clk,reset)
606 
begin
607 
if reset='1' then
608 
  debug_bg_q <= '0';
609 
elsif clk'event and clk='1' then
610 
if debug_bg_q='0' then
611 
  debug_bg_q <= debug_bg;
612 
elsif ack='1' then
613 
  debug_bg_q <= '0';
614 
end if;
615 
end if;
616 
end process;
617 
 
618 
process(clk,reset)
619 
begin
620 
if reset='1' then
621 
  ethernetm_bg_q <= '0';
622 
elsif clk'event and clk='1' then
623 
if ethernetm_bg_q='0' then
624 
  ethernetm_bg_q <= ethernetm_bg;
625 
elsif ack='1' and (ethernetm_cti_o="000" or ethernetm_cti_o="111") then
626 
  ethernetm_bg_q <= '0';
627 
end if;
628 
end if;
629 
end process;
630 
 
631 
idle <= '1' when or32_i_bg_q='0' and or32_d_bg_q='0' and debug_bg_q='0' and ethernetm_bg_q='0' else '0';
632 
or32_i_bg_1 <= '1' when idle='1' and or32_i_cyc_o='1' and or32_i_sdram_ctrl2_ss='1' and or32_i_trafic_limit='0' else '0';
633 
or32_d_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl2_ss='1' and or32_d_trafic_limit='0' else '0';
634 
debug_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0') and debug_cyc_o='1' and debug_sdram_ctrl2_ss='1' and debug_trafic_limit='0' else '0';
635 
ethernetm_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl2_ss='1' and ethernetm_trafic_limit='0' else '0';
636 
or32_i_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0') and or32_i_cyc_o='1' and or32_i_sdram_ctrl2_ss='1' else '0';
637 
or32_d_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl2_ss='1' else '0';
638 
debug_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0') and debug_cyc_o='1' and debug_sdram_ctrl2_ss='1' else '0';
639 
ethernetm_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0' and debug_bg_2='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl2_ss='1' else '0';
640 
or32_i_bg <= or32_i_bg_q or or32_i_bg_1 or or32_i_bg_2;
641 
or32_d_bg <= or32_d_bg_q or or32_d_bg_1 or or32_d_bg_2;
642 
debug_bg <= debug_bg_q or debug_bg_1 or debug_bg_2;
643 
ethernetm_bg <= ethernetm_bg_q or ethernetm_bg_1 or ethernetm_bg_2;
644 
ce <= (or32_i_cyc_o and or32_i_sdram_ctrl2_ss) or (or32_d_cyc_o and or32_d_sdram_ctrl2_ss) or (debug_cyc_o and debug_sdram_ctrl2_ss) or (ethernetm_cyc_o and ethernetm_sdram_ctrl2_ss) when idle='1' else '0';
645 
or32_i_sdram_ctrl2_bg <= or32_i_bg;
646 
or32_d_sdram_ctrl2_bg <= or32_d_bg;
647 
debug_sdram_ctrl2_bg <= debug_bg;
648 
ethernetm_sdram_ctrl2_bg <= ethernetm_bg;
649 
end block arbiter_sdram_ctrl2;
650 2 unneback 
arbiter_bootRAM : block
651 
  signal or32_i_bg, or32_i_bg_1, or32_i_bg_2, or32_i_bg_q : std_logic;
652 
  signal or32_i_trafic_limit : std_logic;
653 
  signal or32_d_bg, or32_d_bg_1, or32_d_bg_2, or32_d_bg_q : std_logic;
654 
  signal or32_d_trafic_limit : std_logic;
655 8 unneback 
  signal debug_bg, debug_bg_1, debug_bg_2, debug_bg_q : std_logic;
656 
  signal debug_trafic_limit : std_logic;
657 2 unneback 
  signal ce, idle, ack : std_logic;
658 
begin
659 
ack <= bootRAM_ack_o;
660 
 
661 
trafic_supervision_1 : entity work.trafic_supervision
662 
generic map(
663 8 unneback 
  priority => 1,
664 
  tot_priority => 3)
665 2 unneback 
port map(
666 
  bg => or32_i_bootRAM_bg,
667 
  ce => ce,
668 
  trafic_limit => or32_i_trafic_limit,
669 
  clk => clk,
670 
  reset => reset);
671 
 
672 
trafic_supervision_2 : entity work.trafic_supervision
673 
generic map(
674 
  priority => 1,
675 8 unneback 
  tot_priority => 3)
676 2 unneback 
port map(
677 
  bg => or32_d_bootRAM_bg,
678 
  ce => ce,
679 
  trafic_limit => or32_d_trafic_limit,
680 
  clk => clk,
681 
  reset => reset);
682 
 
683 8 unneback 
trafic_supervision_3 : entity work.trafic_supervision
684 
generic map(
685 
  priority => 1,
686 
  tot_priority => 3)
687 
port map(
688 
  bg => debug_bootRAM_bg,
689 
  ce => ce,
690 
  trafic_limit => debug_trafic_limit,
691 
  clk => clk,
692 
  reset => reset);
693 
 
694 2 unneback 
process(clk,reset)
695 
begin
696 
if reset='1' then
697 
  or32_i_bg_q <= '0';
698 
elsif clk'event and clk='1' then
699 
if or32_i_bg_q='0' then
700 
  or32_i_bg_q <= or32_i_bg;
701 
elsif ack='1' and (or32_i_cti_o="000" or or32_i_cti_o="111") then
702 
  or32_i_bg_q <= '0';
703 
end if;
704 
end if;
705 
end process;
706 
 
707 
process(clk,reset)
708 
begin
709 
if reset='1' then
710 
  or32_d_bg_q <= '0';
711 
elsif clk'event and clk='1' then
712 
if or32_d_bg_q='0' then
713 
  or32_d_bg_q <= or32_d_bg;
714 
elsif ack='1' and (or32_d_cti_o="000" or or32_d_cti_o="111") then
715 
  or32_d_bg_q <= '0';
716 
end if;
717 
end if;
718 
end process;
719 
 
720 8 unneback 
process(clk,reset)
721 
begin
722 
if reset='1' then
723 
  debug_bg_q <= '0';
724 
elsif clk'event and clk='1' then
725 
if debug_bg_q='0' then
726 
  debug_bg_q <= debug_bg;
727 
elsif ack='1' then
728 
  debug_bg_q <= '0';
729 
end if;
730 
end if;
731 
end process;
732 
 
733 
idle <= '1' when or32_i_bg_q='0' and or32_d_bg_q='0' and debug_bg_q='0' else '0';
734 2 unneback 
or32_i_bg_1 <= '1' when idle='1' and or32_i_cyc_o='1' and or32_i_bootRAM_ss='1' and or32_i_trafic_limit='0' else '0';
735 8 unneback 
or32_d_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0') and or32_d_cyc_o='1' and or32_d_bootRAM_ss='1' and or32_d_trafic_limit='0' else '0';
736 
debug_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0') and debug_cyc_o='1' and debug_bootRAM_ss='1' and debug_trafic_limit='0' else '0';
737 
or32_i_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0') and or32_i_cyc_o='1' and or32_i_bootRAM_ss='1' else '0';
738 
or32_d_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and or32_i_bg_2='0') and or32_d_cyc_o='1' and or32_d_bootRAM_ss='1' else '0';
739 
debug_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0') and debug_cyc_o='1' and debug_bootRAM_ss='1' else '0';
740 2 unneback 
or32_i_bg <= or32_i_bg_q or or32_i_bg_1 or or32_i_bg_2;
741 
or32_d_bg <= or32_d_bg_q or or32_d_bg_1 or or32_d_bg_2;
742 8 unneback 
debug_bg <= debug_bg_q or debug_bg_1 or debug_bg_2;
743 
ce <= (or32_i_cyc_o and or32_i_bootRAM_ss) or (or32_d_cyc_o and or32_d_bootRAM_ss) or (debug_cyc_o and debug_bootRAM_ss) when idle='1' else '0';
744 2 unneback 
or32_i_bootRAM_bg <= or32_i_bg;
745 
or32_d_bootRAM_bg <= or32_d_bg;
746 8 unneback 
debug_bootRAM_bg <= debug_bg;
747 2 unneback 
end block arbiter_bootRAM;
748 8 unneback 
or32_d_ethernets_bg <= or32_d_ethernets_ss and or32_d_cyc_o;
749 2 unneback 
decoder:block
750 
begin
751 8 unneback 
or32_i_sdram_ctrl1_ss <= '1' when or32_i_adr_o(31 downto 28)="0000" else
752 2 unneback 
'0';
753 8 unneback 
or32_i_sdram_ctrl2_ss <= '1' when or32_i_adr_o(31 downto 28)="0001" else
754 2 unneback 
'0';
755 8 unneback 
or32_i_bootRAM_ss <= '1' when or32_i_adr_o(31 downto 28)="1111" else
756 2 unneback 
'0';
757 8 unneback 
or32_d_uart_ss <= '1' when or32_d_adr_o(31 downto 24)="10010000" else
758 
'0';
759 
or32_d_sdram_ctrl1_ss <= '1' when or32_d_adr_o(31 downto 28)="0000" else
760 
'0';
761 
or32_d_sdram_ctrl2_ss <= '1' when or32_d_adr_o(31 downto 28)="0001" else
762 
'0';
763 
or32_d_bootRAM_ss <= '1' when or32_d_adr_o(31 downto 28)="1111" else
764 
'0';
765 
or32_d_ethernets_ss <= '1' when or32_d_adr_o(31 downto 24)="10010010" else
766 
'0';
767 
debug_sdram_ctrl1_ss <= '1' when debug_adr_o(31 downto 28)="0000" else
768 
'0';
769 
debug_sdram_ctrl2_ss <= '1' when debug_adr_o(31 downto 28)="0001" else
770 
'0';
771 
debug_bootRAM_ss <= '1' when debug_adr_o(31 downto 28)="1111" else
772 
'0';
773 
ethernetm_sdram_ctrl1_ss <= '1' when ethernetm_adr_o(31 downto 28)="0000" else
774 
'0';
775 
ethernetm_sdram_ctrl2_ss <= '1' when ethernetm_adr_o(31 downto 28)="0001" else
776 
'0';
777 2 unneback 
uart_adr_i <= or32_d_adr_o(4 downto 0);
778 8 unneback 
sdram_ctrl1_adr_i <= (or32_i_adr_o(23 downto 2) and or32_i_sdram_ctrl1_bg) or (or32_d_adr_o(23 downto 2) and or32_d_sdram_ctrl1_bg) or (debug_adr_o(23 downto 2) and debug_sdram_ctrl1_bg) or (ethernetm_adr_o(23 downto 2) and ethernetm_sdram_ctrl1_bg);
779 
sdram_ctrl2_adr_i <= (or32_i_adr_o(23 downto 2) and or32_i_sdram_ctrl2_bg) or (or32_d_adr_o(23 downto 2) and or32_d_sdram_ctrl2_bg) or (debug_adr_o(23 downto 2) and debug_sdram_ctrl2_bg) or (ethernetm_adr_o(23 downto 2) and ethernetm_sdram_ctrl2_bg);
780 
bootRAM_adr_i <= (or32_i_adr_o(11 downto 2) and or32_i_bootRAM_bg) or (or32_d_adr_o(11 downto 2) and or32_d_bootRAM_bg) or (debug_adr_o(11 downto 2) and debug_bootRAM_bg);
781 
ethernets_adr_i <= or32_d_adr_o(11 downto 2);
782 2 unneback 
end block decoder;
783 
 
784 
-- cyc_i(s)
785 
uart_cyc_i <= (or32_d_cyc_o and or32_d_uart_bg);
786 8 unneback 
sdram_ctrl1_cyc_i <= (or32_i_cyc_o and or32_i_sdram_ctrl1_bg) or (or32_d_cyc_o and or32_d_sdram_ctrl1_bg) or (debug_cyc_o and debug_sdram_ctrl1_bg) or (ethernetm_cyc_o and ethernetm_sdram_ctrl1_bg);
787 
sdram_ctrl2_cyc_i <= (or32_i_cyc_o and or32_i_sdram_ctrl2_bg) or (or32_d_cyc_o and or32_d_sdram_ctrl2_bg) or (debug_cyc_o and debug_sdram_ctrl2_bg) or (ethernetm_cyc_o and ethernetm_sdram_ctrl2_bg);
788 
bootRAM_cyc_i <= (or32_i_cyc_o and or32_i_bootRAM_bg) or (or32_d_cyc_o and or32_d_bootRAM_bg) or (debug_cyc_o and debug_bootRAM_bg);
789 
ethernets_cyc_i <= (or32_d_cyc_o and or32_d_ethernets_bg);
790 2 unneback 
-- stb_i(s)
791 
uart_stb_i <= (or32_d_stb_o and or32_d_uart_bg);
792 8 unneback 
sdram_ctrl1_stb_i <= (or32_i_stb_o and or32_i_sdram_ctrl1_bg) or (or32_d_stb_o and or32_d_sdram_ctrl1_bg) or (debug_stb_o and debug_sdram_ctrl1_bg) or (ethernetm_stb_o and ethernetm_sdram_ctrl1_bg);
793 
sdram_ctrl2_stb_i <= (or32_i_stb_o and or32_i_sdram_ctrl2_bg) or (or32_d_stb_o and or32_d_sdram_ctrl2_bg) or (debug_stb_o and debug_sdram_ctrl2_bg) or (ethernetm_stb_o and ethernetm_sdram_ctrl2_bg);
794 
bootRAM_stb_i <= (or32_i_stb_o and or32_i_bootRAM_bg) or (or32_d_stb_o and or32_d_bootRAM_bg) or (debug_stb_o and debug_bootRAM_bg);
795 
ethernets_stb_i <= (or32_d_stb_o and or32_d_ethernets_bg);
796 2 unneback 
-- we_i(s)
797 
uart_we_i <= (or32_d_we_o and or32_d_uart_bg);
798 8 unneback 
sdram_ctrl1_we_i <= (or32_d_we_o and or32_d_sdram_ctrl1_bg) or (debug_we_o and debug_sdram_ctrl1_bg) or (ethernetm_we_o and ethernetm_sdram_ctrl1_bg);
799 
sdram_ctrl2_we_i <= (or32_d_we_o and or32_d_sdram_ctrl2_bg) or (debug_we_o and debug_sdram_ctrl2_bg) or (ethernetm_we_o and ethernetm_sdram_ctrl2_bg);
800 
ethernets_we_i <= (or32_d_we_o and or32_d_ethernets_bg);
801 2 unneback 
-- ack_i(s)
802 8 unneback 
or32_i_ack_i <= (sdram_ctrl1_ack_o and or32_i_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and or32_i_sdram_ctrl2_bg) or (bootRAM_ack_o and or32_i_bootRAM_bg);
803 
or32_d_ack_i <= (uart_ack_o and or32_d_uart_bg) or (sdram_ctrl1_ack_o and or32_d_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and or32_d_sdram_ctrl2_bg) or (bootRAM_ack_o and or32_d_bootRAM_bg) or (ethernets_ack_o and or32_d_ethernets_bg);
804 
debug_ack_i <= (sdram_ctrl1_ack_o and debug_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and debug_sdram_ctrl2_bg) or (bootRAM_ack_o and debug_bootRAM_bg);
805 
ethernetm_ack_i <= (sdram_ctrl1_ack_o and ethernetm_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and ethernetm_sdram_ctrl2_bg);
806 2 unneback 
-- rty_i(s)
807 
or32_i_rty_i <= '0';
808 
or32_d_rty_i <= '0';
809 8 unneback 
debug_rty_i <= '0';
810 2 unneback 
-- err_i(s)
811 
or32_i_err_i <= '0';
812 
or32_d_err_i <= '0';
813 8 unneback 
debug_err_i <= '0';
814 
ethernetm_err_i <= '0';
815 2 unneback 
-- sel_i(s)
816 
uart_sel_i <= (or32_d_sel_o and or32_d_uart_bg);
817 8 unneback 
sdram_ctrl1_sel_i <= (or32_i_sel_o and or32_i_sdram_ctrl1_bg) or (or32_d_sel_o and or32_d_sdram_ctrl1_bg) or (debug_sel_o and debug_sdram_ctrl1_bg) or (ethernetm_sel_o and ethernetm_sdram_ctrl1_bg);
818 
sdram_ctrl2_sel_i <= (or32_i_sel_o and or32_i_sdram_ctrl2_bg) or (or32_d_sel_o and or32_d_sdram_ctrl2_bg) or (debug_sel_o and debug_sdram_ctrl2_bg) or (ethernetm_sel_o and ethernetm_sdram_ctrl2_bg);
819 
bootRAM_sel_i <= (or32_i_sel_o and or32_i_bootRAM_bg) or (or32_d_sel_o and or32_d_bootRAM_bg) or (debug_sel_o and debug_bootRAM_bg);
820 
ethernets_sel_i <= (or32_d_sel_o and or32_d_ethernets_bg);
821 2 unneback 
-- slave dat_i(s)
822 
uart_dat_i <= or32_d_dat_o;
823 8 unneback 
sdram_ctrl1_dat_i <= (or32_d_dat_o and or32_d_sdram_ctrl1_bg) or (debug_dat_o and debug_sdram_ctrl1_bg) or (ethernetm_dat_o and ethernetm_sdram_ctrl1_bg);
824 
sdram_ctrl2_dat_i <= (or32_d_dat_o and or32_d_sdram_ctrl2_bg) or (debug_dat_o and debug_sdram_ctrl2_bg) or (ethernetm_dat_o and ethernetm_sdram_ctrl2_bg);
825 
ethernets_dat_i <= or32_d_dat_o;
826 2 unneback 
-- master dat_i(s)
827 8 unneback 
or32_i_dat_i <= (sdram_ctrl1_dat_o and or32_i_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and or32_i_sdram_ctrl2_bg) or (bootRAM_dat_o and or32_i_bootRAM_bg);
828 
or32_d_dat_i <= (uart_dat_o and or32_d_uart_bg) or (sdram_ctrl1_dat_o and or32_d_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and or32_d_sdram_ctrl2_bg) or (bootRAM_dat_o and or32_d_bootRAM_bg) or (ethernets_dat_o and or32_d_ethernets_bg);
829 
debug_dat_i <= (sdram_ctrl1_dat_o and debug_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and debug_sdram_ctrl2_bg) or (bootRAM_dat_o and debug_bootRAM_bg);
830 
ethernetm_dat_i <= (sdram_ctrl1_dat_o and ethernetm_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and ethernetm_sdram_ctrl2_bg);
831 2 unneback 
-- tgc_i
832 8 unneback 
sdram_ctrl1_cti_i <= (or32_i_cti_o and or32_i_sdram_ctrl1_bg) or (or32_d_cti_o and or32_d_sdram_ctrl1_bg) or (ethernetm_cti_o and ethernetm_sdram_ctrl1_bg);
833 
sdram_ctrl2_cti_i <= (or32_i_cti_o and or32_i_sdram_ctrl2_bg) or (or32_d_cti_o and or32_d_sdram_ctrl2_bg) or (ethernetm_cti_o and ethernetm_sdram_ctrl2_bg);
834 2 unneback 
-- tga_i
835 
or32_i_wbm_i.dat_i <= or32_i_dat_i;
836 
or32_i_wbm_i.ack_i <= or32_i_ack_i ;
837 
or32_i_wbm_i.err_i <= or32_i_err_i;
838 
or32_i_wbm_i.rty_i <= or32_i_rty_i;
839 
or32_i_sel_o <= or32_i_wbm_o.sel_o;
840 
or32_i_adr_o <= or32_i_wbm_o.adr_o;
841 
or32_i_cti_o <= or32_i_wbm_o.cti_o;
842 
or32_i_bte_o <= or32_i_wbm_o.bte_o;
843 
or32_i_cyc_o <= or32_i_wbm_o.cyc_o;
844 
or32_i_stb_o <= or32_i_wbm_o.stb_o;
845 
or32_d_wbm_i.dat_i <= or32_d_dat_i;
846 
or32_d_wbm_i.ack_i <= or32_d_ack_i ;
847 
or32_d_wbm_i.err_i <= or32_d_err_i;
848 
or32_d_wbm_i.rty_i <= or32_d_rty_i;
849 
or32_d_dat_o <= or32_d_wbm_o.dat_o;
850 
or32_d_we_o  <= or32_d_wbm_o.we_o;
851 
or32_d_sel_o <= or32_d_wbm_o.sel_o;
852 
or32_d_adr_o <= or32_d_wbm_o.adr_o;
853 
or32_d_cti_o <= or32_d_wbm_o.cti_o;
854 
or32_d_bte_o <= or32_d_wbm_o.bte_o;
855 
or32_d_cyc_o <= or32_d_wbm_o.cyc_o;
856 
or32_d_stb_o <= or32_d_wbm_o.stb_o;
857 8 unneback 
debug_wbm_i.dat_i <= debug_dat_i;
858 
debug_wbm_i.ack_i <= debug_ack_i ;
859 
debug_wbm_i.err_i <= debug_err_i;
860 
debug_wbm_i.rty_i <= debug_rty_i;
861 
debug_dat_o <= debug_wbm_o.dat_o;
862 
debug_we_o  <= debug_wbm_o.we_o;
863 
debug_sel_o <= debug_wbm_o.sel_o;
864 
debug_adr_o <= debug_wbm_o.adr_o;
865 
debug_cyc_o <= debug_wbm_o.cyc_o;
866 
debug_stb_o <= debug_wbm_o.stb_o;
867 
ethernetm_wbm_i.dat_i <= ethernetm_dat_i;
868 
ethernetm_wbm_i.ack_i <= ethernetm_ack_i ;
869 
ethernetm_wbm_i.err_i <= ethernetm_err_i;
870 
ethernetm_dat_o <= ethernetm_wbm_o.dat_o;
871 
ethernetm_we_o  <= ethernetm_wbm_o.we_o;
872 
ethernetm_sel_o <= ethernetm_wbm_o.sel_o;
873 
ethernetm_adr_o <= ethernetm_wbm_o.adr_o;
874 
ethernetm_cti_o <= ethernetm_wbm_o.cti_o;
875 
ethernetm_bte_o <= ethernetm_wbm_o.bte_o;
876 
ethernetm_cyc_o <= ethernetm_wbm_o.cyc_o;
877 
ethernetm_stb_o <= ethernetm_wbm_o.stb_o;
878 2 unneback 
uart_dat_o <= uart_wbs_o.dat_o;
879 
uart_ack_o <= uart_wbs_o.ack_o;
880 
uart_wbs_i.dat_i <= uart_dat_i;
881 
uart_wbs_i.we_i  <= uart_we_i;
882 
uart_wbs_i.sel_i <= uart_sel_i;
883 
uart_wbs_i.adr_i <= uart_adr_i;
884 
uart_wbs_i.cyc_i <= uart_cyc_i;
885 
uart_wbs_i.stb_i <= uart_stb_i;
886 8 unneback 
sdram_ctrl1_dat_o <= sdram_ctrl1_wbs_o.dat_o;
887 
sdram_ctrl1_ack_o <= sdram_ctrl1_wbs_o.ack_o;
888 
sdram_ctrl1_wbs_i.dat_i <= sdram_ctrl1_dat_i;
889 
sdram_ctrl1_wbs_i.we_i  <= sdram_ctrl1_we_i;
890 
sdram_ctrl1_wbs_i.sel_i <= sdram_ctrl1_sel_i;
891 
sdram_ctrl1_wbs_i.adr_i <= sdram_ctrl1_adr_i;
892 
sdram_ctrl1_wbs_i.cti_i <= sdram_ctrl1_cti_i;
893 
sdram_ctrl1_wbs_i.cyc_i <= sdram_ctrl1_cyc_i;
894 
sdram_ctrl1_wbs_i.stb_i <= sdram_ctrl1_stb_i;
895 
sdram_ctrl2_dat_o <= sdram_ctrl2_wbs_o.dat_o;
896 
sdram_ctrl2_ack_o <= sdram_ctrl2_wbs_o.ack_o;
897 
sdram_ctrl2_wbs_i.dat_i <= sdram_ctrl2_dat_i;
898 
sdram_ctrl2_wbs_i.we_i  <= sdram_ctrl2_we_i;
899 
sdram_ctrl2_wbs_i.sel_i <= sdram_ctrl2_sel_i;
900 
sdram_ctrl2_wbs_i.adr_i <= sdram_ctrl2_adr_i;
901 
sdram_ctrl2_wbs_i.cti_i <= sdram_ctrl2_cti_i;
902 
sdram_ctrl2_wbs_i.cyc_i <= sdram_ctrl2_cyc_i;
903 
sdram_ctrl2_wbs_i.stb_i <= sdram_ctrl2_stb_i;
904 2 unneback 
bootRAM_dat_o <= bootRAM_wbs_o.dat_o;
905 
bootRAM_ack_o <= bootRAM_wbs_o.ack_o;
906 
bootRAM_wbs_i.sel_i <= bootRAM_sel_i;
907 
bootRAM_wbs_i.adr_i <= bootRAM_adr_i;
908 
bootRAM_wbs_i.cyc_i <= bootRAM_cyc_i;
909 
bootRAM_wbs_i.stb_i <= bootRAM_stb_i;
910 8 unneback 
ethernets_dat_o <= ethernets_wbs_o.dat_o;
911 
ethernets_ack_o <= ethernets_wbs_o.ack_o;
912 
ethernets_err_o <= ethernets_wbs_o.err_o;
913 
ethernets_wbs_i.dat_i <= ethernets_dat_i;
914 
ethernets_wbs_i.we_i  <= ethernets_we_i;
915 
ethernets_wbs_i.sel_i <= ethernets_sel_i;
916 
ethernets_wbs_i.adr_i <= ethernets_adr_i;
917 
ethernets_wbs_i.cyc_i <= ethernets_cyc_i;
918 
ethernets_wbs_i.stb_i <= ethernets_stb_i;
919 2 unneback 
end rtl;

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