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Subversion Repositories wb_builder

[/] [wb_builder/] [trunk/] [rtl/] [vhdl/] [wishbone.defines] - Blame information for rev 2

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Line No. Rev Author Line
1 2 unneback 
# Generated by PERL program wishbone.pl.
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# File used as input for wishbone arbiter generation
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# Generated Fri Apr 30 16:20:22 2004
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filename=wb
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intercon=intercon
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syscon=syscon
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target=altera
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hdl=vhdl
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signal_groups=1
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tga_bits=2
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tgc_bits=3
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tgd_bits=0
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rename_tga=bte
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rename_tgc=cti
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rename_tgd=tgd
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classic=000
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endofburst=111
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dat_size=32
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adr_size=32
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mux_type=andor
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interconnect=crossbarswitch
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master or32_i
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  type=ro
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  lock_o=0
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  tga_o=1
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  tgc_o=1
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  tgd_o=0
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  err_i=1
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  rty_i=1
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  priority_uart=0
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  priority_bootRAM=3
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end master or32_i
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master or32_d
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  type=rw
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  lock_o=0
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  tga_o=1
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  tgc_o=1
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  tgd_o=0
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  err_i=1
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  rty_i=1
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  priority_uart=1
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  priority_bootRAM=1
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end master or32_d
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slave uart
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  type=rw
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  adr_i_hi=4
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  adr_i_lo=0
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  tga_i=0
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  tgc_i=0
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  tgd_i=0
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  lock_i=0
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  err_o=0
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  rty_o=0
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  baseadr=0x90000000
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  size=0x00100000
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  baseadr1=0x00000000
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  size1=0xffffffff
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  baseadr2=0x00000000
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  size2=0xffffffff
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end slave uart
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slave bootRAM
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  type=rw
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  adr_i_hi=11
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  adr_i_lo=2
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  tga_i=0
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  tgc_i=0
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  tgd_i=0
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  lock_i=0
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  err_o=0
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  rty_o=0
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  baseadr=0x00000000
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  size=0x00100000
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  baseadr1=0x00000000
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  size1=0xffffffff
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  baseadr2=0x00000000
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  size2=0xffffffff
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end slave bootRAM

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