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johny |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Connection Matrix Test Cases ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: tests.v,v 1.1.1.1 2003-04-19 08:40:17 johny Exp $
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//
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// $Date: 2003-04-19 08:40:17 $
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// $Revision: 1.1.1.1 $
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// $Author: johny $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/19 11:04:27 rudi
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// WISHBONE CONMAX IP Core
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//
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//
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//
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//
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//
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//
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task show_errors;
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begin
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$display("\n");
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$display(" +--------------------+");
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$display(" | Total ERRORS: %0d |", error_cnt);
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$display(" +--------------------+");
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end
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endtask
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task init_all_mem;
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begin
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s0.fill_mem(1);
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s1.fill_mem(1);
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s2.fill_mem(1);
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s3.fill_mem(1);
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s4.fill_mem(1);
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s5.fill_mem(1);
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s6.fill_mem(1);
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s7.fill_mem(1);
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m0.mem_fill;
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m1.mem_fill;
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m2.mem_fill;
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m3.mem_fill;
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m4.mem_fill;
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m5.mem_fill;
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m6.mem_fill;
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m7.mem_fill;
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end
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endtask
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task verify;
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input master;
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input slave;
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input count;
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integer master, slave, count;
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begin
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verify_sub(master,slave,count,0,0);
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end
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endtask
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task verify_sub;
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input master;
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input slave;
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input count;
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input mo;
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input so;
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integer master, slave, count;
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integer mo, so;
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integer o;
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integer n;
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reg [31:0] mdata, sdata;
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begin
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//$display("V2: %0d %0d %0d %0d %0d",master, slave, count, mo,so);
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for(n=0;n<count;n=n+1)
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begin
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case(master)
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0: mdata = m0.mem[n+mo];
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1: mdata = m1.mem[n+mo];
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2: mdata = m2.mem[n+mo];
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3: mdata = m3.mem[n+mo];
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4: mdata = m4.mem[n+mo];
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5: mdata = m5.mem[n+mo];
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6: mdata = m6.mem[n+mo];
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7: mdata = m7.mem[n+mo];
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default:
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begin
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$display("ERROR: Illegal Master %0d", master);
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$finish;
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end
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endcase
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o = 0;
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case(master)
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0: o = 16'h000;
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1: o = 16'h040;
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2: o = 16'h080;
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3: o = 16'h0c0;
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4: o = 16'h100;
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5: o = 16'h140;
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6: o = 16'h180;
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7: o = 16'h1c0;
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endcase
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case(slave)
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0: sdata = s0.mem[n+o+so];
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1: sdata = s1.mem[n+o+so];
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2: sdata = s2.mem[n+o+so];
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3: sdata = s3.mem[n+o+so];
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4: sdata = s4.mem[n+o+so];
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5: sdata = s5.mem[n+o+so];
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6: sdata = s6.mem[n+o+so];
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7: sdata = s7.mem[n+o+so];
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default:
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begin
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$display("ERROR: Illegal Slave %0d", slave);
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$finish;
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end
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endcase
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//$display("INFO: Master[%0d]: %h - Slave[%0d]: %h (%0t)",
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// master, mdata, slave, sdata, $time);
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if(mdata !== sdata)
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begin
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$display("ERROR: Master[%0d][%0d]: %h - Slave[%0d]: %h (%0t)",
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master, n, mdata, slave, sdata, $time);
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error_cnt = error_cnt + 1;
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end
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end
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end
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endtask
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task test_arb1;
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integer n, del;
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reg [31:0] data;
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begin
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$display("\n\n");
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$display("*****************************************************");
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$display("*** Arb. 1 Test ... ***");
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$display("*****************************************************\n");
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del = 4;
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for(del = 0;del < 5; del=del+1 )
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begin
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$display("Delay: %0d", del);
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init_all_mem;
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m1.wb_wr1( 32'hff00_0000, 4'hf, 32'h0000_a5ff);
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fork
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begin
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m0.wb_rd_mult( 32'h0000_0000 + (0 << 28), 4'hf, del, 4);
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m0.wb_rd1( 32'hff00_0000, 4'hf, data);
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if(data !== 32'h0000_a5ff)
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begin
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$display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
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error_cnt = error_cnt + 1;
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end
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m0.wb_wr_mult( 32'h0000_0010 + (0 << 28), 4'hf, del, 4);
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m0.wb_rd_mult( 32'h0000_0020 + (0 << 28), 4'hf, del, 4);
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m0.wb_wr_mult( 32'h0000_0030 + (0 << 28), 4'hf, del, 4);
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end
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begin
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m1.wb_wr_mult( 32'h0000_0100 + (0 << 28), 4'hf, del, 4);
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m1.wb_rd_mult( 32'h0000_0110 + (0 << 28), 4'hf, del, 4);
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m1.wb_rd1( 32'hff00_0000, 4'hf, data);
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if(data !== 32'h0000_a5ff)
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begin
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$display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
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error_cnt = error_cnt + 1;
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end
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m1.wb_wr_mult( 32'h0000_0120 + (0 << 28), 4'hf, del, 4);
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m1.wb_rd_mult( 32'h0000_0130 + (0 << 28), 4'hf, del, 4);
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end
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begin
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m2.wb_rd_mult( 32'h0000_0200 + (0 << 28), 4'hf, del, 4);
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m2.wb_wr_mult( 32'h0000_0210 + (0 << 28), 4'hf, del, 4);
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m2.wb_rd_mult( 32'h0000_0220 + (0 << 28), 4'hf, del, 4);
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m2.wb_rd1( 32'hff00_0000, 4'hf, data);
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if(data !== 32'h0000_a5ff)
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begin
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$display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
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error_cnt = error_cnt + 1;
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end
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m2.wb_wr_mult( 32'h0000_0230 + (0 << 28), 4'hf, del, 4);
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end
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begin
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m3.wb_wr_mult( 32'h0000_0300 + (0 << 28), 4'hf, del, 4);
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m3.wb_rd_mult( 32'h0000_0310 + (0 << 28), 4'hf, del, 4);
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m3.wb_wr_mult( 32'h0000_0320 + (0 << 28), 4'hf, del, 4);
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m3.wb_rd_mult( 32'h0000_0330 + (0 << 28), 4'hf, del, 4);
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m3.wb_rd1( 32'hff00_0000, 4'hf, data);
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if(data !== 32'h0000_a5ff)
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begin
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$display("ERROR: RF read mismatch: Exp. a5ff, Got %h", data);
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error_cnt = error_cnt + 1;
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end
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end
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begin
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| 262 |
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m4.wb_rd_mult( 32'h0000_0400 + (1 << 28), 4'hf, del, 4);
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m4.wb_wr_mult( 32'h0000_0410 + (1 << 28), 4'hf, del, 4);
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m4.wb_rd_mult( 32'h0000_0420 + (1 << 28), 4'hf, del, 4);
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m4.wb_wr_mult( 32'h0000_0430 + (1 << 28), 4'hf, del, 4);
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| 266 |
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end
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| 268 |
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begin
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| 269 |
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m5.wb_rd_mult( 32'h0000_0500 + (1 << 28), 4'hf, del, 4);
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| 270 |
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m5.wb_wr_mult( 32'h0000_0510 + (1 << 28), 4'hf, del, 4);
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| 271 |
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m5.wb_rd_mult( 32'h0000_0520 + (1 << 28), 4'hf, del, 4);
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| 272 |
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m5.wb_wr_mult( 32'h0000_0530 + (1 << 28), 4'hf, del, 4);
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| 273 |
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end
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| 275 |
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begin
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| 276 |
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m6.wb_wr_mult( 32'h0000_0600 + (7 << 28), 4'hf, del, 4);
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| 277 |
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m6.wb_rd_mult( 32'h0000_0610 + (7 << 28), 4'hf, del, 4);
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| 278 |
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m6.wb_wr_mult( 32'h0000_0620 + (7 << 28), 4'hf, del, 4);
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| 279 |
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m6.wb_rd_mult( 32'h0000_0630 + (7 << 28), 4'hf, del, 4);
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| 280 |
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end
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| 281 |
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| 282 |
|
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begin
|
| 283 |
|
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m7.wb_wr_mult( 32'h0000_0700 + (7 << 28), 4'hf, del, 4);
|
| 284 |
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m7.wb_rd_mult( 32'h0000_0710 + (7 << 28), 4'hf, del, 4);
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| 285 |
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m7.wb_wr_mult( 32'h0000_0720 + (7 << 28), 4'hf, del, 4);
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| 286 |
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m7.wb_rd_mult( 32'h0000_0730 + (7 << 28), 4'hf, del, 4);
|
| 287 |
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end
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| 288 |
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join
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| 289 |
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| 290 |
|
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verify(0,0,16);
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| 291 |
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verify(1,0,16);
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| 292 |
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verify(2,0,16);
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| 293 |
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verify(3,0,16);
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| 294 |
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verify(4,1,16);
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| 295 |
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verify(5,1,16);
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| 296 |
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verify(6,7,16);
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| 297 |
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verify(7,7,16);
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| 298 |
|
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end
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| 299 |
|
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show_errors;
|
| 300 |
|
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$display("*****************************************************");
|
| 301 |
|
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$display("*** Test DONE ... ***");
|
| 302 |
|
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$display("*****************************************************\n\n");
|
| 303 |
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| 304 |
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end
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| 305 |
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endtask
|
| 306 |
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| 307 |
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| 308 |
|
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task test_arb2;
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| 309 |
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|
| 310 |
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integer m, del, siz;
|
| 311 |
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integer n, a, b;
|
| 312 |
|
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time t[0:7];
|
| 313 |
|
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reg [1:0] p[0:7];
|
| 314 |
|
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|
| 315 |
|
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begin
|
| 316 |
|
|
|
| 317 |
|
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$display("\n\n");
|
| 318 |
|
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$display("*****************************************************");
|
| 319 |
|
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$display("*** Arb. 2 Test ... ***");
|
| 320 |
|
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$display("*****************************************************\n");
|
| 321 |
|
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|
| 322 |
|
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|
| 323 |
|
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siz = 4;
|
| 324 |
|
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del = 0;
|
| 325 |
|
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m=0;
|
| 326 |
|
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for(m=0;m<32;m=m+1)
|
| 327 |
|
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for(del=0;del<7;del=del+1)
|
| 328 |
|
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for(siz=1;siz<5;siz=siz+1)
|
| 329 |
|
|
begin
|
| 330 |
|
|
|
| 331 |
|
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init_all_mem;
|
| 332 |
|
|
$display("Mode: %0d del: %0d, siz: %0d", m, del, siz);
|
| 333 |
|
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|
| 334 |
|
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case(m)
|
| 335 |
|
|
0:
|
| 336 |
|
|
begin
|
| 337 |
|
|
p[7] = 2'd3; // M 7
|
| 338 |
|
|
p[6] = 2'd1; // M 6
|
| 339 |
|
|
p[5] = 2'd2; // M 5
|
| 340 |
|
|
p[4] = 2'd3; // M 4
|
| 341 |
|
|
p[3] = 2'd0; // M 3
|
| 342 |
|
|
p[2] = 2'd1; // M 2
|
| 343 |
|
|
p[1] = 2'd0; // M 1
|
| 344 |
|
|
p[0] = 2'd2; // M 0
|
| 345 |
|
|
end
|
| 346 |
|
|
|
| 347 |
|
|
4:
|
| 348 |
|
|
begin
|
| 349 |
|
|
p[7] = 2'd0; // M 7
|
| 350 |
|
|
p[6] = 2'd1; // M 6
|
| 351 |
|
|
p[5] = 2'd2; // M 5
|
| 352 |
|
|
p[4] = 2'd3; // M 4
|
| 353 |
|
|
p[3] = 2'd3; // M 3
|
| 354 |
|
|
p[2] = 2'd2; // M 2
|
| 355 |
|
|
p[1] = 2'd1; // M 1
|
| 356 |
|
|
p[0] = 2'd0; // M 0
|
| 357 |
|
|
end
|
| 358 |
|
|
|
| 359 |
|
|
8:
|
| 360 |
|
|
begin
|
| 361 |
|
|
p[7] = 2'd3; // M 7
|
| 362 |
|
|
p[6] = 2'd2; // M 6
|
| 363 |
|
|
p[5] = 2'd1; // M 5
|
| 364 |
|
|
p[4] = 2'd0; // M 4
|
| 365 |
|
|
p[3] = 2'd0; // M 3
|
| 366 |
|
|
p[2] = 2'd1; // M 2
|
| 367 |
|
|
p[1] = 2'd2; // M 1
|
| 368 |
|
|
p[0] = 2'd3; // M 0
|
| 369 |
|
|
end
|
| 370 |
|
|
|
| 371 |
|
|
12:
|
| 372 |
|
|
begin
|
| 373 |
|
|
p[7] = 2'd3; // M 7
|
| 374 |
|
|
p[6] = 2'd3; // M 6
|
| 375 |
|
|
p[5] = 2'd3; // M 5
|
| 376 |
|
|
p[4] = 2'd0; // M 4
|
| 377 |
|
|
p[3] = 2'd0; // M 3
|
| 378 |
|
|
p[2] = 2'd0; // M 2
|
| 379 |
|
|
p[1] = 2'd1; // M 1
|
| 380 |
|
|
p[0] = 2'd1; // M 0
|
| 381 |
|
|
end
|
| 382 |
|
|
|
| 383 |
|
|
16:
|
| 384 |
|
|
begin
|
| 385 |
|
|
p[7] = 2'd0; // M 7
|
| 386 |
|
|
p[6] = 2'd0; // M 6
|
| 387 |
|
|
p[5] = 2'd0; // M 5
|
| 388 |
|
|
p[4] = 2'd0; // M 4
|
| 389 |
|
|
p[3] = 2'd1; // M 3
|
| 390 |
|
|
p[2] = 2'd1; // M 2
|
| 391 |
|
|
p[1] = 2'd3; // M 1
|
| 392 |
|
|
p[0] = 2'd3; // M 0
|
| 393 |
|
|
end
|
| 394 |
|
|
|
| 395 |
|
|
20:
|
| 396 |
|
|
begin
|
| 397 |
|
|
p[7] = 2'd3; // M 7
|
| 398 |
|
|
p[6] = 2'd0; // M 6
|
| 399 |
|
|
p[5] = 2'd2; // M 5
|
| 400 |
|
|
p[4] = 2'd0; // M 4
|
| 401 |
|
|
p[3] = 2'd1; // M 3
|
| 402 |
|
|
p[2] = 2'd0; // M 2
|
| 403 |
|
|
p[1] = 2'd0; // M 1
|
| 404 |
|
|
p[0] = 2'd0; // M 0
|
| 405 |
|
|
end
|
| 406 |
|
|
|
| 407 |
|
|
24:
|
| 408 |
|
|
begin
|
| 409 |
|
|
p[7] = 2'd0; // M 7
|
| 410 |
|
|
p[6] = 2'd0; // M 6
|
| 411 |
|
|
p[5] = 2'd1; // M 5
|
| 412 |
|
|
p[4] = 2'd0; // M 4
|
| 413 |
|
|
p[3] = 2'd0; // M 3
|
| 414 |
|
|
p[2] = 2'd2; // M 2
|
| 415 |
|
|
p[1] = 2'd0; // M 1
|
| 416 |
|
|
p[0] = 2'd3; // M 0
|
| 417 |
|
|
end
|
| 418 |
|
|
|
| 419 |
|
|
28:
|
| 420 |
|
|
begin
|
| 421 |
|
|
p[7] = 2'd0; // M 7
|
| 422 |
|
|
p[6] = 2'd0; // M 6
|
| 423 |
|
|
p[5] = 2'd1; // M 5
|
| 424 |
|
|
p[4] = 2'd0; // M 4
|
| 425 |
|
|
p[3] = 2'd0; // M 3
|
| 426 |
|
|
p[2] = 2'd0; // M 2
|
| 427 |
|
|
p[1] = 2'd0; // M 1
|
| 428 |
|
|
p[0] = 2'd3; // M 0
|
| 429 |
|
|
end
|
| 430 |
|
|
|
| 431 |
|
|
default:
|
| 432 |
|
|
begin
|
| 433 |
|
|
p[7] = p[7] + 1;// M 7
|
| 434 |
|
|
p[6] = p[6] + 1;// M 6
|
| 435 |
|
|
p[5] = p[5] + 1;// M 5
|
| 436 |
|
|
p[4] = p[4] + 1;// M 4
|
| 437 |
|
|
p[3] = p[3] + 1;// M 3
|
| 438 |
|
|
p[2] = p[2] + 1;// M 2
|
| 439 |
|
|
p[1] = p[1] + 1;// M 1
|
| 440 |
|
|
p[0] = p[0] + 1;// M 0
|
| 441 |
|
|
end
|
| 442 |
|
|
endcase
|
| 443 |
|
|
|
| 444 |
|
|
m1.wb_wr1( 32'hff00_0000, 4'hf, {16'h0000, p[7], p[6], p[5],
|
| 445 |
|
|
p[4], p[3], p[2], p[1], p[0]} );
|
| 446 |
|
|
|
| 447 |
|
|
@(posedge clk);
|
| 448 |
|
|
fork
|
| 449 |
|
|
begin
|
| 450 |
|
|
repeat(del) @(posedge clk);
|
| 451 |
|
|
m0.wb_wr_mult( 32'h0000_0000 , 4'hf, del, siz);
|
| 452 |
|
|
repeat(del) @(posedge clk);
|
| 453 |
|
|
m0.wb_rd_mult( 32'h0000_0000 + (siz * 4), 4'hf, del, siz);
|
| 454 |
|
|
repeat(del) @(posedge clk);
|
| 455 |
|
|
m0.wb_wr_mult( 32'h0000_0000 + (siz * 8), 4'hf, del, siz);
|
| 456 |
|
|
repeat(del) @(posedge clk);
|
| 457 |
|
|
m0.wb_rd_mult( 32'h0000_0000 + (siz * 12), 4'hf, del, siz);
|
| 458 |
|
|
t[0] = $time;
|
| 459 |
|
|
end
|
| 460 |
|
|
|
| 461 |
|
|
begin
|
| 462 |
|
|
repeat(del) @(posedge clk);
|
| 463 |
|
|
m1.wb_rd_mult( 32'h0000_0100 , 4'hf, del, siz);
|
| 464 |
|
|
repeat(del) @(posedge clk);
|
| 465 |
|
|
m1.wb_wr_mult( 32'h0000_0100 + (siz * 4), 4'hf, del, siz);
|
| 466 |
|
|
repeat(del) @(posedge clk);
|
| 467 |
|
|
m1.wb_rd_mult( 32'h0000_0100 + (siz * 8), 4'hf, del, siz);
|
| 468 |
|
|
repeat(del) @(posedge clk);
|
| 469 |
|
|
m1.wb_wr_mult( 32'h0000_0100 + (siz * 12), 4'hf, del, siz);
|
| 470 |
|
|
t[1] = $time;
|
| 471 |
|
|
end
|
| 472 |
|
|
|
| 473 |
|
|
begin
|
| 474 |
|
|
repeat(del) @(posedge clk);
|
| 475 |
|
|
m2.wb_wr_mult( 32'h0000_0200 , 4'hf, del, siz);
|
| 476 |
|
|
repeat(del) @(posedge clk);
|
| 477 |
|
|
m2.wb_rd_mult( 32'h0000_0200 + (siz * 4), 4'hf, del, siz);
|
| 478 |
|
|
repeat(del) @(posedge clk);
|
| 479 |
|
|
m2.wb_wr_mult( 32'h0000_0200 + (siz * 8), 4'hf, del, siz);
|
| 480 |
|
|
repeat(del) @(posedge clk);
|
| 481 |
|
|
m2.wb_rd_mult( 32'h0000_0200 + (siz * 12), 4'hf, del, siz);
|
| 482 |
|
|
t[2] = $time;
|
| 483 |
|
|
end
|
| 484 |
|
|
|
| 485 |
|
|
begin
|
| 486 |
|
|
repeat(del) @(posedge clk);
|
| 487 |
|
|
m3.wb_rd_mult( 32'h0000_0300 , 4'hf, del, siz);
|
| 488 |
|
|
repeat(del) @(posedge clk);
|
| 489 |
|
|
m3.wb_wr_mult( 32'h0000_0300 + (siz * 4), 4'hf, del, siz);
|
| 490 |
|
|
repeat(del) @(posedge clk);
|
| 491 |
|
|
m3.wb_rd_mult( 32'h0000_0300 + (siz * 8), 4'hf, del, siz);
|
| 492 |
|
|
repeat(del) @(posedge clk);
|
| 493 |
|
|
m3.wb_wr_mult( 32'h0000_0300 + (siz * 12), 4'hf, del, siz);
|
| 494 |
|
|
t[3] = $time;
|
| 495 |
|
|
end
|
| 496 |
|
|
|
| 497 |
|
|
begin
|
| 498 |
|
|
repeat(del) @(posedge clk);
|
| 499 |
|
|
m4.wb_wr_mult( 32'h0000_0400 , 4'hf, del, siz);
|
| 500 |
|
|
repeat(del) @(posedge clk);
|
| 501 |
|
|
m4.wb_rd_mult( 32'h0000_0400 + (siz * 4), 4'hf, del, siz);
|
| 502 |
|
|
repeat(del) @(posedge clk);
|
| 503 |
|
|
m4.wb_wr_mult( 32'h0000_0400 + (siz * 8), 4'hf, del, siz);
|
| 504 |
|
|
repeat(del) @(posedge clk);
|
| 505 |
|
|
m4.wb_rd_mult( 32'h0000_0400 + (siz * 12), 4'hf, del, siz);
|
| 506 |
|
|
t[4] = $time;
|
| 507 |
|
|
end
|
| 508 |
|
|
|
| 509 |
|
|
begin
|
| 510 |
|
|
repeat(del) @(posedge clk);
|
| 511 |
|
|
m5.wb_rd_mult( 32'h0000_0500 , 4'hf, del, siz);
|
| 512 |
|
|
repeat(del) @(posedge clk);
|
| 513 |
|
|
m5.wb_wr_mult( 32'h0000_0500 + (siz * 4), 4'hf, del, siz);
|
| 514 |
|
|
repeat(del) @(posedge clk);
|
| 515 |
|
|
m5.wb_rd_mult( 32'h0000_0500 + (siz * 8), 4'hf, del, siz);
|
| 516 |
|
|
repeat(del) @(posedge clk);
|
| 517 |
|
|
m5.wb_wr_mult( 32'h0000_0500 + (siz * 12), 4'hf, del, siz);
|
| 518 |
|
|
t[5] = $time;
|
| 519 |
|
|
end
|
| 520 |
|
|
|
| 521 |
|
|
begin
|
| 522 |
|
|
repeat(del) @(posedge clk);
|
| 523 |
|
|
m6.wb_wr_mult( 32'h0000_0600 , 4'hf, del, siz);
|
| 524 |
|
|
repeat(del) @(posedge clk);
|
| 525 |
|
|
m6.wb_rd_mult( 32'h0000_0600 + (siz * 4), 4'hf, del, siz);
|
| 526 |
|
|
repeat(del) @(posedge clk);
|
| 527 |
|
|
m6.wb_wr_mult( 32'h0000_0600 + (siz * 8), 4'hf, del, siz);
|
| 528 |
|
|
repeat(del) @(posedge clk);
|
| 529 |
|
|
m6.wb_rd_mult( 32'h0000_0600 + (siz * 12), 4'hf, del, siz);
|
| 530 |
|
|
t[6] = $time;
|
| 531 |
|
|
end
|
| 532 |
|
|
|
| 533 |
|
|
begin
|
| 534 |
|
|
repeat(del) @(posedge clk);
|
| 535 |
|
|
m7.wb_wr_mult( 32'h0000_0700 , 4'hf, del, siz);
|
| 536 |
|
|
repeat(del) @(posedge clk);
|
| 537 |
|
|
m7.wb_rd_mult( 32'h0000_0700 + (siz * 4), 4'hf, del, siz);
|
| 538 |
|
|
repeat(del) @(posedge clk);
|
| 539 |
|
|
m7.wb_wr_mult( 32'h0000_0700 + (siz * 8), 4'hf, del, siz);
|
| 540 |
|
|
repeat(del) @(posedge clk);
|
| 541 |
|
|
m7.wb_rd_mult( 32'h0000_0700 + (siz * 12), 4'hf, del, siz);
|
| 542 |
|
|
t[7] = $time;
|
| 543 |
|
|
end
|
| 544 |
|
|
|
| 545 |
|
|
join
|
| 546 |
|
|
|
| 547 |
|
|
verify(0,0,siz*4);
|
| 548 |
|
|
verify(1,0,siz*4);
|
| 549 |
|
|
verify(2,0,siz*4);
|
| 550 |
|
|
verify(3,0,siz*4);
|
| 551 |
|
|
verify(4,0,siz*4);
|
| 552 |
|
|
verify(5,0,siz*4);
|
| 553 |
|
|
verify(6,0,siz*4);
|
| 554 |
|
|
verify(7,0,siz*4);
|
| 555 |
|
|
|
| 556 |
|
|
for(a=0;a<8;a=a+1)
|
| 557 |
|
|
for(b=0;b<8;b=b+1)
|
| 558 |
|
|
if((t[a] < t[b]) & (p[a] <= p[b]) & (p[a] != p[b]) )
|
| 559 |
|
|
begin
|
| 560 |
|
|
$display("ERROR: Master %0d compleated before Master %0d", a, b);
|
| 561 |
|
|
$display(" M[%0d] pri: %0d (t: %0t)", a, p[a], t[a]);
|
| 562 |
|
|
$display(" M[%0d] pri: %0d (t: %0t)", b, p[b], t[b]);
|
| 563 |
|
|
error_cnt = error_cnt + 1;
|
| 564 |
|
|
end
|
| 565 |
|
|
end
|
| 566 |
|
|
|
| 567 |
|
|
show_errors;
|
| 568 |
|
|
$display("*****************************************************");
|
| 569 |
|
|
$display("*** Test DONE ... ***");
|
| 570 |
|
|
$display("*****************************************************\n\n");
|
| 571 |
|
|
|
| 572 |
|
|
end
|
| 573 |
|
|
endtask
|
| 574 |
|
|
|
| 575 |
|
|
|
| 576 |
|
|
|
| 577 |
|
|
task test_dp1;
|
| 578 |
|
|
|
| 579 |
|
|
integer n;
|
| 580 |
|
|
reg [3:0] s, s1, s2, s3, s4, s5, s6, s7;
|
| 581 |
|
|
|
| 582 |
|
|
begin
|
| 583 |
|
|
|
| 584 |
|
|
$display("\n\n");
|
| 585 |
|
|
$display("*****************************************************");
|
| 586 |
|
|
$display("*** Datapath 1 Test ... ***");
|
| 587 |
|
|
$display("*****************************************************\n");
|
| 588 |
|
|
|
| 589 |
|
|
s = 0;
|
| 590 |
|
|
|
| 591 |
|
|
for(n=0;n<8;n=n+1)
|
| 592 |
|
|
begin
|
| 593 |
|
|
init_all_mem;
|
| 594 |
|
|
$display("Mode: %0d", n);
|
| 595 |
|
|
|
| 596 |
|
|
begin
|
| 597 |
|
|
m0.wb_wr_mult( 32'h0000_0000 + (s << 28), 4'hf, 0, 4);
|
| 598 |
|
|
m0.wb_rd_mult( 32'h0000_0010 + (s << 28), 4'hf, 0, 4);
|
| 599 |
|
|
m0.wb_wr_mult( 32'h0000_0020 + (s << 28), 4'hf, 0, 4);
|
| 600 |
|
|
m0.wb_rd_mult( 32'h0000_0030 + (s << 28), 4'hf, 0, 4);
|
| 601 |
|
|
end
|
| 602 |
|
|
|
| 603 |
|
|
begin
|
| 604 |
|
|
m1.wb_wr_mult( 32'h0000_0100 + (s << 28), 4'hf, 0, 4);
|
| 605 |
|
|
m1.wb_rd_mult( 32'h0000_0110 + (s << 28), 4'hf, 0, 4);
|
| 606 |
|
|
m1.wb_wr_mult( 32'h0000_0120 + (s << 28), 4'hf, 0, 4);
|
| 607 |
|
|
m1.wb_rd_mult( 32'h0000_0130 + (s << 28), 4'hf, 0, 4);
|
| 608 |
|
|
end
|
| 609 |
|
|
|
| 610 |
|
|
begin
|
| 611 |
|
|
m2.wb_wr_mult( 32'h0000_0200 + (s << 28), 4'hf, 0, 4);
|
| 612 |
|
|
m2.wb_rd_mult( 32'h0000_0210 + (s << 28), 4'hf, 0, 4);
|
| 613 |
|
|
m2.wb_wr_mult( 32'h0000_0220 + (s << 28), 4'hf, 0, 4);
|
| 614 |
|
|
m2.wb_rd_mult( 32'h0000_0230 + (s << 28), 4'hf, 0, 4);
|
| 615 |
|
|
end
|
| 616 |
|
|
|
| 617 |
|
|
begin
|
| 618 |
|
|
m3.wb_wr_mult( 32'h0000_0300 + (s << 28), 4'hf, 0, 4);
|
| 619 |
|
|
m3.wb_rd_mult( 32'h0000_0310 + (s << 28), 4'hf, 0, 4);
|
| 620 |
|
|
m3.wb_wr_mult( 32'h0000_0320 + (s << 28), 4'hf, 0, 4);
|
| 621 |
|
|
m3.wb_rd_mult( 32'h0000_0330 + (s << 28), 4'hf, 0, 4);
|
| 622 |
|
|
end
|
| 623 |
|
|
|
| 624 |
|
|
begin
|
| 625 |
|
|
m4.wb_wr_mult( 32'h0000_0400 + (s << 28), 4'hf, 0, 4);
|
| 626 |
|
|
m4.wb_rd_mult( 32'h0000_0410 + (s << 28), 4'hf, 0, 4);
|
| 627 |
|
|
m4.wb_wr_mult( 32'h0000_0420 + (s << 28), 4'hf, 0, 4);
|
| 628 |
|
|
m4.wb_rd_mult( 32'h0000_0430 + (s << 28), 4'hf, 0, 4);
|
| 629 |
|
|
end
|
| 630 |
|
|
|
| 631 |
|
|
begin
|
| 632 |
|
|
m5.wb_wr_mult( 32'h0000_0500 + (s << 28), 4'hf, 0, 4);
|
| 633 |
|
|
m5.wb_rd_mult( 32'h0000_0510 + (s << 28), 4'hf, 0, 4);
|
| 634 |
|
|
m5.wb_wr_mult( 32'h0000_0520 + (s << 28), 4'hf, 0, 4);
|
| 635 |
|
|
m5.wb_rd_mult( 32'h0000_0530 + (s << 28), 4'hf, 0, 4);
|
| 636 |
|
|
end
|
| 637 |
|
|
|
| 638 |
|
|
begin
|
| 639 |
|
|
m6.wb_wr_mult( 32'h0000_0600 + (s << 28), 4'hf, 0, 4);
|
| 640 |
|
|
m6.wb_rd_mult( 32'h0000_0610 + (s << 28), 4'hf, 0, 4);
|
| 641 |
|
|
m6.wb_wr_mult( 32'h0000_0620 + (s << 28), 4'hf, 0, 4);
|
| 642 |
|
|
m6.wb_rd_mult( 32'h0000_0630 + (s << 28), 4'hf, 0, 4);
|
| 643 |
|
|
end
|
| 644 |
|
|
|
| 645 |
|
|
begin
|
| 646 |
|
|
m7.wb_wr_mult( 32'h0000_0700 + (s << 28), 4'hf, 0, 4);
|
| 647 |
|
|
m7.wb_rd_mult( 32'h0000_0710 + (s << 28), 4'hf, 0, 4);
|
| 648 |
|
|
m7.wb_wr_mult( 32'h0000_0720 + (s << 28), 4'hf, 0, 4);
|
| 649 |
|
|
m7.wb_rd_mult( 32'h0000_0730 + (s << 28), 4'hf, 0, 4);
|
| 650 |
|
|
end
|
| 651 |
|
|
|
| 652 |
|
|
|
| 653 |
|
|
verify(0,s,16);
|
| 654 |
|
|
verify(1,s,16);
|
| 655 |
|
|
verify(2,s,16);
|
| 656 |
|
|
verify(3,s,16);
|
| 657 |
|
|
verify(4,s,16);
|
| 658 |
|
|
verify(5,s,16);
|
| 659 |
|
|
verify(6,s,16);
|
| 660 |
|
|
verify(7,s,16);
|
| 661 |
|
|
|
| 662 |
|
|
@(posedge clk);
|
| 663 |
|
|
|
| 664 |
|
|
s = s + 1;
|
| 665 |
|
|
// s1 = s1 + 1;
|
| 666 |
|
|
// s2 = s2 + 1;
|
| 667 |
|
|
// s3 = s3 + 1;
|
| 668 |
|
|
// s4 = s4 - 1;
|
| 669 |
|
|
// s5 = s5 - 1;
|
| 670 |
|
|
// s6 = s6 - 1;
|
| 671 |
|
|
// s7 = s7 - 1;
|
| 672 |
|
|
|
| 673 |
|
|
@(posedge clk);
|
| 674 |
|
|
|
| 675 |
|
|
end
|
| 676 |
|
|
|
| 677 |
|
|
show_errors;
|
| 678 |
|
|
$display("*****************************************************");
|
| 679 |
|
|
$display("*** Test DONE ... ***");
|
| 680 |
|
|
$display("*****************************************************\n\n");
|
| 681 |
|
|
|
| 682 |
|
|
end
|
| 683 |
|
|
endtask
|
| 684 |
|
|
|
| 685 |
|
|
task test_dp2;
|
| 686 |
|
|
|
| 687 |
|
|
integer del;
|
| 688 |
|
|
integer x0, x1, x2, x3, x4, x5, x6, x7;
|
| 689 |
|
|
reg [3:0] m;
|
| 690 |
|
|
|
| 691 |
|
|
begin
|
| 692 |
|
|
|
| 693 |
|
|
$display("\n\n");
|
| 694 |
|
|
$display("*****************************************************");
|
| 695 |
|
|
$display("*** Datapath 2 Test ... ***");
|
| 696 |
|
|
$display("*****************************************************\n");
|
| 697 |
|
|
|
| 698 |
|
|
del=0;
|
| 699 |
|
|
for(del=0;del<5;del=del+1)
|
| 700 |
|
|
begin
|
| 701 |
|
|
init_all_mem;
|
| 702 |
|
|
$display("Delay: %0d", del);
|
| 703 |
|
|
|
| 704 |
|
|
// fork
|
| 705 |
|
|
|
| 706 |
|
|
begin
|
| 707 |
|
|
for(x0=0;x0<8;x0=x0+1)
|
| 708 |
|
|
m0.wb_rd_mult( 32'h0000_0000 + ((0+x0) << 28) + (x0<<4), 4'hf, del, 4);
|
| 709 |
|
|
end
|
| 710 |
|
|
|
| 711 |
|
|
begin
|
| 712 |
|
|
for(x1=0;x1<8;x1=x1+1)
|
| 713 |
|
|
m1.wb_rd_mult( 32'h0000_0100 + ((0+x1) << 28) + (x1<<4), 4'hf, del, 4);
|
| 714 |
|
|
end
|
| 715 |
|
|
|
| 716 |
|
|
begin
|
| 717 |
|
|
for(x2=0;x2<8;x2=x2+1)
|
| 718 |
|
|
m2.wb_rd_mult( 32'h0000_0200 + ((0+x2) << 28) + (x2<<4), 4'hf, del, 4);
|
| 719 |
|
|
|
| 720 |
|
|
end
|
| 721 |
|
|
|
| 722 |
|
|
begin
|
| 723 |
|
|
for(x3=0;x3<8;x3=x3+1)
|
| 724 |
|
|
m3.wb_rd_mult( 32'h0000_0300 + ((0+x3) << 28) + (x3<<4), 4'hf, del, 4);
|
| 725 |
|
|
end
|
| 726 |
|
|
|
| 727 |
|
|
begin
|
| 728 |
|
|
for(x4=0;x4<8;x4=x4+1)
|
| 729 |
|
|
m4.wb_rd_mult( 32'h0000_0400 + ((0+x4) << 28) + (x4<<4), 4'hf, del, 4);
|
| 730 |
|
|
end
|
| 731 |
|
|
|
| 732 |
|
|
begin
|
| 733 |
|
|
for(x5=0;x5<8;x5=x5+1)
|
| 734 |
|
|
m5.wb_rd_mult( 32'h0000_0500 + ((0+x5) << 28) + (x5<<4), 4'hf, del, 4);
|
| 735 |
|
|
end
|
| 736 |
|
|
|
| 737 |
|
|
begin
|
| 738 |
|
|
for(x6=0;x6<8;x6=x6+1)
|
| 739 |
|
|
m6.wb_rd_mult( 32'h0000_0600 + ((0+x6) << 28) + (x6<<4), 4'hf, del, 4);
|
| 740 |
|
|
end
|
| 741 |
|
|
|
| 742 |
|
|
begin
|
| 743 |
|
|
for(x7=0;x7<8;x7=x7+1)
|
| 744 |
|
|
m7.wb_rd_mult( 32'h0000_0700 + ((0+x7) << 28) + (x7<<4), 4'hf, del, 4);
|
| 745 |
|
|
end
|
| 746 |
|
|
// join
|
| 747 |
|
|
|
| 748 |
|
|
for(x1=0;x1<8;x1=x1+1)
|
| 749 |
|
|
for(x0=0;x0<8;x0=x0+1)
|
| 750 |
|
|
begin
|
| 751 |
|
|
// m = x0+x1;
|
| 752 |
|
|
verify_sub(x1,x0,4,(x0*4),(x0*4));
|
| 753 |
|
|
end
|
| 754 |
|
|
|
| 755 |
|
|
end
|
| 756 |
|
|
|
| 757 |
|
|
show_errors;
|
| 758 |
|
|
$display("*****************************************************");
|
| 759 |
|
|
$display("*** Test DONE ... ***");
|
| 760 |
|
|
$display("*****************************************************\n\n");
|
| 761 |
|
|
|
| 762 |
|
|
end
|
| 763 |
|
|
endtask
|
| 764 |
|
|
|
| 765 |
|
|
|
| 766 |
|
|
task test_rf;
|
| 767 |
|
|
|
| 768 |
|
|
integer n, m;
|
| 769 |
|
|
reg [31:0] wdata[0:15];
|
| 770 |
|
|
reg [31:0] rdata[0:15];
|
| 771 |
|
|
reg [15:0] rtmp, wtmp;
|
| 772 |
|
|
|
| 773 |
|
|
begin
|
| 774 |
|
|
|
| 775 |
|
|
$display("\n\n");
|
| 776 |
|
|
$display("*****************************************************");
|
| 777 |
|
|
$display("*** Register File Test ... ***");
|
| 778 |
|
|
$display("*****************************************************\n");
|
| 779 |
|
|
|
| 780 |
|
|
for(m=0;m<5;m=m+1)
|
| 781 |
|
|
begin
|
| 782 |
|
|
$display("Mode: %0d", m);
|
| 783 |
|
|
|
| 784 |
|
|
for(n=0;n<16;n=n+1)
|
| 785 |
|
|
wdata[n] = $random;
|
| 786 |
|
|
|
| 787 |
|
|
for(n=0;n<16;n=n+1)
|
| 788 |
|
|
case(m)
|
| 789 |
|
|
0: m0.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
|
| 790 |
|
|
1: m3.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
|
| 791 |
|
|
2: m5.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
|
| 792 |
|
|
3: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
|
| 793 |
|
|
4: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
|
| 794 |
|
|
endcase
|
| 795 |
|
|
|
| 796 |
|
|
for(n=0;n<16;n=n+1)
|
| 797 |
|
|
case(m)
|
| 798 |
|
|
0: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
|
| 799 |
|
|
1: m3.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
|
| 800 |
|
|
2: m6.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
|
| 801 |
|
|
3: m0.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
|
| 802 |
|
|
4: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
|
| 803 |
|
|
endcase
|
| 804 |
|
|
|
| 805 |
|
|
for(n=0;n<16;n=n+1)
|
| 806 |
|
|
begin
|
| 807 |
|
|
rtmp = rdata[n];
|
| 808 |
|
|
wtmp = wdata[n];
|
| 809 |
|
|
if(rtmp !== wtmp)
|
| 810 |
|
|
begin
|
| 811 |
|
|
$display("ERROR: RF[%0d] Mismatch. Expected: %h, Got: %h (%0t)",
|
| 812 |
|
|
n, wtmp, rtmp, $time);
|
| 813 |
|
|
end
|
| 814 |
|
|
end
|
| 815 |
|
|
end
|
| 816 |
|
|
|
| 817 |
|
|
show_errors;
|
| 818 |
|
|
$display("*****************************************************");
|
| 819 |
|
|
$display("*** Test DONE ... ***");
|
| 820 |
|
|
$display("*****************************************************\n\n");
|
| 821 |
|
|
|
| 822 |
|
|
|
| 823 |
|
|
end
|
| 824 |
|
|
endtask
|
| 825 |
|
|
|
