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[/] [wb_conbus/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 6

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.1.1.1 2003-04-19 08:40:15 johny Exp $
//
//  $Date: 2003-04-19 08:40:15 $
//  $Revision: 1.1.1.1 $
//  $Author: johny $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/10/03 05:40:03  rudi
//               Fixed a minor bug in parameter passing, updated headers and specification.
//
//               Revision 1.1.1.1  2001/10/19 11:04:23  rudi
//               WISHBONE CONMAX IP Core
//
//
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   mem[mem_size:0];
integer         cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
 
task mem_fill;
 
integer n;
begin
cnt = 0;
cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
adr = $random;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
adr = $random;
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        //adr = 32'hxxxx_xxxx;
        adr = $random;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
cnt = cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
//      if(n!=0)
                @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + wcount;
end
endtask
 
 
 
 
task wb_wmr;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
        @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cnt = cnt + wcount;
stb=0;
repeat(delay)   @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
cnt = cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
 
cyc = 0;
stb = 0;
we  = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
adr = $random;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = $random;
end
endtask
 
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        //adr = 32'hxxxx_xxxx;
        adr = $random;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
//adr = 32'hffff_ffff;
//adr = 32'hxxxx_xxxx;
adr = $random;
 
cnt = cnt + count;
end
endtask
 
endmodule

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Subversion Repositories wb_conbus

[/] [wb_conbus/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	johny	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
13			`//// www.asics.ws ////`
14			`//// rudi@asics.ws ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer.////`
20			`//// ////`
21			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
22			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
23			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
24			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
25			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
26			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
27			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
28			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
29			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
30			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
31			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
32			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
33			`//// POSSIBILITY OF SUCH DAMAGE. ////`
34			`//// ////`
35			`/////////////////////////////////////////////////////////////////////`
36
37			`// CVS Log`
38			`//`
39			`// $Id: wb_mast_model.v,v 1.1.1.1 2003-04-19 08:40:15 johny Exp $`
40			`//`
41			`// $Date: 2003-04-19 08:40:15 $`
42			`// $Revision: 1.1.1.1 $`
43			`// $Author: johny $`
44			`// $Locker: $`
45			`// $State: Exp $`
46			`//`
47			`// Change History:`
48			`// $Log: not supported by cvs2svn $`
49			`// Revision 1.2 2002/10/03 05:40:03 rudi`
50			`// Fixed a minor bug in parameter passing, updated headers and specification.`
51			`//`
52			`// Revision 1.1.1.1 2001/10/19 11:04:23 rudi`
53			`// WISHBONE CONMAX IP Core`
54			`//`
55			`//`
56			`//`
57			`//`
58			`//`
59
60			`include "wb_model_defines.v"
61
62			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
63
64			`input clk, rst;`
65			`output [31:0] adr;`
66			`input [31:0] din;`
67			`output [31:0] dout;`
68			`output cyc, stb;`
69			`output [3:0] sel;`
70			`output we;`
71			`input ack, err, rty;`
72
73			`////////////////////////////////////////////////////////////////////`
74			`//`
75			`// Local Wires`
76			`//`
77
78			`parameter mem_size = 4096;`
79
80			`reg [31:0] adr;`
81			`reg [31:0] dout;`
82			`reg cyc, stb;`
83			`reg [3:0] sel;`
84			`reg we;`
85
86			`reg [31:0] mem[mem_size:0];`
87			`integer cnt;`
88
89			`////////////////////////////////////////////////////////////////////`
90			`//`
91			`// Memory Logic`
92			`//`
93
94			`initial`
95			`begin`
96			`//adr = 32'hxxxx_xxxx;`
97			`//adr = 0;`
98			`adr = 32'hffff_ffff;`
99			`dout = 32'hxxxx_xxxx;`
100			`cyc = 0;`
101			`stb = 0;`
102			`sel = 4'hx;`
103			`we = 1'hx;`
104			`cnt = 0;`
105			`#1;`
106			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
107			`end`
108
109
110
111			`task mem_fill;`
112
113			`integer n;`
114			`begin`
115			`cnt = 0;`
116			`cnt = 0;`
117			`for(n=0;n<mem_size;n=n+1)`
118			`begin`
119			`mem[n] = $random;`
120			`end`
121			`end`
122			`endtask`
123
124			`////////////////////////////////////////////////////////////////////`
125			`//`
126			`// Write 1 Word Task`
127			`//`
128
129			`task wb_wr1;`
130			`input [31:0] a;`
131			`input [3:0] s;`
132			`input [31:0] d;`
133
134			`begin`
135
136			`//@(posedge clk);`
137			`#1;`
138			`adr = a;`
139			`dout = d;`
140			`cyc = 1;`
141			`stb = 1;`
142			`we=1;`
143			`sel = s;`
144
145			`@(posedge clk);`
146			`while(~ack & ~err) @(posedge clk);`
147			`#1;`
148			`cyc=0;`
149			`stb=0;`
150			`adr = 32'hxxxx_xxxx;`
151			`//adr = 32'hffff_ffff;`
152			`//adr = 0;`
153			`dout = 32'hxxxx_xxxx;`
154			`we = 1'hx;`
155			`sel = 4'hx;`
156			`adr = $random;`
157
158			`end`
159			`endtask`
160
161			`////////////////////////////////////////////////////////////////////`
162			`//`
163			`// Write 4 Words Task`
164			`//`
165
166			`task wb_wr4;`
167			`input [31:0] a;`
168			`input [3:0] s;`
169			`input delay;`
170			`input [31:0] d1;`
171			`input [31:0] d2;`
172			`input [31:0] d3;`
173			`input [31:0] d4;`
174
175			`integer delay;`
176
177			`begin`
178
179			`@(posedge clk);`
180			`#1;`
181			`cyc = 1;`
182			`sel = s;`
183
184			`adr = $random;`
185			`repeat(delay)`
186			`begin`
187			`@(posedge clk);`
188			`#1;`
189			`end`
190			`adr = a;`
191			`dout = d1;`
192			`stb = 1;`
193			`we=1;`
194			`while(~ack & ~err) @(posedge clk);`
195			`#2;`
196			`stb=0;`
197			`we=1'bx;`
198			`dout = 32'hxxxx_xxxx;`
199			`adr = $random;`
200
201
202			`repeat(delay)`
203			`begin`
204			`@(posedge clk);`
205			`#1;`
206			`end`
207			`stb=1;`
208			`adr = a+4;`
209			`dout = d2;`
210			`we=1;`
211			`@(posedge clk);`
212			`while(~ack & ~err) @(posedge clk);`
213			`#2;`
214			`stb=0;`
215			`we=1'bx;`
216			`dout = 32'hxxxx_xxxx;`
217
218			`repeat(delay)`
219			`begin`
220			`@(posedge clk);`
221			`#1;`
222			`end`
223			`stb=1;`
224			`adr = a+8;`
225			`dout = d3;`
226			`we=1;`
227			`@(posedge clk);`
228			`while(~ack & ~err) @(posedge clk);`
229			`#2;`
230			`stb=0;`
231			`we=1'bx;`
232			`dout = 32'hxxxx_xxxx;`
233			`adr = $random;`
234
235			`repeat(delay)`
236			`begin`
237			`@(posedge clk);`
238			`#1;`
239			`end`
240			`stb=1;`
241			`adr = a+12;`
242			`dout = d4;`
243			`we=1;`
244			`@(posedge clk);`
245			`while(~ack & ~err) @(posedge clk);`
246			`#1;`
247			`stb=0;`
248			`cyc=0;`
249
250			`adr = 32'hxxxx_xxxx;`
251			`adr = $random;`
252			`//adr = 0;`
253			`//adr = 32'hffff_ffff;`
254			`dout = 32'hxxxx_xxxx;`
255			`we = 1'hx;`
256			`sel = 4'hx;`
257
258			`end`
259			`endtask`
260
261
262			`task wb_wr_mult;`
263			`input [31:0] a;`
264			`input [3:0] s;`
265			`input delay;`
266			`input count;`
267
268			`integer delay;`
269			`integer count;`
270			`integer n;`
271
272			`begin`
273
274			`//@(posedge clk);`
275			`#1;`
276			`cyc = 1;`
277			`adr = $random;`
278			`for(n=0;n<count;n=n+1)`
279			`begin`
280			`repeat(delay)`
281			`begin`
282			`@(posedge clk);`
283			`#1;`
284			`end`
285			`adr = a + (n*4);`
286			`dout = mem[n + cnt];`
287			`stb = 1;`
288			`we=1;`
289			`sel = s;`
290			`if(n!=0) @(posedge clk);`
291			`while(~ack & ~err) @(posedge clk);`
292			`#2;`
293			`stb=0;`
294			`we=1'bx;`
295			`sel = 4'hx;`
296			`dout = 32'hxxxx_xxxx;`
297			`//adr = 32'hxxxx_xxxx;`
298			`adr = $random;`
299			`end`
300
301			`cyc=0;`
302
303			`adr = 32'hxxxx_xxxx;`
304			`//adr = 32'hffff_ffff;`
305
306			`cnt = cnt + count;`
307			`end`
308			`endtask`
309
310
311			`task wb_rmw;`
312			`input [31:0] a;`
313			`input [3:0] s;`
314			`input delay;`
315			`input rcount;`
316			`input wcount;`
317
318			`integer delay;`
319			`integer rcount;`
320			`integer wcount;`
321			`integer n;`
322
323			`begin`
324
325			`@(posedge clk);`
326			`#1;`
327			`cyc = 1;`
328			`we = 0;`
329			`sel = s;`
330			`repeat(delay) @(posedge clk);`
331
332			`for(n=0;n<rcount-1;n=n+1)`
333			`begin`
334			`adr = a + (n*4);`
335			`stb = 1;`
336			`while(~ack & ~err) @(posedge clk);`
337			`mem[n + cnt] = din;`
338			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
339			`#2;`
340			`stb=0;`
341			`we = 1'hx;`
342			`sel = 4'hx;`
343			`adr = 32'hxxxx_xxxx;`
344			`repeat(delay)`
345			`begin`
346			`@(posedge clk);`
347			`#1;`
348			`end`
349			`we = 0;`
350			`sel = s;`
351			`end`
352
353			`adr = a+(n*4);`
354			`stb = 1;`
355			`@(posedge clk);`
356			`while(~ack & ~err) @(posedge clk);`
357			`mem[n + cnt] = din;`
358			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
359			`#1;`
360			`stb=0;`
361			`we = 1'hx;`
362			`sel = 4'hx;`
363			`adr = 32'hxxxx_xxxx;`
364
365			`cnt = cnt + rcount;`
366
367			`//@(posedge clk);`
368
369
370			`for(n=0;n<wcount;n=n+1)`
371			`begin`
372			`repeat(delay)`
373			`begin`
374			`@(posedge clk);`
375			`#1;`
376			`end`
377			`adr = a + (n*4);`
378			`dout = mem[n + cnt];`
379			`stb = 1;`
380			`we=1;`
381			`sel = s;`
382			`// if(n!=0)`
383			`@(posedge clk);`
384			`while(~ack & ~err) @(posedge clk);`
385			`#2;`
386			`stb=0;`
387			`we=1'bx;`
388			`sel = 4'hx;`
389			`dout = 32'hxxxx_xxxx;`
390			`adr = 32'hxxxx_xxxx;`
391			`end`
392
393			`cyc=0;`
394
395			`adr = 32'hxxxx_xxxx;`
396			`//adr = 32'hffff_ffff;`
397
398			`cnt = cnt + wcount;`
399			`end`
400			`endtask`
401
402
403
404
405			`task wb_wmr;`
406			`input [31:0] a;`
407			`input [3:0] s;`
408			`input delay;`
409			`input rcount;`
410			`input wcount;`
411
412			`integer delay;`
413			`integer rcount;`
414			`integer wcount;`
415			`integer n;`
416
417			`begin`
418
419			`@(posedge clk);`
420			`#1;`
421			`cyc = 1;`
422			`we = 1'bx;`
423			`sel = 4'hx;`
424			`sel = s;`
425
426			`for(n=0;n<wcount;n=n+1)`
427			`begin`
428			`repeat(delay)`
429			`begin`
430			`@(posedge clk);`
431			`#1;`
432			`end`
433			`adr = a + (n*4);`
434			`dout = mem[n + cnt];`
435			`stb = 1;`
436			`we=1;`
437			`sel = s;`
438			`@(posedge clk);`
439			`while(~ack & ~err) @(posedge clk);`
440			`#2;`
441			`stb=0;`
442			`we=1'bx;`
443			`sel = 4'hx;`
444			`dout = 32'hxxxx_xxxx;`
445			`adr = 32'hxxxx_xxxx;`
446			`end`
447
448			`cnt = cnt + wcount;`
449			`stb=0;`
450			`repeat(delay) @(posedge clk);`
451			`#1;`
452
453			`sel = s;`
454			`we = 0;`
455			`for(n=0;n<rcount-1;n=n+1)`
456			`begin`
457			`adr = a + (n*4);`
458			`stb = 1;`
459			`while(~ack & ~err) @(posedge clk);`
460			`mem[n + cnt] = din;`
461			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
462			`#2;`
463			`stb=0;`
464			`we = 1'hx;`
465			`sel = 4'hx;`
466			`adr = 32'hxxxx_xxxx;`
467			`repeat(delay)`
468			`begin`
469			`@(posedge clk);`
470			`#1;`
471			`end`
472			`we = 0;`
473			`sel = s;`
474			`end`
475
476			`adr = a+(n*4);`
477			`stb = 1;`
478			`@(posedge clk);`
479			`while(~ack & ~err) @(posedge clk);`
480			`mem[n + cnt] = din;`
481			`cnt = cnt + rcount;`
482			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
483			`#1;`
484
485			`cyc = 0;`
486			`stb = 0;`
487			`we = 1'hx;`
488			`sel = 4'hx;`
489			`adr = 32'hxxxx_xxxx;`
490
491			`end`
492			`endtask`
493
494
495
496
497			`////////////////////////////////////////////////////////////////////`
498			`//`
499			`// Read 1 Word Task`
500			`//`
501
502			`task wb_rd1;`
503			`input [31:0] a;`
504			`input [3:0] s;`
505			`output [31:0] d;`
506
507			`begin`
508
509			`//@(posedge clk);`
510			`#1;`
511			`adr = a;`
512			`cyc = 1;`
513			`stb = 1;`
514			`we = 0;`
515			`sel = s;`
516
517			`//@(posedge clk);`
518			`while(~ack & ~err) @(posedge clk);`
519			`d = din;`
520			`#1;`
521			`cyc=0;`
522			`stb=0;`
523			`//adr = 32'hxxxx_xxxx;`
524			`//adr = 0;`
525			`adr = 32'hffff_ffff;`
526			`dout = 32'hxxxx_xxxx;`
527			`we = 1'hx;`
528			`sel = 4'hx;`
529			`adr = $random;`
530
531			`end`
532			`endtask`
533
534
535			`////////////////////////////////////////////////////////////////////`
536			`//`
537			`// Read 4 Words Task`
538			`//`
539
540
541			`task wb_rd4;`
542			`input [31:0] a;`
543			`input [3:0] s;`
544			`input delay;`
545			`output [31:0] d1;`
546			`output [31:0] d2;`
547			`output [31:0] d3;`
548			`output [31:0] d4;`
549
550			`integer delay;`
551			`begin`
552
553			`@(posedge clk);`
554			`#1;`
555			`cyc = 1;`
556			`we = 0;`
557			`adr = $random;`
558			`sel = s;`
559			`repeat(delay) @(posedge clk);`
560
561			`adr = a;`
562			`stb = 1;`
563			`while(~ack & ~err) @(posedge clk);`
564			`d1 = din;`
565			`#2;`
566			`stb=0;`
567			`we = 1'hx;`
568			`sel = 4'hx;`
569			`adr = $random;`
570			`repeat(delay)`
571			`begin`
572			`@(posedge clk);`
573			`#1;`
574			`end`
575			`we = 0;`
576			`sel = s;`
577
578			`adr = a+4;`
579			`stb = 1;`
580			`@(posedge clk);`
581			`while(~ack & ~err) @(posedge clk);`
582			`d2 = din;`
583			`#2;`
584			`stb=0;`
585			`we = 1'hx;`
586			`sel = 4'hx;`
587			`adr = $random;`
588			`repeat(delay)`
589			`begin`
590			`@(posedge clk);`
591			`#1;`
592			`end`
593			`we = 0;`
594			`sel = s;`
595
596
597			`adr = a+8;`
598			`stb = 1;`
599			`@(posedge clk);`
600			`while(~ack & ~err) @(posedge clk);`
601			`d3 = din;`
602			`#2;`
603			`stb=0;`
604			`we = 1'hx;`
605			`sel = 4'hx;`
606			`adr = $random;`
607			`repeat(delay)`
608			`begin`
609			`@(posedge clk);`
610			`#1;`
611			`end`
612			`we = 0;`
613			`sel = s;`
614
615			`adr = a+12;`
616			`stb = 1;`
617			`@(posedge clk);`
618			`while(~ack & ~err) @(posedge clk);`
619			`d4 = din;`
620			`#1;`
621			`stb=0;`
622			`cyc=0;`
623			`we = 1'hx;`
624			`sel = 4'hx;`
625			`adr = 32'hffff_ffff;`
626			`adr = $random;`
627			`end`
628			`endtask`
629
630
631
632			`task wb_rd_mult;`
633			`input [31:0] a;`
634			`input [3:0] s;`
635			`input delay;`
636			`input count;`
637
638			`integer delay;`
639			`integer count;`
640			`integer n;`
641
642			`begin`
643
644			`//@(posedge clk);`
645			`#1;`
646			`cyc = 1;`
647			`we = 0;`
648			`sel = s;`
649			`repeat(delay) @(posedge clk);`
650
651			`for(n=0;n<count-1;n=n+1)`
652			`begin`
653			`adr = a + (n*4);`
654			`stb = 1;`
655			`while(~ack & ~err) @(posedge clk);`
656			`mem[n + cnt] = din;`
657			`#2;`
658			`stb=0;`
659			`we = 1'hx;`
660			`sel = 4'hx;`
661			`//adr = 32'hxxxx_xxxx;`
662			`adr = $random;`
663			`repeat(delay)`
664			`begin`
665			`@(posedge clk);`
666			`#1;`
667			`end`
668			`we = 0;`
669			`sel = s;`
670			`end`
671
672			`adr = a+(n*4);`
673			`stb = 1;`
674			`@(posedge clk);`
675			`while(~ack & ~err) @(posedge clk);`
676			`mem[n + cnt] = din;`
677			`#1;`
678			`stb=0;`
679			`cyc=0;`
680			`we = 1'hx;`
681			`sel = 4'hx;`
682			`//adr = 32'hffff_ffff;`
683			`//adr = 32'hxxxx_xxxx;`
684			`adr = $random;`
685
686			`cnt = cnt + count;`
687			`end`
688			`endtask`
689
690			`endmodule`