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[/] [wb_conmax/] [trunk/] [rtl/] [verilog/] [wb_conmax_rf.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Connection Matrix Register File                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_ic/     ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_conmax_rf.v,v 1.1.1.1 2001-10-19 11:01:42 rudi Exp $
//
//  $Date: 2001-10-19 11:01:42 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
 
`include "wb_conmax_defines.v"
 
module wb_conmax_rf(
                clk_i, rst_i,
 
                // Internal Wishbone Interface
                i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,
                i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,
 
                // External Wishbone Interface
                e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,
                e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,
 
                // Configuration Registers
                conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,
                conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15
 
                );
 
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
 
parameter       [3:0]    rf_addr = 4'hf;
parameter               dw      = 32;           // Data bus Width
parameter               aw      = 32;           // Address bus Width
parameter               sw      = dw / 8;       // Number of Select Lines
 
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
 
input           clk_i, rst_i;
 
// Internal Wishbone Interface
input   [dw-1:0] i_wb_data_i;
output  [dw-1:0] i_wb_data_o;
input   [aw-1:0] i_wb_addr_i;
input   [sw-1:0] i_wb_sel_i;
input                   i_wb_we_i;
input                   i_wb_cyc_i;
input                   i_wb_stb_i;
output                  i_wb_ack_o;
output                  i_wb_err_o;
output                  i_wb_rty_o;
 
// External Wishbone Interface
input   [dw-1:0] e_wb_data_i;
output  [dw-1:0] e_wb_data_o;
output  [aw-1:0] e_wb_addr_o;
output  [sw-1:0] e_wb_sel_o;
output                  e_wb_we_o;
output                  e_wb_cyc_o;
output                  e_wb_stb_o;
input                   e_wb_ack_i;
input                   e_wb_err_i;
input                   e_wb_rty_i;
 
// Configuration Registers
output  [15:0]           conf0;
output  [15:0]           conf1;
output  [15:0]           conf2;
output  [15:0]           conf3;
output  [15:0]           conf4;
output  [15:0]           conf5;
output  [15:0]           conf6;
output  [15:0]           conf7;
output  [15:0]           conf8;
output  [15:0]           conf9;
output  [15:0]           conf10;
output  [15:0]           conf11;
output  [15:0]           conf12;
output  [15:0]           conf13;
output  [15:0]           conf14;
output  [15:0]           conf15;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [15:0]   conf0, conf1, conf2, conf3, conf4, conf5;
reg     [15:0]   conf6, conf7, conf8, conf9, conf10, conf11;
reg     [15:0]   conf12, conf13, conf14, conf15;
 
//synopsys infer_multibit "conf0"
//synopsys infer_multibit "conf1"
//synopsys infer_multibit "conf2"
//synopsys infer_multibit "conf3"
//synopsys infer_multibit "conf4"
//synopsys infer_multibit "conf5"
//synopsys infer_multibit "conf6"
//synopsys infer_multibit "conf7"
//synopsys infer_multibit "conf8"
//synopsys infer_multibit "conf9"
//synopsys infer_multibit "conf10"
//synopsys infer_multibit "conf11"
//synopsys infer_multibit "conf12"
//synopsys infer_multibit "conf13"
//synopsys infer_multibit "conf14"
//synopsys infer_multibit "conf15"
 
wire            rf_sel;
reg     [15:0]   rf_dout;
reg             rf_ack;
reg             rf_we;
 
////////////////////////////////////////////////////////////////////
//
// Register File Select Logic
//
 
assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);
 
////////////////////////////////////////////////////////////////////
//
// Register File Logic
//
 
always @(posedge clk_i)
        rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;
 
always @(posedge clk_i)
        rf_ack <= #1 rf_sel & !rf_ack;
 
// Writre Logic
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf0 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd0) )         conf0 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf1 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd1) )         conf1 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf2 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd2) )         conf2 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf3 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd3) )         conf3 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf4 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd4) )         conf4 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf5 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd5) )         conf5 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf6 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd6) )         conf6 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf7 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd7) )         conf7 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf8 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd8) )         conf8 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf9 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd9) )         conf9 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf10 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd10) )        conf10 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf11 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd11) )        conf11 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf12 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd12) )        conf12 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf13 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd13) )        conf13 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf14 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd14) )        conf14 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf15 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd15) )        conf15 <= #1 i_wb_data_i[15:0];
 
// Read Logic
always @(posedge clk_i)
        if(!rf_sel)     rf_dout <= #1 16'h0;
        else
        case(i_wb_addr_i[5:2])
           4'd0:        rf_dout <= #1 conf0;
           4'd1:        rf_dout <= #1 conf1;
           4'd2:        rf_dout <= #1 conf2;
           4'd3:        rf_dout <= #1 conf3;
           4'd4:        rf_dout <= #1 conf4;
           4'd5:        rf_dout <= #1 conf5;
           4'd6:        rf_dout <= #1 conf6;
           4'd7:        rf_dout <= #1 conf7;
           4'd8:        rf_dout <= #1 conf8;
           4'd9:        rf_dout <= #1 conf9;
           4'd10:       rf_dout <= #1 conf10;
           4'd11:       rf_dout <= #1 conf11;
           4'd12:       rf_dout <= #1 conf12;
           4'd13:       rf_dout <= #1 conf13;
           4'd14:       rf_dout <= #1 conf14;
           4'd15:       rf_dout <= #1 conf15;
        endcase
 
////////////////////////////////////////////////////////////////////
//
// Register File By-Pass Logic
//
 
assign e_wb_addr_o = i_wb_addr_i;
assign e_wb_sel_o  = i_wb_sel_i;
assign e_wb_data_o = i_wb_data_i;
 
assign e_wb_cyc_o  = rf_sel ? 1'b0 : i_wb_cyc_i;
assign e_wb_stb_o  = i_wb_stb_i;
assign e_wb_we_o   = i_wb_we_i;
 
assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;
assign i_wb_ack_o  = rf_sel ? rf_ack  : e_wb_ack_i;
assign i_wb_err_o  = rf_sel ? 1'b0    : e_wb_err_i;
assign i_wb_rty_o  = rf_sel ? 1'b0    : e_wb_rty_i;
 
endmodule

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Subversion Repositories wb_conmax

[/] [wb_conmax/] [trunk/] [rtl/] [verilog/] [wb_conmax_rf.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Connection Matrix Register File ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_ic/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_conmax_rf.v,v 1.1.1.1 2001-10-19 11:01:42 rudi Exp $`
41			`//`
42			`// $Date: 2001-10-19 11:01:42 $`
43			`// $Revision: 1.1.1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53			`//`
54
55			`include "wb_conmax_defines.v"
56
57			`module wb_conmax_rf(`
58			`clk_i, rst_i,`
59
60			`// Internal Wishbone Interface`
61			`i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,`
62			`i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,`
63
64			`// External Wishbone Interface`
65			`e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,`
66			`e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,`
67
68			`// Configuration Registers`
69			`conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,`
70			`conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15`
71
72			`);`
73
74			`////////////////////////////////////////////////////////////////////`
75			`//`
76			`// Module Parameters`
77			`//`
78
79			`parameter [3:0] rf_addr = 4'hf;`
80			`parameter dw = 32; // Data bus Width`
81			`parameter aw = 32; // Address bus Width`
82			`parameter sw = dw / 8; // Number of Select Lines`
83
84			`////////////////////////////////////////////////////////////////////`
85			`//`
86			`// Module IOs`
87			`//`
88
89			`input clk_i, rst_i;`
90
91			`// Internal Wishbone Interface`
92			`input [dw-1:0] i_wb_data_i;`
93			`output [dw-1:0] i_wb_data_o;`
94			`input [aw-1:0] i_wb_addr_i;`
95			`input [sw-1:0] i_wb_sel_i;`
96			`input i_wb_we_i;`
97			`input i_wb_cyc_i;`
98			`input i_wb_stb_i;`
99			`output i_wb_ack_o;`
100			`output i_wb_err_o;`
101			`output i_wb_rty_o;`
102
103			`// External Wishbone Interface`
104			`input [dw-1:0] e_wb_data_i;`
105			`output [dw-1:0] e_wb_data_o;`
106			`output [aw-1:0] e_wb_addr_o;`
107			`output [sw-1:0] e_wb_sel_o;`
108			`output e_wb_we_o;`
109			`output e_wb_cyc_o;`
110			`output e_wb_stb_o;`
111			`input e_wb_ack_i;`
112			`input e_wb_err_i;`
113			`input e_wb_rty_i;`
114
115			`// Configuration Registers`
116			`output [15:0] conf0;`
117			`output [15:0] conf1;`
118			`output [15:0] conf2;`
119			`output [15:0] conf3;`
120			`output [15:0] conf4;`
121			`output [15:0] conf5;`
122			`output [15:0] conf6;`
123			`output [15:0] conf7;`
124			`output [15:0] conf8;`
125			`output [15:0] conf9;`
126			`output [15:0] conf10;`
127			`output [15:0] conf11;`
128			`output [15:0] conf12;`
129			`output [15:0] conf13;`
130			`output [15:0] conf14;`
131			`output [15:0] conf15;`
132
133			`////////////////////////////////////////////////////////////////////`
134			`//`
135			`// Local Wires`
136			`//`
137
138			`reg [15:0] conf0, conf1, conf2, conf3, conf4, conf5;`
139			`reg [15:0] conf6, conf7, conf8, conf9, conf10, conf11;`
140			`reg [15:0] conf12, conf13, conf14, conf15;`
141
142			`//synopsys infer_multibit "conf0"`
143			`//synopsys infer_multibit "conf1"`
144			`//synopsys infer_multibit "conf2"`
145			`//synopsys infer_multibit "conf3"`
146			`//synopsys infer_multibit "conf4"`
147			`//synopsys infer_multibit "conf5"`
148			`//synopsys infer_multibit "conf6"`
149			`//synopsys infer_multibit "conf7"`
150			`//synopsys infer_multibit "conf8"`
151			`//synopsys infer_multibit "conf9"`
152			`//synopsys infer_multibit "conf10"`
153			`//synopsys infer_multibit "conf11"`
154			`//synopsys infer_multibit "conf12"`
155			`//synopsys infer_multibit "conf13"`
156			`//synopsys infer_multibit "conf14"`
157			`//synopsys infer_multibit "conf15"`
158
159			`wire rf_sel;`
160			`reg [15:0] rf_dout;`
161			`reg rf_ack;`
162			`reg rf_we;`
163
164			`////////////////////////////////////////////////////////////////////`
165			`//`
166			`// Register File Select Logic`
167			`//`
168
169			`assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);`
170
171			`////////////////////////////////////////////////////////////////////`
172			`//`
173			`// Register File Logic`
174			`//`
175
176			`always @(posedge clk_i)`
177			`rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;`
178
179			`always @(posedge clk_i)`
180			`rf_ack <= #1 rf_sel & !rf_ack;`
181
182			`// Writre Logic`
183			`always @(posedge clk_i or posedge rst_i)`
184			`if(rst_i) conf0 <= #1 16'h0;`
185			`else`
186			`if(rf_we & (i_wb_addr_i[5:2] == 4'd0) ) conf0 <= #1 i_wb_data_i[15:0];`
187
188			`always @(posedge clk_i or posedge rst_i)`
189			`if(rst_i) conf1 <= #1 16'h0;`
190			`else`
191			`if(rf_we & (i_wb_addr_i[5:2] == 4'd1) ) conf1 <= #1 i_wb_data_i[15:0];`
192
193			`always @(posedge clk_i or posedge rst_i)`
194			`if(rst_i) conf2 <= #1 16'h0;`
195			`else`
196			`if(rf_we & (i_wb_addr_i[5:2] == 4'd2) ) conf2 <= #1 i_wb_data_i[15:0];`
197
198			`always @(posedge clk_i or posedge rst_i)`
199			`if(rst_i) conf3 <= #1 16'h0;`
200			`else`
201			`if(rf_we & (i_wb_addr_i[5:2] == 4'd3) ) conf3 <= #1 i_wb_data_i[15:0];`
202
203			`always @(posedge clk_i or posedge rst_i)`
204			`if(rst_i) conf4 <= #1 16'h0;`
205			`else`
206			`if(rf_we & (i_wb_addr_i[5:2] == 4'd4) ) conf4 <= #1 i_wb_data_i[15:0];`
207
208			`always @(posedge clk_i or posedge rst_i)`
209			`if(rst_i) conf5 <= #1 16'h0;`
210			`else`
211			`if(rf_we & (i_wb_addr_i[5:2] == 4'd5) ) conf5 <= #1 i_wb_data_i[15:0];`
212
213			`always @(posedge clk_i or posedge rst_i)`
214			`if(rst_i) conf6 <= #1 16'h0;`
215			`else`
216			`if(rf_we & (i_wb_addr_i[5:2] == 4'd6) ) conf6 <= #1 i_wb_data_i[15:0];`
217
218			`always @(posedge clk_i or posedge rst_i)`
219			`if(rst_i) conf7 <= #1 16'h0;`
220			`else`
221			`if(rf_we & (i_wb_addr_i[5:2] == 4'd7) ) conf7 <= #1 i_wb_data_i[15:0];`
222
223			`always @(posedge clk_i or posedge rst_i)`
224			`if(rst_i) conf8 <= #1 16'h0;`
225			`else`
226			`if(rf_we & (i_wb_addr_i[5:2] == 4'd8) ) conf8 <= #1 i_wb_data_i[15:0];`
227
228			`always @(posedge clk_i or posedge rst_i)`
229			`if(rst_i) conf9 <= #1 16'h0;`
230			`else`
231			`if(rf_we & (i_wb_addr_i[5:2] == 4'd9) ) conf9 <= #1 i_wb_data_i[15:0];`
232
233			`always @(posedge clk_i or posedge rst_i)`
234			`if(rst_i) conf10 <= #1 16'h0;`
235			`else`
236			`if(rf_we & (i_wb_addr_i[5:2] == 4'd10) ) conf10 <= #1 i_wb_data_i[15:0];`
237
238			`always @(posedge clk_i or posedge rst_i)`
239			`if(rst_i) conf11 <= #1 16'h0;`
240			`else`
241			`if(rf_we & (i_wb_addr_i[5:2] == 4'd11) ) conf11 <= #1 i_wb_data_i[15:0];`
242
243			`always @(posedge clk_i or posedge rst_i)`
244			`if(rst_i) conf12 <= #1 16'h0;`
245			`else`
246			`if(rf_we & (i_wb_addr_i[5:2] == 4'd12) ) conf12 <= #1 i_wb_data_i[15:0];`
247
248			`always @(posedge clk_i or posedge rst_i)`
249			`if(rst_i) conf13 <= #1 16'h0;`
250			`else`
251			`if(rf_we & (i_wb_addr_i[5:2] == 4'd13) ) conf13 <= #1 i_wb_data_i[15:0];`
252
253			`always @(posedge clk_i or posedge rst_i)`
254			`if(rst_i) conf14 <= #1 16'h0;`
255			`else`
256			`if(rf_we & (i_wb_addr_i[5:2] == 4'd14) ) conf14 <= #1 i_wb_data_i[15:0];`
257
258			`always @(posedge clk_i or posedge rst_i)`
259			`if(rst_i) conf15 <= #1 16'h0;`
260			`else`
261			`if(rf_we & (i_wb_addr_i[5:2] == 4'd15) ) conf15 <= #1 i_wb_data_i[15:0];`
262
263			`// Read Logic`
264			`always @(posedge clk_i)`
265			`if(!rf_sel) rf_dout <= #1 16'h0;`
266			`else`
267			`case(i_wb_addr_i[5:2])`
268			`4'd0: rf_dout <= #1 conf0;`
269			`4'd1: rf_dout <= #1 conf1;`
270			`4'd2: rf_dout <= #1 conf2;`
271			`4'd3: rf_dout <= #1 conf3;`
272			`4'd4: rf_dout <= #1 conf4;`
273			`4'd5: rf_dout <= #1 conf5;`
274			`4'd6: rf_dout <= #1 conf6;`
275			`4'd7: rf_dout <= #1 conf7;`
276			`4'd8: rf_dout <= #1 conf8;`
277			`4'd9: rf_dout <= #1 conf9;`
278			`4'd10: rf_dout <= #1 conf10;`
279			`4'd11: rf_dout <= #1 conf11;`
280			`4'd12: rf_dout <= #1 conf12;`
281			`4'd13: rf_dout <= #1 conf13;`
282			`4'd14: rf_dout <= #1 conf14;`
283			`4'd15: rf_dout <= #1 conf15;`
284			`endcase`
285
286			`////////////////////////////////////////////////////////////////////`
287			`//`
288			`// Register File By-Pass Logic`
289			`//`
290
291			`assign e_wb_addr_o = i_wb_addr_i;`
292			`assign e_wb_sel_o = i_wb_sel_i;`
293			`assign e_wb_data_o = i_wb_data_i;`
294
295			`assign e_wb_cyc_o = rf_sel ? 1'b0 : i_wb_cyc_i;`
296			`assign e_wb_stb_o = i_wb_stb_i;`
297			`assign e_wb_we_o = i_wb_we_i;`
298
299			`assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;`
300			`assign i_wb_ack_o = rf_sel ? rf_ack : e_wb_ack_i;`
301			`assign i_wb_err_o = rf_sel ? 1'b0 : e_wb_err_i;`
302			`assign i_wb_rty_o = rf_sel ? 1'b0 : e_wb_rty_i;`
303
304			`endmodule`