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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_bench_top.v,v 1.5 2002-02-01 01:55:44 rudi Exp $
//
//  $Date: 2002-02-01 01:55:44 $
//  $Revision: 1.5 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.4  2001/10/19 04:47:31  rudi
//
//               - Made the core parameterized
//
//               Revision 1.3  2001/09/07 15:34:36  rudi
//
//               Changed reset to active high.
//
//               Revision 1.2  2001/08/15 05:40:29  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Added Section 3.10, describing DMA restart.
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.1.1.1  2001/03/19 13:11:22  rudi
//               Initial Release
//
//
//                        
 
`include "wb_dma_defines.v"
 
`define CH_COUNT 4
 
module test;
 
reg             clk;
reg             rst;
 
// IO Prototypes
 
wire    [31:0]   wb0s_data_i;
wire    [31:0]   wb0s_data_o;
wire    [31:0]   wb0_addr_i;
wire    [3:0]    wb0_sel_i;
wire            wb0_we_i;
wire            wb0_cyc_i;
wire            wb0_stb_i;
wire            wb0_ack_o;
wire            wb0_err_o;
wire            wb0_rty_o;
wire    [31:0]   wb0m_data_i;
wire    [31:0]   wb0m_data_o;
wire    [31:0]   wb0_addr_o;
wire    [3:0]    wb0_sel_o;
wire            wb0_we_o;
wire            wb0_cyc_o;
wire            wb0_stb_o;
wire            wb0_ack_i;
wire            wb0_err_i;
wire            wb0_rty_i;
wire    [31:0]   wb1s_data_i;
wire    [31:0]   wb1s_data_o;
wire    [31:0]   wb1_addr_i;
wire    [3:0]    wb1_sel_i;
wire            wb1_we_i;
wire            wb1_cyc_i;
wire            wb1_stb_i;
wire            wb1_ack_o;
wire            wb1_err_o;
wire            wb1_rty_o;
wire    [31:0]   wb1m_data_i;
wire    [31:0]   wb1m_data_o;
wire    [31:0]   wb1_addr_o;
wire    [3:0]    wb1_sel_o;
wire            wb1_we_o;
wire            wb1_cyc_o;
wire            wb1_stb_o;
wire            wb1_ack_i;
wire            wb1_err_i;
wire            wb1_rty_i;
reg     [`CH_COUNT-1:0]  req_i;
wire    [`CH_COUNT-1:0]  ack_o;
reg     [`CH_COUNT-1:0]  nd_i;
reg     [`CH_COUNT-1:0]  rest_i;
wire            inta_o;
wire            intb_o;
 
wire    [31:0]   wb0_data_o_mast;
wire    [31:0]   wb1_data_o_mast;
wire    [31:0]   wb0_data_o_slv;
wire    [31:0]   wb1_data_o_slv;
 
// Test Bench Variables
reg     [31:0]   wd_cnt;
integer         error_cnt;
reg             ack_cnt_clr;
reg     [31:0]   ack_cnt;
 
// Misc Variables
 
/////////////////////////////////////////////////////////////////////
//
// Defines 
//
 
 
`define MEM             32'h0002_0000
`define REG_BASE        32'hb000_0000
 
`define COR             8'h0
`define INT_MASKA       8'h4
`define INT_MASKB       8'h8
`define INT_SRCA        8'hc
`define INT_SRCB        8'h10
 
`define CH0_CSR         8'h20
`define CH0_TXSZ        8'h24
`define CH0_ADR0        8'h28
`define CH0_AM0         8'h2c
`define CH0_ADR1        8'h30
`define CH0_AM1         8'h34
`define PTR0            8'h38
 
`define CH1_CSR         8'h40
`define CH1_TXSZ        8'h44
`define CH1_ADR0        8'h48
`define CH1_AM0         8'h4c
`define CH1_ADR1        8'h50
`define CH1_AM1         8'h54
`define PTR1            8'h58
 
`define CH2_CSR         8'h60
`define CH2_TXSZ        8'h64
`define CH2_ADR0        8'h68
`define CH2_AM0         8'h6c
`define CH2_ADR1        8'h70
`define CH2_AM1         8'h74
`define PTR2            8'h78
 
`define CH3_CSR         8'h80
`define CH3_TXSZ        8'h84
`define CH3_ADR0        8'h88
`define CH3_AM0         8'h8c
`define CH3_ADR1        8'h90
`define CH3_AM1         8'h94
`define PTR3            8'h98
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
initial
   begin
        $display("\n\n");
        $display("**********************************************");
        $display("* WISHBONE DMA/BRIDGE Simulation started ... *");
        $display("**********************************************");
        $display("\n");
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        req_i = 0;
        nd_i = 0;
        wd_cnt = 0;
        ack_cnt = 0;
        ack_cnt_clr = 0;
        error_cnt = 0;
        clk = 0;
        rst = 1;
        rest_i = 0;
 
        repeat(10)      @(posedge clk);
        rst = 0;
        repeat(10)      @(posedge clk);
 
        // HERE IS WHERE THE TEST CASES GO ...
 
if(1)   // Full Regression Run
   begin
$display(" ......................................................");
$display(" :                                                    :");
$display(" :    Long Regression Run ...                         :");
$display(" :....................................................:");
        pt10_rd;
        pt01_wr;
        pt01_rd;
        pt10_wr;
        sw_dma1(0);
        sw_dma2(0);
        hw_dma1(0);
        hw_dma2(0);
        arb_test1;
        sw_ext_desc1(0);
        hw_dma3(0);
        hw_dma4(0);
   end
else
if(1)   // Quick Regression Run
   begin
$display(" ......................................................");
$display(" :                                                    :");
$display(" :    Short Regression Run ...                        :");
$display(" :....................................................:");
        pt10_rd;
        pt01_wr;
        pt01_rd;
        pt10_wr;
        sw_dma1(2);
        sw_dma2(2);
        hw_dma1(1);
        hw_dma2(2);
        hw_dma3(2);
        hw_dma4(2);
        arb_test1;
        sw_ext_desc1(1);
   end
else
   begin
 
        //
        // TEST DEVELOPMENT AREA
        //
        sw_dma1(3);
 
        //arb_test1;
 
        repeat(100)     @(posedge clk);
 
   end
 
        repeat(100)     @(posedge clk);
        $finish;
   end
 
/////////////////////////////////////////////////////////////////////
//
// ack counter
//
 
always @(posedge clk)
        if(ack_cnt_clr)                 ack_cnt <= #1 0;
        else
        if(wb0_ack_i | wb1_ack_i)       ack_cnt <= #1 ack_cnt + 1;
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
 
always @(posedge clk)
        if(wb0_cyc_i | wb1_cyc_i | wb0_ack_i | wb1_ack_i)       wd_cnt <= #1 0;
        else                                                    wd_cnt <= #1 wd_cnt + 1;
 
always @(wd_cnt)
        if(wd_cnt>5000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
always #5 clk = ~clk;
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE DMA IP Core
//
 
 
// Module Prototype
 
wb_dma_top
        #(      4'hb,           // register file address
                2'd1,           // Number of priorities (4)
                `CH_COUNT,      // Number of channels
                4'hf,
                4'hf,
                4'hf,
                4'hf,
                4'hf,
                4'hf,
                4'hf,
                4'hf
                )
                u0(
                .clk_i(         clk             ),
                .rst_i(         rst             ),
                .wb0s_data_i(   wb0s_data_i     ),
                .wb0s_data_o(   wb0s_data_o     ),
                .wb0_addr_i(    wb0_addr_i      ),
                .wb0_sel_i(     wb0_sel_i       ),
                .wb0_we_i(      wb0_we_i        ),
                .wb0_cyc_i(     wb0_cyc_i       ),
                .wb0_stb_i(     wb0_stb_i       ),
                .wb0_ack_o(     wb0_ack_o       ),
                .wb0_err_o(     wb0_err_o       ),
                .wb0_rty_o(     wb0_rty_o       ),
                .wb0m_data_i(   wb0m_data_i     ),
                .wb0m_data_o(   wb0m_data_o     ),
                .wb0_addr_o(    wb0_addr_o      ),
                .wb0_sel_o(     wb0_sel_o       ),
                .wb0_we_o(      wb0_we_o        ),
                .wb0_cyc_o(     wb0_cyc_o       ),
                .wb0_stb_o(     wb0_stb_o       ),
                .wb0_ack_i(     wb0_ack_i       ),
                .wb0_err_i(     wb0_err_i       ),
                .wb0_rty_i(     wb0_rty_i       ),
                .wb1s_data_i(   wb1s_data_i     ),
                .wb1s_data_o(   wb1s_data_o     ),
                .wb1_addr_i(    wb1_addr_i      ),
                .wb1_sel_i(     wb1_sel_i       ),
                .wb1_we_i(      wb1_we_i        ),
                .wb1_cyc_i(     wb1_cyc_i       ),
                .wb1_stb_i(     wb1_stb_i       ),
                .wb1_ack_o(     wb1_ack_o       ),
                .wb1_err_o(     wb1_err_o       ),
                .wb1_rty_o(     wb1_rty_o       ),
                .wb1m_data_i(   wb1m_data_i     ),
                .wb1m_data_o(   wb1m_data_o     ),
                .wb1_addr_o(    wb1_addr_o      ),
                .wb1_sel_o(     wb1_sel_o       ),
                .wb1_we_o(      wb1_we_o        ),
                .wb1_cyc_o(     wb1_cyc_o       ),
                .wb1_stb_o(     wb1_stb_o       ),
                .wb1_ack_i(     wb1_ack_i       ),
                .wb1_err_i(     wb1_err_i       ),
                .wb1_rty_i(     wb1_rty_i       ),
                .dma_req_i(     req_i           ),
                .dma_ack_o(     ack_o           ),
                .dma_nd_i(      nd_i            ),
                .dma_rest_i(    rest_i          ),
                .inta_o(        inta_o          ),
                .intb_o(        intb_o          )
                );
 
wb_slv  #(14) s0(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb0_addr_o      ),
                .din(           wb0s_data_o     ),
                .dout(          wb0s_data_i     ),
                .cyc(           wb0_cyc_o       ),
                .stb(           wb0_stb_o       ),
                .sel(           wb0_sel_o       ),
                .we(            wb0_we_o        ),
                .ack(           wb0_ack_i       ),
                .err(           wb0_err_i       ),
                .rty(           wb0_rty_i       )
                );
 
wb_slv  #(14) s1(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb1_addr_o      ),
                .din(           wb1s_data_o     ),
                .dout(          wb1s_data_i     ),
                .cyc(           wb1_cyc_o       ),
                .stb(           wb1_stb_o       ),
                .sel(           wb1_sel_o       ),
                .we(            wb1_we_o        ),
                .ack(           wb1_ack_i       ),
                .err(           wb1_err_i       ),
                .rty(           wb1_rty_i       )
                );
 
wb_mast m0(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb0_addr_i      ),
                .din(           wb0m_data_o     ),
                .dout(          wb0m_data_i     ),
                .cyc(           wb0_cyc_i       ),
                .stb(           wb0_stb_i       ),
                .sel(           wb0_sel_i       ),
                .we(            wb0_we_i        ),
                .ack(           wb0_ack_o       ),
                .err(           wb0_err_o       ),
                .rty(           wb0_rty_o       )
                );
 
wb_mast m1(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb1_addr_i      ),
                .din(           wb1m_data_o     ),
                .dout(          wb1m_data_i     ),
                .cyc(           wb1_cyc_i       ),
                .stb(           wb1_stb_i       ),
                .sel(           wb1_sel_i       ),
                .we(            wb1_we_i        ),
                .ack(           wb1_ack_o       ),
                .err(           wb1_err_o       ),
                .rty(           wb1_rty_o       )
                );
 
`include "tests.v"
 
endmodule
 

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	15	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17	5	rudi	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	15	rudi	`// $Id: test_bench_top.v,v 1.5 2002-02-01 01:55:44 rudi Exp $`
42	5	rudi	`//`
43	15	rudi	`// $Date: 2002-02-01 01:55:44 $`
44			`// $Revision: 1.5 $`
45	5	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	15	rudi	`// Revision 1.4 2001/10/19 04:47:31 rudi`
52			`//`
53			`// - Made the core parameterized`
54			`//`
55	12	rudi	`// Revision 1.3 2001/09/07 15:34:36 rudi`
56			`//`
57			`// Changed reset to active high.`
58			`//`
59	9	rudi	`// Revision 1.2 2001/08/15 05:40:29 rudi`
60			`//`
61			`// - Changed IO names to be more clear.`
62			`// - Uniquifyed define names to be core specific.`
63			`// - Added Section 3.10, describing DMA restart.`
64			`//`
65	8	rudi	`// Revision 1.1 2001/07/29 08:57:02 rudi`
66			`//`
67			`//`
68			`// 1) Changed Directory Structure`
69			`// 2) Added restart signal (REST)`
70			`//`
71	5	rudi	`// Revision 1.1.1.1 2001/03/19 13:11:22 rudi`
72			`// Initial Release`
73			`//`
74			`//`
75			`//`
76
77			`include "wb_dma_defines.v"
78
79	12	rudi	`define CH_COUNT 4
80
81	5	rudi	`module test;`
82
83			`reg clk;`
84			`reg rst;`
85
86			`// IO Prototypes`
87
88			`wire [31:0] wb0s_data_i;`
89			`wire [31:0] wb0s_data_o;`
90			`wire [31:0] wb0_addr_i;`
91			`wire [3:0] wb0_sel_i;`
92			`wire wb0_we_i;`
93			`wire wb0_cyc_i;`
94			`wire wb0_stb_i;`
95			`wire wb0_ack_o;`
96			`wire wb0_err_o;`
97			`wire wb0_rty_o;`
98			`wire [31:0] wb0m_data_i;`
99			`wire [31:0] wb0m_data_o;`
100			`wire [31:0] wb0_addr_o;`
101			`wire [3:0] wb0_sel_o;`
102			`wire wb0_we_o;`
103			`wire wb0_cyc_o;`
104			`wire wb0_stb_o;`
105			`wire wb0_ack_i;`
106			`wire wb0_err_i;`
107			`wire wb0_rty_i;`
108			`wire [31:0] wb1s_data_i;`
109			`wire [31:0] wb1s_data_o;`
110			`wire [31:0] wb1_addr_i;`
111			`wire [3:0] wb1_sel_i;`
112			`wire wb1_we_i;`
113			`wire wb1_cyc_i;`
114			`wire wb1_stb_i;`
115			`wire wb1_ack_o;`
116			`wire wb1_err_o;`
117			`wire wb1_rty_o;`
118			`wire [31:0] wb1m_data_i;`
119			`wire [31:0] wb1m_data_o;`
120			`wire [31:0] wb1_addr_o;`
121			`wire [3:0] wb1_sel_o;`
122			`wire wb1_we_o;`
123			`wire wb1_cyc_o;`
124			`wire wb1_stb_o;`
125			`wire wb1_ack_i;`
126			`wire wb1_err_i;`
127			`wire wb1_rty_i;`
128	12	rudi	reg [`CH_COUNT-1:0] req_i;
129			wire [`CH_COUNT-1:0] ack_o;
130			reg [`CH_COUNT-1:0] nd_i;
131			reg [`CH_COUNT-1:0] rest_i;
132	5	rudi	`wire inta_o;`
133			`wire intb_o;`
134
135			`wire [31:0] wb0_data_o_mast;`
136			`wire [31:0] wb1_data_o_mast;`
137			`wire [31:0] wb0_data_o_slv;`
138			`wire [31:0] wb1_data_o_slv;`
139
140			`// Test Bench Variables`
141			`reg [31:0] wd_cnt;`
142			`integer error_cnt;`
143			`reg ack_cnt_clr;`
144			`reg [31:0] ack_cnt;`
145
146			`// Misc Variables`
147
148			`/////////////////////////////////////////////////////////////////////`
149			`//`
150			`// Defines`
151			`//`
152
153
154			`define MEM 32'h0002_0000
155	9	rudi	`define REG_BASE 32'hb000_0000
156	5	rudi
157			`define COR 8'h0
158			`define INT_MASKA 8'h4
159			`define INT_MASKB 8'h8
160			`define INT_SRCA 8'hc
161			`define INT_SRCB 8'h10
162
163			`define CH0_CSR 8'h20
164			`define CH0_TXSZ 8'h24
165			`define CH0_ADR0 8'h28
166			`define CH0_AM0 8'h2c
167			`define CH0_ADR1 8'h30
168			`define CH0_AM1 8'h34
169			`define PTR0 8'h38
170
171			`define CH1_CSR 8'h40
172			`define CH1_TXSZ 8'h44
173			`define CH1_ADR0 8'h48
174			`define CH1_AM0 8'h4c
175			`define CH1_ADR1 8'h50
176			`define CH1_AM1 8'h54
177			`define PTR1 8'h58
178
179			`define CH2_CSR 8'h60
180			`define CH2_TXSZ 8'h64
181			`define CH2_ADR0 8'h68
182			`define CH2_AM0 8'h6c
183			`define CH2_ADR1 8'h70
184			`define CH2_AM1 8'h74
185			`define PTR2 8'h78
186
187			`define CH3_CSR 8'h80
188			`define CH3_TXSZ 8'h84
189			`define CH3_ADR0 8'h88
190			`define CH3_AM0 8'h8c
191			`define CH3_ADR1 8'h90
192			`define CH3_AM1 8'h94
193			`define PTR3 8'h98
194
195			`/////////////////////////////////////////////////////////////////////`
196			`//`
197			`// Simulation Initialization and Start up Section`
198			`//`
199
200			`initial`
201			`begin`
202			`$display("\n\n");`
203			`$display("**********************************************");`
204			`$display("* WISHBONE DMA/BRIDGE Simulation started ... *");`
205			`$display("**********************************************");`
206			`$display("\n");`
207			`ifdef WAVES
208			`$shm_open("waves");`
209			`$shm_probe("AS",test,"AS");`
210			`$display("INFO: Signal dump enabled ...\n\n");`
211			`endif
212			`req_i = 0;`
213			`nd_i = 0;`
214			`wd_cnt = 0;`
215			`ack_cnt = 0;`
216			`ack_cnt_clr = 0;`
217			`error_cnt = 0;`
218			`clk = 0;`
219	9	rudi	`rst = 1;`
220	5	rudi	`rest_i = 0;`
221
222			`repeat(10) @(posedge clk);`
223	9	rudi	`rst = 0;`
224	5	rudi	`repeat(10) @(posedge clk);`
225
226			`// HERE IS WHERE THE TEST CASES GO ...`
227
228	15	rudi	`if(1) // Full Regression Run`
229	5	rudi	`begin`
230	9	rudi	`$display(" ......................................................");`
231			`$display(" : :");`
232			`$display(" : Long Regression Run ... :");`
233			`$display(" :....................................................:");`
234	5	rudi	`pt10_rd;`
235			`pt01_wr;`
236			`pt01_rd;`
237			`pt10_wr;`
238			`sw_dma1(0);`
239			`sw_dma2(0);`
240			`hw_dma1(0);`
241			`hw_dma2(0);`
242			`arb_test1;`
243			`sw_ext_desc1(0);`
244			`hw_dma3(0);`
245			`hw_dma4(0);`
246			`end`
247			`else`
248			`if(1) // Quick Regression Run`
249			`begin`
250	9	rudi	`$display(" ......................................................");`
251			`$display(" : :");`
252			`$display(" : Short Regression Run ... :");`
253			`$display(" :....................................................:");`
254	5	rudi	`pt10_rd;`
255			`pt01_wr;`
256			`pt01_rd;`
257			`pt10_wr;`
258			`sw_dma1(2);`
259			`sw_dma2(2);`
260			`hw_dma1(1);`
261			`hw_dma2(2);`
262			`hw_dma3(2);`
263			`hw_dma4(2);`
264			`arb_test1;`
265			`sw_ext_desc1(1);`
266			`end`
267			`else`
268			`begin`
269
270			`//`
271			`// TEST DEVELOPMENT AREA`
272			`//`
273	9	rudi	`sw_dma1(3);`
274	5	rudi
275	9	rudi	`//arb_test1;`
276	5	rudi
277			`repeat(100) @(posedge clk);`
278
279			`end`
280
281			`repeat(100) @(posedge clk);`
282			`$finish;`
283			`end`
284
285			`/////////////////////////////////////////////////////////////////////`
286			`//`
287			`// ack counter`
288			`//`
289
290			`always @(posedge clk)`
291			`if(ack_cnt_clr) ack_cnt <= #1 0;`
292			`else`
293			`if(wb0_ack_i \| wb1_ack_i) ack_cnt <= #1 ack_cnt + 1;`
294
295			`/////////////////////////////////////////////////////////////////////`
296			`//`
297			`// Watchdog Counter`
298			`//`
299
300
301			`always @(posedge clk)`
302			`if(wb0_cyc_i \| wb1_cyc_i \| wb0_ack_i \| wb1_ack_i) wd_cnt <= #1 0;`
303	8	rudi	`else wd_cnt <= #1 wd_cnt + 1;`
304	5	rudi
305			`always @(wd_cnt)`
306			`if(wd_cnt>5000)`
307			`begin`
308			`$display("\n\n*************************************\n");`
309			`$display("ERROR: Watch Dog Counter Expired\n");`
310			`$display("*************************************\n\n\n");`
311			`$finish;`
312			`end`
313
314			`always #5 clk = ~clk;`
315
316			`/////////////////////////////////////////////////////////////////////`
317			`//`
318			`// WISHBONE DMA IP Core`
319			`//`
320
321
322			`// Module Prototype`
323
324	12	rudi	`wb_dma_top`
325			`#( 4'hb, // register file address`
326			`2'd1, // Number of priorities (4)`
327			`CH_COUNT, // Number of channels
328			`4'hf,`
329			`4'hf,`
330			`4'hf,`
331			`4'hf,`
332			`4'hf,`
333			`4'hf,`
334			`4'hf,`
335			`4'hf`
336			`)`
337			`u0(`
338	8	rudi	`.clk_i( clk ),`
339			`.rst_i( rst ),`
340	5	rudi	`.wb0s_data_i( wb0s_data_i ),`
341			`.wb0s_data_o( wb0s_data_o ),`
342			`.wb0_addr_i( wb0_addr_i ),`
343			`.wb0_sel_i( wb0_sel_i ),`
344			`.wb0_we_i( wb0_we_i ),`
345			`.wb0_cyc_i( wb0_cyc_i ),`
346			`.wb0_stb_i( wb0_stb_i ),`
347			`.wb0_ack_o( wb0_ack_o ),`
348			`.wb0_err_o( wb0_err_o ),`
349			`.wb0_rty_o( wb0_rty_o ),`
350			`.wb0m_data_i( wb0m_data_i ),`
351			`.wb0m_data_o( wb0m_data_o ),`
352			`.wb0_addr_o( wb0_addr_o ),`
353			`.wb0_sel_o( wb0_sel_o ),`
354			`.wb0_we_o( wb0_we_o ),`
355			`.wb0_cyc_o( wb0_cyc_o ),`
356			`.wb0_stb_o( wb0_stb_o ),`
357			`.wb0_ack_i( wb0_ack_i ),`
358			`.wb0_err_i( wb0_err_i ),`
359			`.wb0_rty_i( wb0_rty_i ),`
360			`.wb1s_data_i( wb1s_data_i ),`
361			`.wb1s_data_o( wb1s_data_o ),`
362			`.wb1_addr_i( wb1_addr_i ),`
363			`.wb1_sel_i( wb1_sel_i ),`
364			`.wb1_we_i( wb1_we_i ),`
365			`.wb1_cyc_i( wb1_cyc_i ),`
366			`.wb1_stb_i( wb1_stb_i ),`
367			`.wb1_ack_o( wb1_ack_o ),`
368			`.wb1_err_o( wb1_err_o ),`
369			`.wb1_rty_o( wb1_rty_o ),`
370			`.wb1m_data_i( wb1m_data_i ),`
371			`.wb1m_data_o( wb1m_data_o ),`
372			`.wb1_addr_o( wb1_addr_o ),`
373			`.wb1_sel_o( wb1_sel_o ),`
374			`.wb1_we_o( wb1_we_o ),`
375			`.wb1_cyc_o( wb1_cyc_o ),`
376			`.wb1_stb_o( wb1_stb_o ),`
377			`.wb1_ack_i( wb1_ack_i ),`
378			`.wb1_err_i( wb1_err_i ),`
379			`.wb1_rty_i( wb1_rty_i ),`
380			`.dma_req_i( req_i ),`
381			`.dma_ack_o( ack_o ),`
382			`.dma_nd_i( nd_i ),`
383			`.dma_rest_i( rest_i ),`
384			`.inta_o( inta_o ),`
385			`.intb_o( intb_o )`
386			`);`
387
388			`wb_slv #(14) s0(`
389			`.clk( clk ),`
390	9	rudi	`.rst( ~rst ),`
391	5	rudi	`.adr( wb0_addr_o ),`
392			`.din( wb0s_data_o ),`
393			`.dout( wb0s_data_i ),`
394			`.cyc( wb0_cyc_o ),`
395			`.stb( wb0_stb_o ),`
396			`.sel( wb0_sel_o ),`
397			`.we( wb0_we_o ),`
398			`.ack( wb0_ack_i ),`
399			`.err( wb0_err_i ),`
400			`.rty( wb0_rty_i )`
401			`);`
402
403			`wb_slv #(14) s1(`
404			`.clk( clk ),`
405	9	rudi	`.rst( ~rst ),`
406	5	rudi	`.adr( wb1_addr_o ),`
407			`.din( wb1s_data_o ),`
408			`.dout( wb1s_data_i ),`
409			`.cyc( wb1_cyc_o ),`
410			`.stb( wb1_stb_o ),`
411			`.sel( wb1_sel_o ),`
412			`.we( wb1_we_o ),`
413			`.ack( wb1_ack_i ),`
414			`.err( wb1_err_i ),`
415			`.rty( wb1_rty_i )`
416			`);`
417
418			`wb_mast m0(`
419			`.clk( clk ),`
420	9	rudi	`.rst( ~rst ),`
421	5	rudi	`.adr( wb0_addr_i ),`
422			`.din( wb0m_data_o ),`
423			`.dout( wb0m_data_i ),`
424			`.cyc( wb0_cyc_i ),`
425			`.stb( wb0_stb_i ),`
426			`.sel( wb0_sel_i ),`
427			`.we( wb0_we_i ),`
428			`.ack( wb0_ack_o ),`
429			`.err( wb0_err_o ),`
430			`.rty( wb0_rty_o )`
431			`);`
432
433			`wb_mast m1(`
434			`.clk( clk ),`
435	9	rudi	`.rst( ~rst ),`
436	5	rudi	`.adr( wb1_addr_i ),`
437			`.din( wb1m_data_o ),`
438			`.dout( wb1m_data_i ),`
439			`.cyc( wb1_cyc_i ),`
440			`.stb( wb1_stb_i ),`
441			`.sel( wb1_sel_i ),`
442			`.we( wb1_we_i ),`
443			`.ack( wb1_ack_o ),`
444			`.err( wb1_err_o ),`
445			`.rty( wb1_rty_o )`
446			`);`
447
448			`include "tests.v"
449
450			`endmodule`
451

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