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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_bench_top.v,v 1.3 2001-09-07 15:34:36 rudi Exp $
//
//  $Date: 2001-09-07 15:34:36 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/08/15 05:40:29  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Added Section 3.10, describing DMA restart.
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.1.1.1  2001/03/19 13:11:22  rudi
//               Initial Release
//
//
//                        
 
`include "wb_dma_defines.v"
 
module test;
 
reg             clk;
reg             rst;
 
// IO Prototypes
 
wire    [31:0]   wb0s_data_i;
wire    [31:0]   wb0s_data_o;
wire    [31:0]   wb0_addr_i;
wire    [3:0]    wb0_sel_i;
wire            wb0_we_i;
wire            wb0_cyc_i;
wire            wb0_stb_i;
wire            wb0_ack_o;
wire            wb0_err_o;
wire            wb0_rty_o;
wire    [31:0]   wb0m_data_i;
wire    [31:0]   wb0m_data_o;
wire    [31:0]   wb0_addr_o;
wire    [3:0]    wb0_sel_o;
wire            wb0_we_o;
wire            wb0_cyc_o;
wire            wb0_stb_o;
wire            wb0_ack_i;
wire            wb0_err_i;
wire            wb0_rty_i;
wire    [31:0]   wb1s_data_i;
wire    [31:0]   wb1s_data_o;
wire    [31:0]   wb1_addr_i;
wire    [3:0]    wb1_sel_i;
wire            wb1_we_i;
wire            wb1_cyc_i;
wire            wb1_stb_i;
wire            wb1_ack_o;
wire            wb1_err_o;
wire            wb1_rty_o;
wire    [31:0]   wb1m_data_i;
wire    [31:0]   wb1m_data_o;
wire    [31:0]   wb1_addr_o;
wire    [3:0]    wb1_sel_o;
wire            wb1_we_o;
wire            wb1_cyc_o;
wire            wb1_stb_o;
wire            wb1_ack_i;
wire            wb1_err_i;
wire            wb1_rty_i;
reg     [`WDMA_CH_COUNT-1:0]     req_i;
wire    [`WDMA_CH_COUNT-1:0]     ack_o;
reg     [`WDMA_CH_COUNT-1:0]     nd_i;
reg     [`WDMA_CH_COUNT-1:0]     rest_i;
wire            inta_o;
wire            intb_o;
 
wire    [31:0]   wb0_data_o_mast;
wire    [31:0]   wb1_data_o_mast;
wire    [31:0]   wb0_data_o_slv;
wire    [31:0]   wb1_data_o_slv;
 
// Test Bench Variables
reg     [31:0]   wd_cnt;
integer         error_cnt;
reg             ack_cnt_clr;
reg     [31:0]   ack_cnt;
 
// Misc Variables
 
/////////////////////////////////////////////////////////////////////
//
// Defines 
//
 
 
`define MEM             32'h0002_0000
`define REG_BASE        32'hb000_0000
 
`define COR             8'h0
`define INT_MASKA       8'h4
`define INT_MASKB       8'h8
`define INT_SRCA        8'hc
`define INT_SRCB        8'h10
 
`define CH0_CSR         8'h20
`define CH0_TXSZ        8'h24
`define CH0_ADR0        8'h28
`define CH0_AM0         8'h2c
`define CH0_ADR1        8'h30
`define CH0_AM1         8'h34
`define PTR0            8'h38
 
`define CH1_CSR         8'h40
`define CH1_TXSZ        8'h44
`define CH1_ADR0        8'h48
`define CH1_AM0         8'h4c
`define CH1_ADR1        8'h50
`define CH1_AM1         8'h54
`define PTR1            8'h58
 
`define CH2_CSR         8'h60
`define CH2_TXSZ        8'h64
`define CH2_ADR0        8'h68
`define CH2_AM0         8'h6c
`define CH2_ADR1        8'h70
`define CH2_AM1         8'h74
`define PTR2            8'h78
 
`define CH3_CSR         8'h80
`define CH3_TXSZ        8'h84
`define CH3_ADR0        8'h88
`define CH3_AM0         8'h8c
`define CH3_ADR1        8'h90
`define CH3_AM1         8'h94
`define PTR3            8'h98
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
initial
   begin
        $display("\n\n");
        $display("**********************************************");
        $display("* WISHBONE DMA/BRIDGE Simulation started ... *");
        $display("**********************************************");
        $display("\n");
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        req_i = 0;
        nd_i = 0;
        wd_cnt = 0;
        ack_cnt = 0;
        ack_cnt_clr = 0;
        error_cnt = 0;
        clk = 0;
        rst = 1;
        rest_i = 0;
 
        repeat(10)      @(posedge clk);
        rst = 0;
        repeat(10)      @(posedge clk);
 
        // HERE IS WHERE THE TEST CASES GO ...
 
if(0)    // Full Regression Run
   begin
$display(" ......................................................");
$display(" :                                                    :");
$display(" :    Long Regression Run ...                         :");
$display(" :....................................................:");
        pt10_rd;
        pt01_wr;
        pt01_rd;
        pt10_wr;
        sw_dma1(0);
        sw_dma2(0);
        hw_dma1(0);
        hw_dma2(0);
        arb_test1;
        sw_ext_desc1(0);
        hw_dma3(0);
        hw_dma4(0);
   end
else
if(1)   // Quick Regression Run
   begin
$display(" ......................................................");
$display(" :                                                    :");
$display(" :    Short Regression Run ...                        :");
$display(" :....................................................:");
        pt10_rd;
        pt01_wr;
        pt01_rd;
        pt10_wr;
        sw_dma1(2);
        sw_dma2(2);
        hw_dma1(1);
        hw_dma2(2);
        hw_dma3(2);
        hw_dma4(2);
        arb_test1;
        sw_ext_desc1(1);
   end
else
   begin
 
        //
        // TEST DEVELOPMENT AREA
        //
        sw_dma1(3);
 
        //arb_test1;
 
        repeat(100)     @(posedge clk);
 
   end
 
        repeat(100)     @(posedge clk);
        $finish;
   end
 
/////////////////////////////////////////////////////////////////////
//
// ack counter
//
 
always @(posedge clk)
        if(ack_cnt_clr)                 ack_cnt <= #1 0;
        else
        if(wb0_ack_i | wb1_ack_i)       ack_cnt <= #1 ack_cnt + 1;
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
 
always @(posedge clk)
        if(wb0_cyc_i | wb1_cyc_i | wb0_ack_i | wb1_ack_i)       wd_cnt <= #1 0;
        else                                                    wd_cnt <= #1 wd_cnt + 1;
 
always @(wd_cnt)
        if(wd_cnt>5000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
always #5 clk = ~clk;
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE DMA IP Core
//
 
 
// Module Prototype
 
wb_dma_top      u0(
                .clk_i(         clk             ),
                .rst_i(         rst             ),
                .wb0s_data_i(   wb0s_data_i     ),
                .wb0s_data_o(   wb0s_data_o     ),
                .wb0_addr_i(    wb0_addr_i      ),
                .wb0_sel_i(     wb0_sel_i       ),
                .wb0_we_i(      wb0_we_i        ),
                .wb0_cyc_i(     wb0_cyc_i       ),
                .wb0_stb_i(     wb0_stb_i       ),
                .wb0_ack_o(     wb0_ack_o       ),
                .wb0_err_o(     wb0_err_o       ),
                .wb0_rty_o(     wb0_rty_o       ),
                .wb0m_data_i(   wb0m_data_i     ),
                .wb0m_data_o(   wb0m_data_o     ),
                .wb0_addr_o(    wb0_addr_o      ),
                .wb0_sel_o(     wb0_sel_o       ),
                .wb0_we_o(      wb0_we_o        ),
                .wb0_cyc_o(     wb0_cyc_o       ),
                .wb0_stb_o(     wb0_stb_o       ),
                .wb0_ack_i(     wb0_ack_i       ),
                .wb0_err_i(     wb0_err_i       ),
                .wb0_rty_i(     wb0_rty_i       ),
                .wb1s_data_i(   wb1s_data_i     ),
                .wb1s_data_o(   wb1s_data_o     ),
                .wb1_addr_i(    wb1_addr_i      ),
                .wb1_sel_i(     wb1_sel_i       ),
                .wb1_we_i(      wb1_we_i        ),
                .wb1_cyc_i(     wb1_cyc_i       ),
                .wb1_stb_i(     wb1_stb_i       ),
                .wb1_ack_o(     wb1_ack_o       ),
                .wb1_err_o(     wb1_err_o       ),
                .wb1_rty_o(     wb1_rty_o       ),
                .wb1m_data_i(   wb1m_data_i     ),
                .wb1m_data_o(   wb1m_data_o     ),
                .wb1_addr_o(    wb1_addr_o      ),
                .wb1_sel_o(     wb1_sel_o       ),
                .wb1_we_o(      wb1_we_o        ),
                .wb1_cyc_o(     wb1_cyc_o       ),
                .wb1_stb_o(     wb1_stb_o       ),
                .wb1_ack_i(     wb1_ack_i       ),
                .wb1_err_i(     wb1_err_i       ),
                .wb1_rty_i(     wb1_rty_i       ),
                .dma_req_i(     req_i           ),
                .dma_ack_o(     ack_o           ),
                .dma_nd_i(      nd_i            ),
                .dma_rest_i(    rest_i          ),
                .inta_o(        inta_o          ),
                .intb_o(        intb_o          )
                );
 
wb_slv  #(14) s0(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb0_addr_o      ),
                .din(           wb0s_data_o     ),
                .dout(          wb0s_data_i     ),
                .cyc(           wb0_cyc_o       ),
                .stb(           wb0_stb_o       ),
                .sel(           wb0_sel_o       ),
                .we(            wb0_we_o        ),
                .ack(           wb0_ack_i       ),
                .err(           wb0_err_i       ),
                .rty(           wb0_rty_i       )
                );
 
wb_slv  #(14) s1(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb1_addr_o      ),
                .din(           wb1s_data_o     ),
                .dout(          wb1s_data_i     ),
                .cyc(           wb1_cyc_o       ),
                .stb(           wb1_stb_o       ),
                .sel(           wb1_sel_o       ),
                .we(            wb1_we_o        ),
                .ack(           wb1_ack_i       ),
                .err(           wb1_err_i       ),
                .rty(           wb1_rty_i       )
                );
 
wb_mast m0(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb0_addr_i      ),
                .din(           wb0m_data_o     ),
                .dout(          wb0m_data_i     ),
                .cyc(           wb0_cyc_i       ),
                .stb(           wb0_stb_i       ),
                .sel(           wb0_sel_i       ),
                .we(            wb0_we_i        ),
                .ack(           wb0_ack_o       ),
                .err(           wb0_err_o       ),
                .rty(           wb0_rty_o       )
                );
 
wb_mast m1(
                .clk(           clk             ),
                .rst(           ~rst            ),
                .adr(           wb1_addr_i      ),
                .din(           wb1m_data_o     ),
                .dout(          wb1m_data_i     ),
                .cyc(           wb1_cyc_i       ),
                .stb(           wb1_stb_i       ),
                .sel(           wb1_sel_i       ),
                .we(            wb1_we_i        ),
                .ack(           wb1_ack_o       ),
                .err(           wb1_err_o       ),
                .rty(           wb1_rty_o       )
                );
 
`include "tests.v"
 
endmodule
 

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	9	rudi	`// $Id: test_bench_top.v,v 1.3 2001-09-07 15:34:36 rudi Exp $`
41	5	rudi	`//`
42	9	rudi	`// $Date: 2001-09-07 15:34:36 $`
43			`// $Revision: 1.3 $`
44	5	rudi	`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	9	rudi	`// Revision 1.2 2001/08/15 05:40:29 rudi`
51			`//`
52			`// - Changed IO names to be more clear.`
53			`// - Uniquifyed define names to be core specific.`
54			`// - Added Section 3.10, describing DMA restart.`
55			`//`
56	8	rudi	`// Revision 1.1 2001/07/29 08:57:02 rudi`
57			`//`
58			`//`
59			`// 1) Changed Directory Structure`
60			`// 2) Added restart signal (REST)`
61			`//`
62	5	rudi	`// Revision 1.1.1.1 2001/03/19 13:11:22 rudi`
63			`// Initial Release`
64			`//`
65			`//`
66			`//`
67
68			`include "wb_dma_defines.v"
69
70			`module test;`
71
72			`reg clk;`
73			`reg rst;`
74
75			`// IO Prototypes`
76
77			`wire [31:0] wb0s_data_i;`
78			`wire [31:0] wb0s_data_o;`
79			`wire [31:0] wb0_addr_i;`
80			`wire [3:0] wb0_sel_i;`
81			`wire wb0_we_i;`
82			`wire wb0_cyc_i;`
83			`wire wb0_stb_i;`
84			`wire wb0_ack_o;`
85			`wire wb0_err_o;`
86			`wire wb0_rty_o;`
87			`wire [31:0] wb0m_data_i;`
88			`wire [31:0] wb0m_data_o;`
89			`wire [31:0] wb0_addr_o;`
90			`wire [3:0] wb0_sel_o;`
91			`wire wb0_we_o;`
92			`wire wb0_cyc_o;`
93			`wire wb0_stb_o;`
94			`wire wb0_ack_i;`
95			`wire wb0_err_i;`
96			`wire wb0_rty_i;`
97			`wire [31:0] wb1s_data_i;`
98			`wire [31:0] wb1s_data_o;`
99			`wire [31:0] wb1_addr_i;`
100			`wire [3:0] wb1_sel_i;`
101			`wire wb1_we_i;`
102			`wire wb1_cyc_i;`
103			`wire wb1_stb_i;`
104			`wire wb1_ack_o;`
105			`wire wb1_err_o;`
106			`wire wb1_rty_o;`
107			`wire [31:0] wb1m_data_i;`
108			`wire [31:0] wb1m_data_o;`
109			`wire [31:0] wb1_addr_o;`
110			`wire [3:0] wb1_sel_o;`
111			`wire wb1_we_o;`
112			`wire wb1_cyc_o;`
113			`wire wb1_stb_o;`
114			`wire wb1_ack_i;`
115			`wire wb1_err_i;`
116			`wire wb1_rty_i;`
117	8	rudi	reg [`WDMA_CH_COUNT-1:0] req_i;
118			wire [`WDMA_CH_COUNT-1:0] ack_o;
119			reg [`WDMA_CH_COUNT-1:0] nd_i;
120			reg [`WDMA_CH_COUNT-1:0] rest_i;
121	5	rudi	`wire inta_o;`
122			`wire intb_o;`
123
124			`wire [31:0] wb0_data_o_mast;`
125			`wire [31:0] wb1_data_o_mast;`
126			`wire [31:0] wb0_data_o_slv;`
127			`wire [31:0] wb1_data_o_slv;`
128
129			`// Test Bench Variables`
130			`reg [31:0] wd_cnt;`
131			`integer error_cnt;`
132			`reg ack_cnt_clr;`
133			`reg [31:0] ack_cnt;`
134
135			`// Misc Variables`
136
137			`/////////////////////////////////////////////////////////////////////`
138			`//`
139			`// Defines`
140			`//`
141
142
143			`define MEM 32'h0002_0000
144	9	rudi	`define REG_BASE 32'hb000_0000
145	5	rudi
146			`define COR 8'h0
147			`define INT_MASKA 8'h4
148			`define INT_MASKB 8'h8
149			`define INT_SRCA 8'hc
150			`define INT_SRCB 8'h10
151
152			`define CH0_CSR 8'h20
153			`define CH0_TXSZ 8'h24
154			`define CH0_ADR0 8'h28
155			`define CH0_AM0 8'h2c
156			`define CH0_ADR1 8'h30
157			`define CH0_AM1 8'h34
158			`define PTR0 8'h38
159
160			`define CH1_CSR 8'h40
161			`define CH1_TXSZ 8'h44
162			`define CH1_ADR0 8'h48
163			`define CH1_AM0 8'h4c
164			`define CH1_ADR1 8'h50
165			`define CH1_AM1 8'h54
166			`define PTR1 8'h58
167
168			`define CH2_CSR 8'h60
169			`define CH2_TXSZ 8'h64
170			`define CH2_ADR0 8'h68
171			`define CH2_AM0 8'h6c
172			`define CH2_ADR1 8'h70
173			`define CH2_AM1 8'h74
174			`define PTR2 8'h78
175
176			`define CH3_CSR 8'h80
177			`define CH3_TXSZ 8'h84
178			`define CH3_ADR0 8'h88
179			`define CH3_AM0 8'h8c
180			`define CH3_ADR1 8'h90
181			`define CH3_AM1 8'h94
182			`define PTR3 8'h98
183
184			`/////////////////////////////////////////////////////////////////////`
185			`//`
186			`// Simulation Initialization and Start up Section`
187			`//`
188
189			`initial`
190			`begin`
191			`$display("\n\n");`
192			`$display("**********************************************");`
193			`$display("* WISHBONE DMA/BRIDGE Simulation started ... *");`
194			`$display("**********************************************");`
195			`$display("\n");`
196			`ifdef WAVES
197			`$shm_open("waves");`
198			`$shm_probe("AS",test,"AS");`
199			`$display("INFO: Signal dump enabled ...\n\n");`
200			`endif
201			`req_i = 0;`
202			`nd_i = 0;`
203			`wd_cnt = 0;`
204			`ack_cnt = 0;`
205			`ack_cnt_clr = 0;`
206			`error_cnt = 0;`
207			`clk = 0;`
208	9	rudi	`rst = 1;`
209	5	rudi	`rest_i = 0;`
210
211			`repeat(10) @(posedge clk);`
212	9	rudi	`rst = 0;`
213	5	rudi	`repeat(10) @(posedge clk);`
214
215			`// HERE IS WHERE THE TEST CASES GO ...`
216
217	9	rudi	`if(0) // Full Regression Run`
218	5	rudi	`begin`
219	9	rudi	`$display(" ......................................................");`
220			`$display(" : :");`
221			`$display(" : Long Regression Run ... :");`
222			`$display(" :....................................................:");`
223	5	rudi	`pt10_rd;`
224			`pt01_wr;`
225			`pt01_rd;`
226			`pt10_wr;`
227			`sw_dma1(0);`
228			`sw_dma2(0);`
229			`hw_dma1(0);`
230			`hw_dma2(0);`
231			`arb_test1;`
232			`sw_ext_desc1(0);`
233			`hw_dma3(0);`
234			`hw_dma4(0);`
235			`end`
236			`else`
237			`if(1) // Quick Regression Run`
238			`begin`
239	9	rudi	`$display(" ......................................................");`
240			`$display(" : :");`
241			`$display(" : Short Regression Run ... :");`
242			`$display(" :....................................................:");`
243	5	rudi	`pt10_rd;`
244			`pt01_wr;`
245			`pt01_rd;`
246			`pt10_wr;`
247			`sw_dma1(2);`
248			`sw_dma2(2);`
249			`hw_dma1(1);`
250			`hw_dma2(2);`
251			`hw_dma3(2);`
252			`hw_dma4(2);`
253			`arb_test1;`
254			`sw_ext_desc1(1);`
255			`end`
256			`else`
257			`begin`
258
259			`//`
260			`// TEST DEVELOPMENT AREA`
261			`//`
262	9	rudi	`sw_dma1(3);`
263	5	rudi
264	9	rudi	`//arb_test1;`
265	5	rudi
266			`repeat(100) @(posedge clk);`
267
268			`end`
269
270			`repeat(100) @(posedge clk);`
271			`$finish;`
272			`end`
273
274			`/////////////////////////////////////////////////////////////////////`
275			`//`
276			`// ack counter`
277			`//`
278
279			`always @(posedge clk)`
280			`if(ack_cnt_clr) ack_cnt <= #1 0;`
281			`else`
282			`if(wb0_ack_i \| wb1_ack_i) ack_cnt <= #1 ack_cnt + 1;`
283
284			`/////////////////////////////////////////////////////////////////////`
285			`//`
286			`// Watchdog Counter`
287			`//`
288
289
290			`always @(posedge clk)`
291			`if(wb0_cyc_i \| wb1_cyc_i \| wb0_ack_i \| wb1_ack_i) wd_cnt <= #1 0;`
292	8	rudi	`else wd_cnt <= #1 wd_cnt + 1;`
293	5	rudi
294			`always @(wd_cnt)`
295			`if(wd_cnt>5000)`
296			`begin`
297			`$display("\n\n*************************************\n");`
298			`$display("ERROR: Watch Dog Counter Expired\n");`
299			`$display("*************************************\n\n\n");`
300			`$finish;`
301			`end`
302
303			`always #5 clk = ~clk;`
304
305			`/////////////////////////////////////////////////////////////////////`
306			`//`
307			`// WISHBONE DMA IP Core`
308			`//`
309
310
311			`// Module Prototype`
312
313			`wb_dma_top u0(`
314	8	rudi	`.clk_i( clk ),`
315			`.rst_i( rst ),`
316	5	rudi	`.wb0s_data_i( wb0s_data_i ),`
317			`.wb0s_data_o( wb0s_data_o ),`
318			`.wb0_addr_i( wb0_addr_i ),`
319			`.wb0_sel_i( wb0_sel_i ),`
320			`.wb0_we_i( wb0_we_i ),`
321			`.wb0_cyc_i( wb0_cyc_i ),`
322			`.wb0_stb_i( wb0_stb_i ),`
323			`.wb0_ack_o( wb0_ack_o ),`
324			`.wb0_err_o( wb0_err_o ),`
325			`.wb0_rty_o( wb0_rty_o ),`
326			`.wb0m_data_i( wb0m_data_i ),`
327			`.wb0m_data_o( wb0m_data_o ),`
328			`.wb0_addr_o( wb0_addr_o ),`
329			`.wb0_sel_o( wb0_sel_o ),`
330			`.wb0_we_o( wb0_we_o ),`
331			`.wb0_cyc_o( wb0_cyc_o ),`
332			`.wb0_stb_o( wb0_stb_o ),`
333			`.wb0_ack_i( wb0_ack_i ),`
334			`.wb0_err_i( wb0_err_i ),`
335			`.wb0_rty_i( wb0_rty_i ),`
336			`.wb1s_data_i( wb1s_data_i ),`
337			`.wb1s_data_o( wb1s_data_o ),`
338			`.wb1_addr_i( wb1_addr_i ),`
339			`.wb1_sel_i( wb1_sel_i ),`
340			`.wb1_we_i( wb1_we_i ),`
341			`.wb1_cyc_i( wb1_cyc_i ),`
342			`.wb1_stb_i( wb1_stb_i ),`
343			`.wb1_ack_o( wb1_ack_o ),`
344			`.wb1_err_o( wb1_err_o ),`
345			`.wb1_rty_o( wb1_rty_o ),`
346			`.wb1m_data_i( wb1m_data_i ),`
347			`.wb1m_data_o( wb1m_data_o ),`
348			`.wb1_addr_o( wb1_addr_o ),`
349			`.wb1_sel_o( wb1_sel_o ),`
350			`.wb1_we_o( wb1_we_o ),`
351			`.wb1_cyc_o( wb1_cyc_o ),`
352			`.wb1_stb_o( wb1_stb_o ),`
353			`.wb1_ack_i( wb1_ack_i ),`
354			`.wb1_err_i( wb1_err_i ),`
355			`.wb1_rty_i( wb1_rty_i ),`
356			`.dma_req_i( req_i ),`
357			`.dma_ack_o( ack_o ),`
358			`.dma_nd_i( nd_i ),`
359			`.dma_rest_i( rest_i ),`
360			`.inta_o( inta_o ),`
361			`.intb_o( intb_o )`
362			`);`
363
364			`wb_slv #(14) s0(`
365			`.clk( clk ),`
366	9	rudi	`.rst( ~rst ),`
367	5	rudi	`.adr( wb0_addr_o ),`
368			`.din( wb0s_data_o ),`
369			`.dout( wb0s_data_i ),`
370			`.cyc( wb0_cyc_o ),`
371			`.stb( wb0_stb_o ),`
372			`.sel( wb0_sel_o ),`
373			`.we( wb0_we_o ),`
374			`.ack( wb0_ack_i ),`
375			`.err( wb0_err_i ),`
376			`.rty( wb0_rty_i )`
377			`);`
378
379			`wb_slv #(14) s1(`
380			`.clk( clk ),`
381	9	rudi	`.rst( ~rst ),`
382	5	rudi	`.adr( wb1_addr_o ),`
383			`.din( wb1s_data_o ),`
384			`.dout( wb1s_data_i ),`
385			`.cyc( wb1_cyc_o ),`
386			`.stb( wb1_stb_o ),`
387			`.sel( wb1_sel_o ),`
388			`.we( wb1_we_o ),`
389			`.ack( wb1_ack_i ),`
390			`.err( wb1_err_i ),`
391			`.rty( wb1_rty_i )`
392			`);`
393
394			`wb_mast m0(`
395			`.clk( clk ),`
396	9	rudi	`.rst( ~rst ),`
397	5	rudi	`.adr( wb0_addr_i ),`
398			`.din( wb0m_data_o ),`
399			`.dout( wb0m_data_i ),`
400			`.cyc( wb0_cyc_i ),`
401			`.stb( wb0_stb_i ),`
402			`.sel( wb0_sel_i ),`
403			`.we( wb0_we_i ),`
404			`.ack( wb0_ack_o ),`
405			`.err( wb0_err_o ),`
406			`.rty( wb0_rty_o )`
407			`);`
408
409			`wb_mast m1(`
410			`.clk( clk ),`
411	9	rudi	`.rst( ~rst ),`
412	5	rudi	`.adr( wb1_addr_i ),`
413			`.din( wb1m_data_o ),`
414			`.dout( wb1m_data_i ),`
415			`.cyc( wb1_cyc_i ),`
416			`.stb( wb1_stb_i ),`
417			`.sel( wb1_sel_i ),`
418			`.we( wb1_we_i ),`
419			`.ack( wb1_ack_o ),`
420			`.err( wb1_err_o ),`
421			`.rty( wb1_rty_o )`
422			`);`
423
424			`include "tests.v"
425
426			`endmodule`
427

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