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[/] [wb_dma/] [trunk/] [bench/] [verilog/] [tests.v] - Blame information for rev 17

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1 5 rudi 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
3 
////  DMA Test Cases                                             ////
4 
////                                                             ////
5 
////                                                             ////
6 
////  Author: Rudolf Usselmann                                   ////
7 
////          rudi@asics.ws                                      ////
8 
////                                                             ////
9 
////                                                             ////
10 
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
11 
////                                                             ////
12 
/////////////////////////////////////////////////////////////////////
13 
////                                                             ////
14 
//// Copyright (C) 2000 Rudolf Usselmann                         ////
15 
////                    rudi@asics.ws                            ////
16 
////                                                             ////
17 
//// This source file may be used and distributed without        ////
18 
//// restriction provided that this copyright statement is not   ////
19 
//// removed from the file and that any derivative work contains ////
20 
//// the original copyright notice and the associated disclaimer.////
21 
////                                                             ////
22 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
23 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
24 
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
25 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
26 
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
27 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
28 
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
29 
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
30 
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
31 
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
32 
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
33 
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
34 
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
35 
////                                                             ////
36 
/////////////////////////////////////////////////////////////////////
37 
 
38 
//  CVS Log
39 
//
40 9 rudi 
//  $Id: tests.v,v 1.3 2001-09-07 15:34:36 rudi Exp $
41 5 rudi 
//
42 9 rudi 
//  $Date: 2001-09-07 15:34:36 $
43 
//  $Revision: 1.3 $
44 5 rudi 
//  $Author: rudi $
45 
//  $Locker:  $
46 
//  $State: Exp $
47 
//
48 
// Change History:
49 
//               $Log: not supported by cvs2svn $
50 9 rudi 
//               Revision 1.2  2001/08/15 05:40:29  rudi
51 
//
52 
//               - Changed IO names to be more clear.
53 
//               - Uniquifyed define names to be core specific.
54 
//               - Added Section 3.10, describing DMA restart.
55 
//
56 8 rudi 
//               Revision 1.1  2001/07/29 08:57:02  rudi
57 
//
58 
//
59 
//               1) Changed Directory Structure
60 
//               2) Added restart signal (REST)
61 
//
62 5 rudi 
//               Revision 1.1.1.1  2001/03/19 13:12:39  rudi
63 
//               Initial Release
64 
//
65 
//
66 
//
67 
 
68 
task sw_ext_desc1;
69 
input           quick;
70 
 
71 
integer         quick, tot_sz_max, chunk_sz_max, del_max;
72 
 
73 
reg     [7:0]    mode;
74 
reg     [15:0]   tot_sz;
75 
reg     [15:0]   chunk_sz;
76 
integer         ii, n,del;
77 
reg     [31:0]   int_src, d0, d1;
78 
 
79 
begin
80 
$display("\n\n");
81 
$display("*****************************************************");
82 
$display("*** SW DMA No Buffer Ext. Descr LL ...            ***");
83 
$display("*****************************************************\n");
84 
 
85 9 rudi 
rst = 1;
86 
repeat(10)      @(posedge clk);
87 5 rudi 
rst = 0;
88 
repeat(10)      @(posedge clk);
89 
 
90 
if(quick)
91 
   begin
92 
        tot_sz_max = 32;
93 
        del_max = 2;
94 
        chunk_sz_max = 4;
95 
   end
96 
else
97 
   begin
98 
        tot_sz_max = 128;
99 
        del_max = 6;
100 
        chunk_sz_max = 8;
101 
   end
102 
 
103 
 
104 
mode = 1;
105 
tot_sz = 64;
106 
chunk_sz=3;
107 
del = 0;
108 
 
109 
for(del=0;del<del_max;del=del+1)
110 
for(mode=0;mode<4;mode=mode+1)
111 
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz + 1)
112 
begin
113 
 
114 
if(tot_sz>8)    tot_sz = tot_sz + 2;
115 
if(tot_sz>16)   tot_sz = tot_sz + 2;
116 
if(tot_sz>32)   tot_sz = tot_sz + 12;
117 
 
118 
 
119 
for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
120 
begin
121 
 
122 
        case(mode)
123 
           0: $write("Mode: 0->0, ");
124 
           1: $write("Mode: 0->1, ");
125 
           2: $write("Mode: 1->0, ");
126 
           3: $write("Mode: 1->1, ");
127 
        endcase
128 
        $display("Total Size: %0d, Chunk Size: %0d, Slave Delay: %0d",
129 
                tot_sz, chunk_sz, del);
130 
 
131 
        ack_cnt_clr = 1;
132 
        @(posedge clk);
133 
        ack_cnt_clr = 0;
134 
 
135 
        s0.delay = del;
136 
        s1.delay = del;
137 
 
138 
        s0.fill_mem(1);
139 
        s1.fill_mem(1);
140 
 
141 
        s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
142 
        s0.mem[1] = 32'h0000_0100;
143 
        s0.mem[2] = 32'h0000_0400;
144 
        s0.mem[3] = 32'h0000_0010;
145 
 
146 
        s0.mem[4] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
147 
        s0.mem[5] = 32'h0000_0100 + (tot_sz * 4);
148 
        s0.mem[6] = 32'h0000_0400 + (tot_sz * 4);
149 
        s0.mem[7] = 32'h0000_0000;
150 
 
151 
 
152 
        s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
153 
        s0.mem[9] = 32'h0000_0800;
154 
        s0.mem[10] = 32'h0000_0c00;
155 
        s0.mem[11] = 32'h0000_0030;
156 
 
157 
        s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
158 
        s0.mem[13] = 32'h0000_0800 + (tot_sz * 4);
159 
        s0.mem[14] = 32'h0000_0c00 + (tot_sz * 4);
160 
        s0.mem[15] = 32'h0000_0000;
161 
 
162 
 
163 
        m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
164 
 
165 
        m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0020);
166 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 12'h0});
167 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0080);
168 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
169 
 
170 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
171 
        {15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});
172 
 
173 
 
174 
        m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0000);
175 
        m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 12'h0});
176 
        m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080);
177 
        m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4000);
178 
 
179 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
180 
        {15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});
181 
 
182 
 
183 
for(ii=0;ii<2;ii=ii+1)
184 
begin
185 
        repeat(5)       @(posedge clk);
186 
        while(!inta_o)  @(posedge clk);
187 
 
188 
        m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
189 
 
190 
        if(int_src[0])
191 
        begin
192 
        for(n=0;n<tot_sz*2;n=n+1)
193 
           begin
194 
                if(mode[1])     d0=s1.mem[(s0.mem[9]>>2) + n ];
195 
                else            d0=s0.mem[(s0.mem[9]>>2) + n ];
196 
                if(mode[0])      d1=s1.mem[(s0.mem[10]>>2) + n ];
197 
                else            d1=s0.mem[(s0.mem[10]>>2) + n ];
198 
 
199 
                if( d1 !== d0 )
200 
                   begin
201 
                        $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
202 
                        n, d0, d1, $time);
203 
                        error_cnt = error_cnt + 1;
204 
                   end
205 
           end
206 
        m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1);
207 
        d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0};
208 
        if( d1 !== d0 )
209 
           begin
210 
                $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)",
211 
                        d0, d1, $time);
212 
                error_cnt = error_cnt + 1;
213 
           end
214 
        end
215 
 
216 
 
217 
        if(int_src[1])
218 
        begin
219 
        for(n=0;n<tot_sz*2;n=n+1)
220 
           begin
221 
                if(mode[1])     d0=s1.mem[(s0.mem[1]>>2) + n ];
222 
                else            d0=s0.mem[(s0.mem[1]>>2) + n ];
223 
                if(mode[0])      d1=s1.mem[(s0.mem[2]>>2) + n ];
224 
                else            d1=s0.mem[(s0.mem[2]>>2) + n ];
225 
 
226 
                if( d1 !== d0 )
227 
                   begin
228 
                        $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
229 
                        n, d0, d1, $time);
230 
                        error_cnt = error_cnt + 1;
231 
                   end
232 
           end
233 
        m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d1);
234 
        d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0};
235 
        if( d1 !== d0 )
236 
           begin
237 
                $display("ERROR: CH1_CSR Mismatch: Expected: %x, Got: %x (%0t)",
238 
                        d0, d1, $time);
239 
                error_cnt = error_cnt + 1;
240 
           end
241 
        end
242 
 
243 
end
244 
 
245 
        if(ack_cnt != ((tot_sz*4)+(4*2))*2 )
246 
           begin
247 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
248 
                ((tot_sz*4)+(4*2)), ack_cnt, $time);
249 
                error_cnt = error_cnt + 1;
250 
           end
251 
 
252 
        repeat(5)       @(posedge clk);
253 
 
254 
end
255 
end
256 
 
257 
show_errors;
258 
$display("*****************************************************");
259 
$display("*** Test DONE ...                                 ***");
260 
$display("*****************************************************\n\n");
261 
end
262 
 
263 
 
264 
endtask
265 
 
266 
 
267 
 
268 
task arb_test1;
269 
 
270 
reg     [7:0]    mode;
271 
reg     [15:0]   tot_sz;
272 
reg     [15:0]   chunk_sz0;
273 
reg     [15:0]   chunk_sz1;
274 
reg     [15:0]   chunk_sz2;
275 
reg     [15:0]   chunk_sz3;
276 
integer         a,n,ptr;
277 
reg     [31:0]   d0,d1;
278 
reg     [7:0]    pri, order, finish;
279 
 
280 
begin
281 
$display("\n\n");
282 
$display("*****************************************************");
283 
$display("*** SW DMA No Buffer 4 ch pri ...                 ***");
284 
$display("*****************************************************\n");
285 
 
286 
mode = 0;
287 
tot_sz = 32;
288 
chunk_sz0=4;
289 
chunk_sz1=4;
290 
chunk_sz2=4;
291 
chunk_sz3=4;
292 
a=0;
293 
 
294 
m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0);
295 
m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0);
296 
m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0);
297 
m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0);
298 
 
299 
m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0);
300 
 
301 
for(mode=0;mode<4;mode=mode+1)
302 
for(a=0;a<17;a=a+1)
303 
begin
304 
 
305 
        chunk_sz0=4;
306 
        chunk_sz1=4;
307 
        chunk_sz2=4;
308 
        chunk_sz3=4;
309 
 
310 
        s0.delay = 0;
311 
        s1.delay = 0;
312 
 
313 
        case(a)         // ch3 ch2 ch1 ch0
314 
           0:
315 
             begin
316 
                pri = 8'b10_10_10_10;   // All equal 0,1,2,3
317 
                order = {2'd0, 2'd1, 2'd2, 2'd3};
318 
             end
319 
 
320 
                // One channel with High Priority
321 
                // The other depend oon the ARB state
322 
           1:
323 
             begin
324 
                pri = 8'b00_00_00_10;   // 3,1,0,2
325 
                order = {2'b0, 2'd3, 2'd1, 2'd2};
326 
             end
327 
           2:
328 
             begin
329 
                pri = 8'b00_00_10_00;   // 2,3,0,1
330 
                order = {2'd1, 2'd0, 2'd2, 2'd3};
331 
             end
332 
           3:
333 
             begin
334 
                pri = 8'b00_10_00_00;   // 1,0,2,3
335 
                order = {2'd2, 2'd0, 2'd1, 2'd3};
336 
             end
337 
           4:
338 
             begin
339 
                pri = 8'b10_00_00_00;   // 0,3,1,2
340 
                order = {2'd3, 2'd0, 2'd1, 2'd2};
341 
             end
342 
 
343 
                // Specific order for all Channels
344 
           5:
345 
             begin
346 
                pri = 8'b10_00_01_11;   // 3,0,2,1
347 
                order = {2'd0, 2'd3, 2'd1, 2'd2};
348 
             end
349 
 
350 
           6:
351 
             begin
352 
                pri = 8'b00_10_11_01;   // 2,1,3,0
353 
                order = {2'd1, 2'd2, 2'd0, 2'd3};
354 
             end
355 
 
356 
           7:
357 
             begin
358 
                pri = 8'b00_11_01_10;   // 1,3,2,0
359 
                order = {2'd2, 2'd0, 2'd1, 2'd3};
360 
             end
361 
 
362 
           8:
363 
             begin
364 
                pri = 8'b00_01_10_11;   // 3,2,1,0
365 
                order = {2'd0, 2'd1, 2'd2, 2'd3};
366 
             end
367 
 
368 
                // One channel with High Priority
369 
                // The other depend oon the ARB state
370 
                // Chunk Size varies
371 
                // First channel small chunkc size
372 
           9:
373 
             begin
374 
                pri = 8'b00_00_00_10;   // 3,1,0,2
375 
                order = {2'd0, 2'd1, 2'd2, 2'd3};
376 
                chunk_sz3=1;
377 
             end
378 
           10:
379 
             begin
380 
                pri = 8'b00_00_10_00;   // 2,0,1,3
381 
                order = {2'd1, 2'd0, 2'd3, 2'd2};
382 
                chunk_sz2=1;
383 
             end
384 
           11:
385 
             begin
386 
                pri = 8'b00_10_00_00;   // 1,0,2,3
387 
                order = {2'd2, 2'd0, 2'd3, 2'd1};
388 
                chunk_sz1=1;
389 
             end
390 
           12:
391 
             begin
392 
                pri = 8'b10_00_00_00;   // 0,2,3,1
393 
                order = {2'd3, 2'd1, 2'd2, 2'd0};
394 
                chunk_sz0=1;
395 
             end
396 
 
397 
                // First channel large chunkc size
398 
           13:
399 
             begin
400 
                pri = 8'b00_00_00_10;   // 3,0,2,1
401 
                order = {2'd0, 2'd3, 2'd1, 2'd2};
402 
                chunk_sz3=8;
403 
             end
404 
           14:
405 
             begin
406 
                pri = 8'b00_00_10_00;   // 2,0,3,1
407 
                order = {2'd1, 2'd2, 2'd0, 2'd3};
408 
                chunk_sz2=8;
409 
             end
410 
           15:
411 
             begin
412 
                pri = 8'b00_10_00_00;   // 1,0,3,2
413 
                order = {2'd2, 2'd1, 2'd0, 2'd3};
414 
                chunk_sz1=8;
415 
             end
416 
           16:
417 
             begin
418 
                pri = 8'b10_00_00_00;   // 0,2,3,1
419 
                order = {2'd3, 2'd0, 2'd1, 2'd2};
420 
                chunk_sz0=8;
421 
             end
422 
 
423 
        endcase
424 
 
425 
case(mode)
426 
   0: $write("Mode: 0->0, ");
427 
   1: $write("Mode: 0->1, ");
428 
   2: $write("Mode: 1->0, ");
429 
   3: $write("Mode: 1->1, ");
430 
endcase
431 
$display("a: %0d", a);
432 
 
433 
        ack_cnt_clr = 1;
434 
        @(posedge clk);
435 
        ack_cnt_clr = 0;
436 
 
437 
        s0.fill_mem(1);
438 
        s1.fill_mem(1);
439 
 
440 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
441 8 rudi 
                {17'h00000, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b0});
442 5 rudi 
 
443 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
444 8 rudi 
                {17'h00000, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b0});
445 5 rudi 
 
446 
        m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
447 8 rudi 
                {17'h00000, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b0});
448 5 rudi 
 
449 
        m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
450 8 rudi 
                {17'h00000, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b0});
451 5 rudi 
 
452 
        m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
453 
 
454 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz0, tot_sz});
455 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
456 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
457 
 
458 
        m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz1, tot_sz});
459 
        m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080);
460 
        m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4080);
461 
 
462 
        m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz2, tot_sz});
463 
        m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_0100);
464 
        m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_4100);
465 
 
466 
        m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz3, tot_sz});
467 
        m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_0180);
468 
        m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_4180);
469 
 
470 8 rudi 
 
471 5 rudi 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
472 8 rudi 
                {12'h000, 3'b010, 1'b0, 1'b0, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b1});
473 5 rudi 
 
474 8 rudi 
                //{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});
475 
 
476 5 rudi 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
477 8 rudi 
                {12'h000, 3'b010, 1'b0, 1'b0, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b1});
478 5 rudi 
 
479 
        m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
480 8 rudi 
                {12'h000, 3'b010, 1'b0, 1'b0, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b1});
481 5 rudi 
 
482 8 rudi 
 
483 
 
484 5 rudi 
        m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
485 8 rudi 
                {12'h0000, 3'b010, 1'b0, 1'b0, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b1});
486 5 rudi 
 
487 
        repeat(1)       @(posedge clk);
488 
 
489 
        // Wait for interrupt, Check completion order
490 
 
491 
        ptr=0;
492 
        finish = 8'hxx;
493 
 
494 
        while(ptr!=4)
495 8 rudi 
           begin
496 
                while(!inta_o)  @(posedge clk);
497 
                m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0);
498 5 rudi 
 
499 8 rudi 
                if(d0[0])        d0[1:0] = 0;
500 
                else
501 
                if(d0[1])       d0[1:0] = 1;
502 
                else
503 
                if(d0[2])       d0[1:0] = 2;
504 
                else
505 
                if(d0[3])       d0[1:0] = 3;
506 5 rudi 
 
507 8 rudi 
                case(ptr)
508 
                   0: finish[7:6] = d0[1:0];
509 
                   1: finish[5:4] = d0[1:0];
510 
                   2: finish[3:2] = d0[1:0];
511 
                   3: finish[1:0] = d0[1:0];
512 
                endcase
513 5 rudi 
 
514 8 rudi 
                case(d0[1:0])
515 
                   0: m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
516 
                   1: m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
517 
                   2: m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
518 
                   3: m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
519 
                endcase
520 5 rudi 
 
521 8 rudi 
                ptr=ptr+1;
522 
                repeat(4)       @(posedge clk);
523 
           end
524 5 rudi 
 
525 
 
526 
        if(finish !== order)
527 
           begin
528 
                $display("ERROR: Completion Order[%0d] Mismatch: Expected: %b, Got: %b (%0t)",
529 
                a, order, finish, $time);
530 
                error_cnt = error_cnt + 1;
531 
           end
532 
 
533 
 
534 
        for(n=0;n<tot_sz*4;n=n+1)
535 
           begin
536 
                if(mode[1])     d0=s1.mem[ n ];
537 
                else            d0=s0.mem[ n ];
538 
                if(mode[0])      d1=s1.mem[32'h0000_1000 + n ];
539 
                else            d1=s0.mem[32'h0000_1000 + n ];
540 
 
541 
                if( d1 !== d0 )
542 
                   begin
543 
                        $display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
544 
                        n, d0, d1, $time);
545 
                        error_cnt = error_cnt + 1;
546 
                   end
547 
           end
548 
 
549 
        if(ack_cnt != ((tot_sz*4*2)) )
550 
           begin
551 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
552 
                ((tot_sz*4)), ack_cnt, $time);
553 
                error_cnt = error_cnt + 1;
554 
           end
555 
 
556 
 
557 
        repeat(5)       @(posedge clk);
558 
 
559 
end
560 
 
561 
show_errors;
562 
$display("*****************************************************");
563 
$display("*** Test DONE ...                                 ***");
564 
$display("*****************************************************\n\n");
565 
end
566 
 
567 
endtask
568 
 
569 
 
570 
 
571 
 
572 
 
573 
 
574 
task hw_dma1;
575 
input   quick;
576 
 
577 
integer         quick, chunk_sz_max, del_max;
578 
 
579 
reg     [7:0]    mode;
580 
reg     [15:0]   chunk_sz, tot_sz;
581 
integer         n,m,k,rep,del;
582 
reg     [31:0]   d0,d1;
583 
 
584 
begin
585 
$display("\n\n");
586 
$display("*****************************************************");
587 
$display("*** HW DMA No Buffer ...                          ***");
588 
$display("*****************************************************\n");
589 
 
590 
if(quick)
591 
   begin
592 
        tot_sz = 32;
593 
        chunk_sz_max= 4;
594 
        del_max = 3;
595 
   end
596 
else
597 
   begin
598 
        tot_sz = 64;
599 
        chunk_sz_max= 8;
600 
        del_max = 5;
601 
   end
602 
 
603 
mode = 1;
604 
chunk_sz=4;
605 
del = 8;
606 
for(mode=0;mode<4;mode=mode+1)
607 
for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
608 
for(del=0;del<del_max;del=del+1)
609 
begin
610 
 
611 
        m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'h0000_ffff);
612 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz});
613 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
614 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
615 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
616 
                {25'h0000000, 4'b1111, mode[1:0], 1'b1});
617 
 
618 
$write("Delay: %0d ",del);
619 
case(mode)
620 
   0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz);
621 
   1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz);
622 
   2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz);
623 
   3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz);
624 
endcase
625 
 
626 
for(rep=0;rep<4;rep=rep+1)
627 
   begin
628 
        ack_cnt_clr = 1;
629 
        @(posedge clk);
630 
        ack_cnt_clr = 0;
631 
 
632 
        if(del==4)      del = 10;
633 
 
634 
        s0.delay = del;
635 
        s1.delay = del;
636 
 
637 
        if(chunk_sz==0)          k = 1;
638 
        else
639 
           begin
640 
                k = tot_sz/chunk_sz;
641 
                if((k*chunk_sz) != tot_sz)      k = k + 1;
642 
           end
643 
 
644 
        s0.fill_mem(1);
645 
        s1.fill_mem(1);
646 
 
647 
        fork
648 
           begin
649 
 
650 
                for(m=0;m < k;m=m+1)
651 
                   begin
652 
                        repeat(del)     @(posedge clk);
653 
                        #1;
654 
                        req_i[0] = 1;
655 
                        while(!ack_o[0]) @(posedge clk);
656 
                        #1;
657 
                        req_i[0] = 0;
658 
                   end
659 
 
660 
           end
661 
 
662 
           begin
663 
                repeat(1)       @(posedge clk);
664 
                while(!u0.dma_done_all) @(posedge clk);
665 
 
666 
/*
667 
        repeat(5)       @(posedge clk);
668 
        while(!inta_o)  @(posedge clk);
669 
 
670 
        m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d1);
671 
        d0 = 32'h0000_0002;
672 
        if( d1 !== d0 )
673 
           begin
674 
                $display("ERROR: INT_SRC Mismatch: Expected: %x, Got: %x (%0t)",
675 
                        d0, d1, $time);
676 
                error_cnt = error_cnt + 1;
677 
           end
678 
 
679 
        m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1);
680 
        d0 = {24'h0000_081, 1'b1, mode[1:0], 1'b0};
681 
        if( d1 !== d0 )
682 
           begin
683 
                $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)",
684 
                        d0, d1, $time);
685 
                error_cnt = error_cnt + 1;
686 
           end
687 
*/
688 
 
689 
 
690 
                for(n=0;n<tot_sz;n=n+1)
691 
                   begin
692 
                        if(mode[1])     d0=s1.mem[ n ];
693 
                        else            d0=s0.mem[ n ];
694 
                        if(mode[0])      d1=s1.mem[32'h0000_1000 + n ];
695 
                        else            d1=s0.mem[32'h0000_1000 + n ];
696 
 
697 
                        if( d1 !== d0 )
698 
                           begin
699 
                                $display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
700 
                                n, d0, d1, $time);
701 
                                error_cnt = error_cnt + 1;
702 
                           end
703 
                   end
704 
 
705 
           end
706 
 
707 
        join
708 
 
709 
        if(ack_cnt != ((tot_sz*2)) )
710 
           begin
711 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
712 
                ((tot_sz*2)), ack_cnt, $time);
713 
                error_cnt = error_cnt + 1;
714 
           end
715 
 
716 
   end
717 
end
718 
 
719 
        s0.delay = 0;
720 
        s1.delay = 0;
721 
 
722 
show_errors;
723 
$display("*****************************************************");
724 
$display("*** Test DONE ...                                 ***");
725 
$display("*****************************************************\n\n");
726 
end
727 
 
728 
endtask
729 
 
730 
 
731 
 
732 
 
733 
task hw_dma2;
734 
input           quick;
735 
 
736 
integer         quick, tot_sz_max, chunk_sz_max, del_max;
737 
 
738 
reg     [7:0]    mode;
739 
reg     [15:0]   chunk_sz, tot_sz;
740 
integer         i, n,m0, m1, m2, m3, k,rep,del;
741 
reg     [31:0]   int_src, d0,d1;
742 
 
743 
begin
744 
$display("\n\n");
745 
$display("*****************************************************");
746 
$display("*** HW DMA No Buffer Ext Descr. 4 Channels ...    ***");
747 
$display("*****************************************************\n");
748 
 
749 
case(quick)
750 
        default:
751 
           begin
752 
                del_max = 6;
753 
                tot_sz_max = 200;
754 
                chunk_sz_max = 8;
755 
           end
756 
         1:
757 
           begin
758 
                del_max = 4;
759 
                tot_sz_max = 128;
760 
                chunk_sz_max = 4;
761 
           end
762 
         2:
763 
           begin
764 
                del_max = 3;
765 
                tot_sz_max = 32;
766 
                chunk_sz_max = 4;
767 
           end
768 
endcase
769 
 
770 
mode = 0;
771 
tot_sz = 128;
772 
chunk_sz=2;
773 
del = 0;
774 
 
775 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0);
776 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0);
777 
        m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0);
778 
        m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0);
779 
 
780 
        m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
781 
 
782 
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz+1)
783 
begin
784 
 
785 
if(tot_sz>4)    tot_sz = tot_sz + 4;
786 
if(tot_sz>16)   tot_sz = tot_sz + 12;
787 
if(tot_sz>64)   tot_sz = tot_sz + 48;
788 
 
789 
for(del=0;del<del_max;del=del+1)
790 
for(mode=0;mode<4;mode=mode+1)
791 
for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
792 
begin
793 
        s0.delay = del;
794 
        s1.delay = del;
795 
 
796 
        s0.fill_mem(1);
797 
        s1.fill_mem(1);
798 
 
799 
        s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
800 
        s0.mem[1] = 32'h0000_0100;
801 
        s0.mem[2] = 32'h0000_0900;
802 
        s0.mem[3] = 32'h0000_0010;
803 
 
804 
        s0.mem[4] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
805 
        s0.mem[5] = 32'h0000_0100 + (tot_sz * 4);
806 
        s0.mem[6] = 32'h0000_0900 + (tot_sz * 4);
807 
        s0.mem[7] = 32'h0000_0000;
808 
 
809 
        s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
810 
        s0.mem[9] = 32'h0000_1100;
811 
        s0.mem[10] = 32'h0000_1900;
812 
        s0.mem[11] = 32'h0000_0030;
813 
 
814 
        s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
815 
        s0.mem[13] = 32'h0000_1100 + (tot_sz * 4);
816 
        s0.mem[14] = 32'h0000_1900 + (tot_sz * 4);
817 
        s0.mem[15] = 32'h0000_0000;
818 
 
819 
        s0.mem[16] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
820 
        s0.mem[17] = 32'h0000_2100;
821 
        s0.mem[18] = 32'h0000_2900;
822 
        s0.mem[19] = 32'h0000_0050;
823 
 
824 
        s0.mem[20] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
825 
        s0.mem[21] = 32'h0000_2100 + (tot_sz * 4);
826 
        s0.mem[22] = 32'h0000_2900 + (tot_sz * 4);
827 
        s0.mem[23] = 32'h0000_0000;
828 
 
829 
        s0.mem[24] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
830 
        s0.mem[25] = 32'h0000_3100;
831 
        s0.mem[26] = 32'h0000_3900;
832 
        s0.mem[27] = 32'h0000_0070;
833 
 
834 
        s0.mem[28] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
835 
        s0.mem[29] = 32'h0000_3100 + (tot_sz * 4);
836 
        s0.mem[30] = 32'h0000_3900 + (tot_sz * 4);
837 
        s0.mem[31] = 32'h0000_0000;
838 
 
839 
        m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
840 
 
841 
        m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0000);
842 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 16'h0fff});
843 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_ffff);
844 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_ffff);
845 
 
846 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
847 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
848 
                        {12'h0000, 3'b010, 1'b0, 9'h001, 4'b0111, 2'b00, 1'b1});
849 
 
850 
        m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0020);
851 
        m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 16'h0fff});
852 
        m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_ffff);
853 
        m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_ffff);
854 
 
855 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
856 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
857 
                        {12'h0000, 3'b010, 1'b0, 9'h001, 4'b0111, 2'b00, 1'b1});
858 
 
859 
        m0.wb_wr1(`REG_BASE + `PTR2, 4'hf, 32'h0000_0040);
860 
        m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz, 16'h0fff});
861 
        m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_ffff);
862 
        m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_ffff);
863 
 
864 
        m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
865 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
866 
                        {12'h0000, 3'b010, 1'b0, 9'h001, 4'b0111, 2'b00, 1'b1});
867 
 
868 
        m0.wb_wr1(`REG_BASE + `PTR3, 4'hf, 32'h0000_0060);
869 
        m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz, 16'h0fff});
870 
        m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_ffff);
871 
        m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_ffff);
872 
 
873 
        m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
874 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
875 
                        {12'h0000, 3'b010, 1'b0, 9'h001, 4'b0111, 2'b00, 1'b1});
876 
 
877 
 
878 
        $write("Total Size: %0d, Delay: %0d ",tot_sz, del);
879 
        case(mode)
880 
           0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz);
881 
           1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz);
882 
           2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz);
883 
           3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz);
884 
        endcase
885 
 
886 
        ack_cnt_clr = 1;
887 
        @(posedge clk);
888 
        ack_cnt_clr = 0;
889 
 
890 
        if(chunk_sz==0)          k = 1;
891 
        else
892 
           begin
893 
                k = tot_sz/chunk_sz;
894 
                if((k*chunk_sz) != tot_sz)      k = k + 1;
895 
           end
896 
 
897 
        k = k * 2;
898 
 
899 
        fork
900 
           begin
901 
                repeat(5)       @(posedge clk);
902 
                for(m0=0;m0 < k;m0=m0+1)
903 
                   begin
904 
                        repeat(del)     @(posedge clk);
905 
                        #1;
906 
                        req_i[0] = 1;
907 
                        while(!ack_o[0]) @(posedge clk);
908 
                        #1;
909 
                        req_i[0] = 0;
910 
                   end
911 
           end
912 
 
913 
           begin
914 
                repeat(5)       @(posedge clk);
915 
                for(m1=0;m1 < k;m1=m1+1)
916 
                   begin
917 
                        repeat(del)     @(posedge clk);
918 
                        #1;
919 
                        req_i[1] = 1;
920 
                        while(!ack_o[1])        @(posedge clk);
921 
                        #1;
922 
                        req_i[1] = 0;
923 
                   end
924 
           end
925 
 
926 
           begin
927 
                repeat(5)       @(posedge clk);
928 
                for(m2=0;m2 < k;m2=m2+1)
929 
                   begin
930 
                        repeat(del)     @(posedge clk);
931 
                        #1;
932 
                        req_i[2] = 1;
933 
                        while(!ack_o[2])        @(posedge clk);
934 
                        #1;
935 
                        req_i[2] = 0;
936 
                   end
937 
           end
938 
 
939 
           begin
940 
                repeat(5)       @(posedge clk);
941 
                for(m3=0;m3 < k;m3=m3+1)
942 
                   begin
943 
                        repeat(del)     @(posedge clk);
944 
                        #1;
945 
                        req_i[3] = 1;
946 
                        while(!ack_o[3])        @(posedge clk);
947 
                        #1;
948 
                        req_i[3] = 0;
949 
                   end
950 
           end
951 
 
952 
           for(i=0;i<4;i=i)
953 
           begin
954 
                repeat(5)       @(posedge clk);
955 
                while(!inta_o)  @(posedge clk);
956 
                m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
957 
 
958 
                if(int_src[0])
959 
                   begin
960 
                        m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
961 
                        i=i+1;
962 
                        for(n=0;n<tot_sz*2;n=n+1)
963 
                           begin
964 
                                if(mode[1])     d0=s1.mem[(s0.mem[1]>>2) + n ];
965 
                                else            d0=s0.mem[(s0.mem[1]>>2) + n ];
966 
                                if(mode[0])      d1=s1.mem[(s0.mem[2]>>2) + n ];
967 
                                else            d1=s0.mem[(s0.mem[2]>>2) + n ];
968 
 
969 
                                if( d1 !== d0 )
970 
                                   begin
971 
                                        $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
972 
                                        n, d0, d1, $time);
973 
                                        error_cnt = error_cnt + 1;
974 
                                   end
975 
                           end
976 
                   end
977 
 
978 
                if(int_src[1])
979 
                   begin
980 
                        m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
981 
                        i=i+1;
982 
                        for(n=0;n<tot_sz*2;n=n+1)
983 
                           begin
984 
                                if(mode[1])     d0=s1.mem[(s0.mem[9]>>2) + n ];
985 
                                else            d0=s0.mem[(s0.mem[9]>>2) + n ];
986 
                                if(mode[0])      d1=s1.mem[(s0.mem[10]>>2) + n ];
987 
                                else            d1=s0.mem[(s0.mem[10]>>2) + n ];
988 
 
989 
                                if( d1 !== d0 )
990 
                                   begin
991 
                                        $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
992 
                                        n, d0, d1, $time);
993 
                                        error_cnt = error_cnt + 1;
994 
                                   end
995 
                           end
996 
                   end
997 
 
998 
                if(int_src[2])
999 
                   begin
1000 
                        m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
1001 
                        i=i+1;
1002 
                        for(n=0;n<tot_sz*2;n=n+1)
1003 
                           begin
1004 
                                if(mode[1])     d0=s1.mem[(s0.mem[17]>>2) + n ];
1005 
                                else            d0=s0.mem[(s0.mem[17]>>2) + n ];
1006 
                                if(mode[0])      d1=s1.mem[(s0.mem[18]>>2) + n ];
1007 
                                else            d1=s0.mem[(s0.mem[18]>>2) + n ];
1008 
 
1009 
                                if( d1 !== d0 )
1010 
                                   begin
1011 
                                        $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1012 
                                        n, d0, d1, $time);
1013 
                                        error_cnt = error_cnt + 1;
1014 
                                   end
1015 
                           end
1016 
                   end
1017 
 
1018 
                if(int_src[3])
1019 
                   begin
1020 
                        m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
1021 
                        i=i+1;
1022 
                        for(n=0;n<tot_sz*2;n=n+1)
1023 
                           begin
1024 
                                if(mode[1])     d0=s1.mem[(s0.mem[25]>>2) + n ];
1025 
                                else            d0=s0.mem[(s0.mem[25]>>2) + n ];
1026 
                                if(mode[0])      d1=s1.mem[(s0.mem[26]>>2) + n ];
1027 
                                else            d1=s0.mem[(s0.mem[26]>>2) + n ];
1028 
 
1029 
                                if( d1 !== d0 )
1030 
                                   begin
1031 
                                        $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1032 
                                        n, d0, d1, $time);
1033 
                                        error_cnt = error_cnt + 1;
1034 
                                   end
1035 
                           end
1036 
                   end
1037 
 
1038 
           end
1039 
 
1040 
        join
1041 
 
1042 
 
1043 
        if(ack_cnt != ((tot_sz*2*4*2)+(4*4*2)) )
1044 
           begin
1045 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
1046 
                ((tot_sz*2*4*2)+(4*4*2)), ack_cnt, $time);
1047 
                error_cnt = error_cnt + 1;
1048 
           end
1049 
 
1050 
        repeat(5)       @(posedge clk);
1051 
 
1052 
end
1053 
end
1054 
 
1055 
        s0.delay = 0;
1056 
        s1.delay = 0;
1057 
 
1058 
show_errors;
1059 
$display("*****************************************************");
1060 
$display("*** Test DONE ...                                 ***");
1061 
$display("*****************************************************\n\n");
1062 
end
1063 
 
1064 
endtask
1065 
 
1066 
 
1067 
 
1068 
 
1069 
 
1070 
 
1071 
task hw_dma3;
1072 
input           quick;
1073 
 
1074 
integer         quick, tot_sz_max, chunk_sz_max, del_max;
1075 
 
1076 
reg     [7:0]    mode;
1077 
reg     [15:0]   chunk_sz, tot_sz;
1078 
integer         odd, i, iz, n,m0, m1, m2, m3, k, k1, rep,del;
1079 
reg     [31:0]   int_src, d0,d1;
1080 
 
1081 
begin
1082 
$display("\n\n");
1083 
$display("*****************************************************");
1084 
$display("*** HW DMA Ext Descr. 4 Channels ND Test ...      ***");
1085 
$display("*****************************************************\n");
1086 
 
1087 
case(quick)
1088 
        default:
1089 
           begin
1090 
                del_max = 6;
1091 
                chunk_sz_max = 8;
1092 
           end
1093 
         1:
1094 
           begin
1095 
                del_max = 4;
1096 
                chunk_sz_max = 4;
1097 
           end
1098 
         2:
1099 
           begin
1100 
                del_max = 3;
1101 
                chunk_sz_max = 4;
1102 
           end
1103 
endcase
1104 
 
1105 
mode = 0;
1106 
tot_sz = 64;
1107 
chunk_sz=4;
1108 
del = 0;
1109 
 
1110 
m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0);
1111 
m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0);
1112 
m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0);
1113 
m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0);
1114 
 
1115 
m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
1116 
 
1117 
 
1118 
for(del=0;del<del_max;del=del+1)
1119 
for(mode=0;mode<4;mode=mode+1)
1120 
for(chunk_sz=1;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
1121 
begin
1122 
        repeat(50)      @(posedge clk);
1123 
        s0.delay = del;
1124 
        s1.delay = del;
1125 
 
1126 
        s0.fill_mem(1);
1127 
        s1.fill_mem(1);
1128 
 
1129 
        // Channel 0 Descriptors
1130 
        s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1131 
        s0.mem[1] = 32'h0000_0400;
1132 
        s0.mem[2] = 32'h0000_0800;
1133 
        s0.mem[3] = 32'h0000_0010;
1134 
 
1135 
        s0.mem[4] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1136 
        s0.mem[5] = 32'h0000_0400 + (tot_sz * 4);
1137 
        s0.mem[6] = 32'h0000_0800 + (tot_sz * 4);
1138 
        s0.mem[7] = 32'h0000_0020;
1139 
 
1140 
        s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1141 
        s0.mem[9] = 32'h0000_0400 + (tot_sz * 4);
1142 
        s0.mem[10] = 32'h0000_0800 + (tot_sz * 4);
1143 
        s0.mem[11] = 32'h0000_0030;
1144 
 
1145 
        s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1146 
        s0.mem[13] = 32'h0000_0400 + (tot_sz * 4);
1147 
        s0.mem[14] = 32'h0000_0800 + (tot_sz * 4);
1148 
        s0.mem[15] = 32'h0000_0000;
1149 
 
1150 
        // Channel 1 Descriptors
1151 
        s0.mem[16] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1152 
        s0.mem[17] = 32'h0000_0c00;
1153 
        s0.mem[18] = 32'h0000_1000;
1154 
        s0.mem[19] = 32'h0000_0050;
1155 
 
1156 
        s0.mem[20] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1157 
        s0.mem[21] = 32'h0000_0c00 + (tot_sz * 4);
1158 
        s0.mem[22] = 32'h0000_1000 + (tot_sz * 4);
1159 
        s0.mem[23] = 32'h0000_0060;
1160 
 
1161 
        s0.mem[24] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1162 
        s0.mem[25] = 32'h0000_0c00 + (tot_sz * 4);
1163 
        s0.mem[26] = 32'h0000_1000 + (tot_sz * 4);
1164 
        s0.mem[27] = 32'h0000_0070;
1165 
 
1166 
        s0.mem[28] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1167 
        s0.mem[29] = 32'h0000_0c00 + (tot_sz * 4);
1168 
        s0.mem[30] = 32'h0000_1000 + (tot_sz * 4);
1169 
        s0.mem[31] = 32'h0000_0000;
1170 
 
1171 
        // Channel 2 Descriptors
1172 
        s0.mem[32] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1173 
        s0.mem[33] = 32'h0000_1400;
1174 
        s0.mem[34] = 32'h0000_1800;
1175 
        s0.mem[35] = 32'h0000_0090;
1176 
 
1177 
        s0.mem[36] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1178 
        s0.mem[37] = 32'h0000_1400 + (tot_sz * 4);
1179 
        s0.mem[38] = 32'h0000_1800 + (tot_sz * 4);
1180 
        s0.mem[39] = 32'h0000_00a0;
1181 
 
1182 
        s0.mem[40] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1183 
        s0.mem[41] = 32'h0000_1400 + (tot_sz * 4);
1184 
        s0.mem[42] = 32'h0000_1800 + (tot_sz * 4);
1185 
        s0.mem[43] = 32'h0000_00b0;
1186 
 
1187 
        s0.mem[44] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1188 
        s0.mem[45] = 32'h0000_1400 + (tot_sz * 4);
1189 
        s0.mem[46] = 32'h0000_1800 + (tot_sz * 4);
1190 
        s0.mem[47] = 32'h0000_0000;
1191 
 
1192 
        // Channel 3 Descriptors
1193 
        s0.mem[48] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1194 
        s0.mem[49] = 32'h0000_1c00;
1195 
        s0.mem[50] = 32'h0000_2000;
1196 
        s0.mem[51] = 32'h0000_00d0;
1197 
 
1198 
        s0.mem[52] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1199 
        s0.mem[53] = 32'h0000_1c00 + (tot_sz * 4);
1200 
        s0.mem[54] = 32'h0000_2000 + (tot_sz * 4);
1201 
        s0.mem[55] = 32'h0000_00e0;
1202 
 
1203 
        s0.mem[56] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1204 
        s0.mem[57] = 32'h0000_1c00 + (tot_sz * 4);
1205 
        s0.mem[58] = 32'h0000_2000 + (tot_sz * 4);
1206 
        s0.mem[59] = 32'h0000_00f0;
1207 
 
1208 
        s0.mem[60] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz*4;
1209 
        s0.mem[61] = 32'h0000_1c00 + (tot_sz * 4);
1210 
        s0.mem[62] = 32'h0000_2000 + (tot_sz * 4);
1211 
        s0.mem[63] = 32'h0000_0000;
1212 
 
1213 
 
1214 
        m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
1215 
 
1216 
        m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0000);
1217 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 16'h0fff});
1218 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_ffff);
1219 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_ffff);
1220 
 
1221 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
1222 
                        {12'h0000, 3'b010, 1'b0, 9'h003, 4'b0111, 2'b00, 1'b1});
1223 
 
1224 
        m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0040);
1225 
        m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 16'h0fff});
1226 
        m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_ffff);
1227 
        m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_ffff);
1228 
 
1229 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
1230 
                        {12'h0000, 3'b010, 1'b0, 9'h003, 4'b0111, 2'b00, 1'b1});
1231 
 
1232 
        m0.wb_wr1(`REG_BASE + `PTR2, 4'hf, 32'h0000_0080);
1233 
        m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz, 16'h0fff});
1234 
        m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_ffff);
1235 
        m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_ffff);
1236 
 
1237 
        m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
1238 
                        {12'h0000, 3'b010, 1'b0, 9'h003, 4'b0111, 2'b00, 1'b1});
1239 
 
1240 
        m0.wb_wr1(`REG_BASE + `PTR3, 4'hf, 32'h0000_00c0);
1241 
        m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz, 16'h0fff});
1242 
        m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_ffff);
1243 
        m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_ffff);
1244 
 
1245 
        m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
1246 
                        {12'h0000, 3'b010, 1'b0, 9'h003, 4'b0111, 2'b00, 1'b1});
1247 
 
1248 
 
1249 
        $write("Total Size: %0d, Delay: %0d ",tot_sz, del);
1250 
        case(mode)
1251 
           0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz);
1252 
           1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz);
1253 
           2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz);
1254 
           3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz);
1255 
        endcase
1256 
 
1257 
        ack_cnt_clr = 1;
1258 
        @(posedge clk);
1259 
        ack_cnt_clr = 0;
1260 
 
1261 
        if(chunk_sz==0)          k = 1;
1262 
        else
1263 
           begin
1264 
                k = tot_sz/chunk_sz;
1265 
                if((k*chunk_sz) != tot_sz)      k = k + 1;
1266 
                if((k*chunk_sz) != tot_sz)      odd = 1;
1267 
                else                            odd = 0;
1268 
           end
1269 
 
1270 
        if(chunk_sz==0)          k1 = 4;
1271 
        else
1272 
           begin
1273 
                k1 = tot_sz/chunk_sz;
1274 
                if((k1*chunk_sz) != tot_sz)     k1 = k1 + 1;
1275 
                k1 = k1 * 4;
1276 
           end
1277 
 
1278 
        k1 = k * 4;
1279 
        iz = k;
1280 
 
1281 
        fork
1282 
           begin
1283 
                repeat(5)       @(posedge clk);
1284 
                for(m0=0;m0 < k1+1;m0=m0+1)
1285 
                   begin
1286 
                        repeat(del)     @(posedge clk);
1287 
                        #1;
1288 
 
1289 
                        if(m0==iz)      nd_i[0] = 1;
1290 
                        else
1291 
                        if(m0==(iz*2))  nd_i[0] = 1;
1292 
                        else
1293 
                        if(m0==(iz*3))  nd_i[0] = 1;
1294 
                        else
1295 
                        if(m0==(iz*4))  nd_i[0] = 1;
1296 
                        else            req_i[0] = 1;
1297 
 
1298 
                        if(nd_i[0]==1)
1299 
                           begin
1300 
                                @(posedge clk);
1301 
                                #1;
1302 
                                nd_i[0] = 0;
1303 
                                repeat(1)       @(posedge clk);
1304 
                                #1;
1305 
                                req_i[0] = 1;
1306 
                           end
1307 
 
1308 
                        while(!ack_o[0] & (m0 < k1))     @(posedge clk);
1309 
                        #1;
1310 
                        req_i[0] = 0;
1311 
                        nd_i[0] = 0;
1312 
                   end
1313 
           end
1314 
 
1315 
           begin
1316 
                repeat(5)       @(posedge clk);
1317 
                for(m1=0;m1 < k1;m1=m1+1)
1318 
                   begin
1319 
                        repeat(del)     @(posedge clk);
1320 
                        #1;
1321 
                        if(m1==k-1)     nd_i[1] = 1;
1322 
                        if(m1==(k*2)-1) nd_i[1] = 1;
1323 
                        if(m1==(k*3)-1) nd_i[1] = 1;
1324 
                        if(m1==(k*4)-1) nd_i[1] = 1;
1325 
                        req_i[1] = 1;
1326 
                        while(!ack_o[1])        @(posedge clk);
1327 
                        #1;
1328 
                        req_i[1] = 0;
1329 
                        nd_i[1] = 0;
1330 
                   end
1331 
           end
1332 
 
1333 
           begin
1334 
                repeat(5)       @(posedge clk);
1335 
                for(m2=0;m2 < k1+1;m2=m2+1)
1336 
                   begin
1337 
                        repeat(del)     @(posedge clk);
1338 
                        #1;
1339 
 
1340 
                        if(m2==k)       nd_i[2] = 1;
1341 
                        else
1342 
                        if(m2==(k*2))   nd_i[2] = 1;
1343 
                        else
1344 
                        if(m2==(k*3))   nd_i[2] = 1;
1345 
                        else
1346 
                        if(m2==(k*4))   nd_i[2] = 1;
1347 
                        else            req_i[2] = 1;
1348 
 
1349 
                        if(nd_i[2]==1)
1350 
                           begin
1351 
                                @(posedge clk);
1352 
                                #1;
1353 
                                nd_i[2] = 0;
1354 
                                repeat(1)       @(posedge clk);
1355 
                                #1;
1356 
                                req_i[2] = 1;
1357 
                           end
1358 
 
1359 
                        while(!ack_o[2] & (m2 < k1))    @(posedge clk);
1360 
                        #1;
1361 
                        req_i[2] = 0;
1362 
                        nd_i[2] = 0;
1363 
                   end
1364 
           end
1365 
 
1366 
 
1367 
           begin
1368 
                repeat(5)       @(posedge clk);
1369 
                for(m3=0;m3 < k1;m3=m3+1)
1370 
                   begin
1371 
                        repeat(del)     @(posedge clk);
1372 
                        #1;
1373 
                        if(m3==k-1)     nd_i[3] = 1;
1374 
                        if(m3==(k*2)-1) nd_i[3] = 1;
1375 
                        if(m3==(k*3)-1) nd_i[3] = 1;
1376 
                        if(m3==(k*4)-1) nd_i[3] = 1;
1377 
                        req_i[3] = 1;
1378 
                        while(!ack_o[3])        @(posedge clk);
1379 
                        #1;
1380 
                        req_i[3] = 0;
1381 
                        nd_i[3] = 0;
1382 
                   end
1383 
           end
1384 
 
1385 
 
1386 
           for(i=0;i<4;i=i)
1387 
           begin
1388 
                repeat(5)       @(posedge clk);
1389 
                while(!inta_o)  @(posedge clk);
1390 
                m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
1391 
 
1392 
                if(int_src[0])
1393 
                   begin
1394 
                        i=i+1;
1395 
                        for(n=0;n<tot_sz*2;n=n+1)
1396 
                           begin
1397 
                                if(mode[1])     d0=s1.mem[(s0.mem[1]>>2) + n ];
1398 
                                else            d0=s0.mem[(s0.mem[1]>>2) + n ];
1399 
                                if(mode[0])      d1=s1.mem[(s0.mem[2]>>2) + n ];
1400 
                                else            d1=s0.mem[(s0.mem[2]>>2) + n ];
1401 
 
1402 
                                if( d1 !== d0 )
1403 
                                   begin
1404 
                                        $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1405 
                                        n, d0, d1, $time);
1406 
                                        error_cnt = error_cnt + 1;
1407 
                                   end
1408 
                           end
1409 
                        repeat(1)       @(posedge clk);
1410 
                        d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
1411 
                        m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
1412 
                        repeat(1)       @(posedge clk);
1413 
                        if( d1 !== d0 )
1414 
                           begin
1415 
                                $display("ERROR: CH0: CSR Mismatch: Expected: %x, Got: %x (%0t)",
1416 
                                d1, d0, $time);
1417 
                                error_cnt = error_cnt + 1;
1418 
                           end
1419 
                   end
1420 
 
1421 
                if(int_src[1])
1422 
                   begin
1423 
                        i=i+1;
1424 
                        for(n=0;n<tot_sz*2;n=n+1)
1425 
                           begin
1426 
                                if(mode[1])     d0=s1.mem[(s0.mem[17]>>2) + n ];
1427 
                                else            d0=s0.mem[(s0.mem[17]>>2) + n ];
1428 
                                if(mode[0])      d1=s1.mem[(s0.mem[18]>>2) + n ];
1429 
                                else            d1=s0.mem[(s0.mem[18]>>2) + n ];
1430 
 
1431 
                                if( d1 !== d0 )
1432 
                                   begin
1433 
                                        $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1434 
                                        n, d0, d1, $time);
1435 
                                        error_cnt = error_cnt + 1;
1436 
                                   end
1437 
                           end
1438 
                        repeat(1)       @(posedge clk);
1439 
                        d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
1440 
                        m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
1441 
                        repeat(1)       @(posedge clk);
1442 
                        if( d1 !== d0 )
1443 
                           begin
1444 
                                $display("ERROR: CH1: CSR Mismatch: Expected: %x, Got: %x (%0t)",
1445 
                                d1, d0, $time);
1446 
                                error_cnt = error_cnt + 1;
1447 
                           end
1448 
                        repeat(1)       @(posedge clk);
1449 
                        case(chunk_sz)
1450 
                           default:     d1 = 32'h0000_00c0;
1451 
                                3:      d1 = 32'h0000_00be;
1452 
                                5:      d1 = 32'h0000_00bf;
1453 
                                6:      d1 = 32'h0000_00be;
1454 
                                7:      d1 = 32'h0000_00ba;
1455 
                        endcase
1456 
                        d0 = s0.mem[16];
1457 
                        repeat(1)       @(posedge clk);
1458 
                        if( d1 !== d0 )
1459 
                           begin
1460 
                                $display("ERROR: CH1: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)",
1461 
                                d1, d0, $time);
1462 
                                error_cnt = error_cnt + 1;
1463 
                           end
1464 
                   end
1465 
 
1466 
                if(int_src[2])
1467 
                   begin
1468 
                        i=i+1;
1469 
                        for(n=0;n<tot_sz*2;n=n+1)
1470 
                           begin
1471 
                                if(mode[1])     d0=s1.mem[(s0.mem[33]>>2) + n ];
1472 
                                else            d0=s0.mem[(s0.mem[33]>>2) + n ];
1473 
                                if(mode[0])      d1=s1.mem[(s0.mem[34]>>2) + n ];
1474 
                                else            d1=s0.mem[(s0.mem[34]>>2) + n ];
1475 
 
1476 
                                if( d1 !== d0 )
1477 
                                   begin
1478 
                                        $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1479 
                                        n, d0, d1, $time);
1480 
                                        error_cnt = error_cnt + 1;
1481 
                                   end
1482 
                           end
1483 
                        repeat(1)       @(posedge clk);
1484 
                        d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
1485 
                        m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
1486 
                        repeat(1)       @(posedge clk);
1487 
                        if( d1 !== d0 )
1488 
                           begin
1489 
                                $display("ERROR: CH2: CSR Mismatch: Expected: %x, Got: %x (%0t)",
1490 
                                d1, d0, $time);
1491 
                                error_cnt = error_cnt + 1;
1492 
                           end
1493 
                   end
1494 
 
1495 
                if(int_src[3])
1496 
                   begin
1497 
                        i=i+1;
1498 
                        for(n=0;n<tot_sz*2;n=n+1)
1499 
                           begin
1500 
                                if(mode[1])     d0=s1.mem[(s0.mem[49]>>2) + n ];
1501 
                                else            d0=s0.mem[(s0.mem[49]>>2) + n ];
1502 
                                if(mode[0])      d1=s1.mem[(s0.mem[50]>>2) + n ];
1503 
                                else            d1=s0.mem[(s0.mem[50]>>2) + n ];
1504 
 
1505 
                                if( d1 !== d0 )
1506 
                                   begin
1507 
                                        $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1508 
                                        n, d0, d1, $time);
1509 
                                        error_cnt = error_cnt + 1;
1510 
                                   end
1511 
                           end
1512 
                        repeat(1)       @(posedge clk);
1513 
                        d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
1514 
                        m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
1515 
                        repeat(1)       @(posedge clk);
1516 
                        if( d1 !== d0 )
1517 
                           begin
1518 
                                $display("ERROR: CH3: CSR Mismatch: Expected: %x, Got: %x (%0t)",
1519 
                                d1, d0, $time);
1520 
                                error_cnt = error_cnt + 1;
1521 
                           end
1522 
                        repeat(1)       @(posedge clk);
1523 
                        case(chunk_sz)
1524 
                           default:     d1 = 32'h0000_00c0;
1525 
                                3:      d1 = 32'h0000_00be;
1526 
                                5:      d1 = 32'h0000_00bf;
1527 
                                6:      d1 = 32'h0000_00be;
1528 
                                7:      d1 = 32'h0000_00ba;
1529 
                        endcase
1530 
                        d0 = s0.mem[48];
1531 
                        repeat(1)       @(posedge clk);
1532 
                        if( d1 !== d0 )
1533 
                           begin
1534 
                                $display("ERROR: CH3: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)",
1535 
                                d1, d0, $time);
1536 
                                error_cnt = error_cnt + 1;
1537 
                           end
1538 
 
1539 
                   end
1540 
 
1541 
           end
1542 
        join
1543 
 
1544 
        // CH0: 528 Acks
1545 
        // CH1: 532 Acks
1546 
        // CH2: 528 Acks
1547 
        // CH3: 532 Acks
1548 
 
1549 
        case(chunk_sz)
1550 
           default:     k = 2120;
1551 
                3:      k = 2184;
1552 
                5:      k = 2152;
1553 
                6:      k = 2184;
1554 
                7:      k = 2312;
1555 
        endcase
1556 
 
1557 
        if(ack_cnt != k )
1558 
           begin
1559 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
1560 
                k, ack_cnt, $time);
1561 
                error_cnt = error_cnt + 1;
1562 
           end
1563 
 
1564 
        repeat(5)       @(posedge clk);
1565 
 
1566 
end
1567 
 
1568 
s0.delay = 0;
1569 
s1.delay = 0;
1570 
 
1571 
show_errors;
1572 
$display("*****************************************************");
1573 
$display("*** Test DONE ...                                 ***");
1574 
$display("*****************************************************\n\n");
1575 
end
1576 
 
1577 
endtask
1578 
 
1579 
 
1580 
 
1581 
 
1582 
 
1583 
task sw_dma1;
1584 
input           quick;
1585 
 
1586 
integer         quick, tot_sz_max, chunk_sz_max;
1587 
reg     [7:0]    mode;
1588 
reg     [15:0]   chunk_sz, tot_sz;
1589 
integer         n;
1590 
reg     [31:0]   d0,d1;
1591 
 
1592 
begin
1593 
$display("\n\n");
1594 
$display("*****************************************************");
1595 
$display("*** SW DMA No Buffer (tx & chunk size test) ...   ***");
1596 
$display("*****************************************************\n");
1597 
 
1598 
case(quick)
1599 
        default:
1600 
           begin
1601 
                tot_sz_max = 1024;
1602 
                chunk_sz_max = 256;
1603 
           end
1604 
         1:
1605 
           begin
1606 
                tot_sz_max = 128;
1607 
                chunk_sz_max = 64;
1608 
           end
1609 
         2:
1610 
           begin
1611 
                tot_sz_max = 32;
1612 
                chunk_sz_max = 4;
1613 
           end
1614 
endcase
1615 
 
1616 
mode = 1;
1617 
tot_sz = 2048;
1618 
tot_sz = 16;
1619 
chunk_sz=4;
1620 
 
1621 
for(mode=0;mode<4;mode=mode+1)
1622 
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz+1)
1623 
begin
1624 
 
1625 
if(tot_sz>64)   tot_sz=tot_sz+4;
1626 
if(tot_sz>128)  tot_sz=tot_sz+12;
1627 
case(mode)
1628 
   0: $display("Mode: 0->0, tot_size: %0d", tot_sz);
1629 
   1: $display("Mode: 0->1, tot_size: %0d", tot_sz);
1630 
   2: $display("Mode: 1->0, tot_size: %0d", tot_sz);
1631 
   3: $display("Mode: 1->1, tot_size: %0d", tot_sz);
1632 
endcase
1633 
 
1634 
for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
1635 
   begin
1636 
 
1637 
        if(chunk_sz==17)        chunk_sz=128;
1638 
        if(chunk_sz==129)       chunk_sz=255;
1639 
 
1640 
        ack_cnt_clr = 1;
1641 
        @(posedge clk);
1642 
        ack_cnt_clr = 0;
1643 
 
1644 
        s0.fill_mem(1);
1645 
        s1.fill_mem(1);
1646 
 
1647 
        m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
1648 
 
1649 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz});
1650 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
1651 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
1652 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
1653 
                {12'h0000, 3'b010, 1'b0, 11'h000, 2'b11, mode[1:0], 1'b1});
1654 
 
1655 
        repeat(5)       @(posedge clk);
1656 
        while(!inta_o)  @(posedge clk);
1657 
 
1658 
        m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d1);
1659 
        d0 = 32'h0000_0001;
1660 
        if( d1 !== d0 )
1661 
           begin
1662 
                $display("ERROR: INT_SRCA Mismatch: Expected: %x, Got: %x (%0t)",
1663 
                        d0, d1, $time);
1664 
                error_cnt = error_cnt + 1;
1665 
           end
1666 
 
1667 
        m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1);
1668 
        d0 = {24'h0064_081, 1'b1, mode[1:0], 1'b0};
1669 
        if( d1 !== d0 )
1670 
           begin
1671 
                $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)",
1672 
                        d0, d1, $time);
1673 
                error_cnt = error_cnt + 1;
1674 
           end
1675 
 
1676 
        for(n=0;n<tot_sz;n=n+1)
1677 
           begin
1678 
                if(mode[1])     d0=s1.mem[ n ];
1679 
                else            d0=s0.mem[ n ];
1680 
                if(mode[0])      d1=s1.mem[32'h0000_1000 + n ];
1681 
                else            d1=s0.mem[32'h0000_1000 + n ];
1682 
 
1683 
                if( d1 !== d0 )
1684 
                   begin
1685 
                        $display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1686 
                        n, d0, d1, $time);
1687 
                        error_cnt = error_cnt + 1;
1688 
                   end
1689 
           end
1690 
 
1691 
        if(ack_cnt != ((tot_sz*2)) )
1692 
           begin
1693 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
1694 
                ((tot_sz*2)), ack_cnt, $time);
1695 
                error_cnt = error_cnt + 1;
1696 
           end
1697 
 
1698 
   end
1699 
end
1700 
 
1701 
show_errors;
1702 
$display("*****************************************************");
1703 
$display("*** Test DONE ...                                 ***");
1704 
$display("*****************************************************\n\n");
1705 
end
1706 
endtask
1707 
 
1708 
 
1709 
 
1710 
task sw_dma2;
1711 
input           quick;
1712 
 
1713 
integer         quick, tot_sz_max, chunk_sz_max, max_del;
1714 
 
1715 
reg     [7:0]    mode;
1716 
reg     [15:0]   chunk_sz, tot_sz;
1717 
integer         n;
1718 
reg     [31:0]   d0,d1;
1719 
integer         del0, del1;
1720 
 
1721 
begin
1722 
$display("\n\n");
1723 
$display("*****************************************************");
1724 
$display("*** SW DMA No Buffer (slave delay slide) ...      ***");
1725 
$display("*****************************************************\n");
1726 
 
1727 
case(quick)
1728 
        default:
1729 
           begin
1730 
                max_del =  6;
1731 
                tot_sz_max = 256;
1732 
                chunk_sz_max = 16;
1733 
           end
1734 
         1:
1735 
           begin
1736 
                max_del =  4;
1737 
                tot_sz_max = 128;
1738 
                chunk_sz_max = 8;
1739 
           end
1740 
         2:
1741 
           begin
1742 
                max_del =  2;
1743 
                tot_sz_max = 32;
1744 
                chunk_sz_max = 4;
1745 
           end
1746 
endcase
1747 
 
1748 
mode = 0;
1749 
tot_sz = 2048;
1750 
tot_sz = 16;
1751 
chunk_sz=4;
1752 
 
1753 
for(del0=0;del0<max_del;del0=del0+1)
1754 
for(del1=0;del1<max_del;del1=del1+1)
1755 
for(mode=0;mode<4;mode=mode+1)
1756 
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz+4)
1757 
begin
1758 
 
1759 
if(del0==5)     del0=8;
1760 
if(del1==5)     del1=8;
1761 
 
1762 
if(tot_sz>128)                  tot_sz=tot_sz+4;
1763 
 
1764 
$write("Slv 0 delay: %0d, Slv 1 Delay: %0d - ",del0, del1);
1765 
case(mode)
1766 
   0: $display("Mode: 0->0, tot_size: %0d", tot_sz);
1767 
   1: $display("Mode: 0->1, tot_size: %0d", tot_sz);
1768 
   2: $display("Mode: 1->0, tot_size: %0d", tot_sz);
1769 
   3: $display("Mode: 1->1, tot_size: %0d", tot_sz);
1770 
endcase
1771 
 
1772 
for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
1773 
 
1774 
   begin
1775 
 
1776 
        if(quick & (chunk_sz > 4))      chunk_sz = chunk_sz + 1;
1777 
 
1778 
        s0.delay = del0;
1779 
        s1.delay = del1;
1780 
 
1781 
        ack_cnt_clr = 1;
1782 
        @(posedge clk);
1783 
        ack_cnt_clr = 0;
1784 
 
1785 
        s0.fill_mem(1);
1786 
        s1.fill_mem(1);
1787 
        m0.wb_wr1(`REG_BASE + `INT_MASKB,4'hf,32'hffff_ffff);
1788 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz});
1789 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
1790 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
1791 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
1792 
                {12'h0000, 3'b010, 1'b0, 11'h000, 2'b11, mode[1:0], 1'b1});
1793 
 
1794 
        repeat(5)       @(posedge clk);
1795 
        while(!intb_o)  @(posedge clk);
1796 
 
1797 
        m0.wb_rd1(`REG_BASE + `INT_SRCB, 4'hf, d1);
1798 
        d0 = 32'h0000_0001;
1799 
        if( d1 !== d0 )
1800 
           begin
1801 
                $display("ERROR: INT_SRC Mismatch: Expected: %x, Got: %x (%0t)",
1802 
                        d0, d1, $time);
1803 
                error_cnt = error_cnt + 1;
1804 
           end
1805 
 
1806 
        m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1);
1807 
        d0 = {24'h0064_081, 1'b1, mode[1:0], 1'b0};
1808 
        if( d1 !== d0 )
1809 
           begin
1810 
                $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)",
1811 
                        d0, d1, $time);
1812 
                error_cnt = error_cnt + 1;
1813 
           end
1814 
 
1815 
        for(n=0;n<tot_sz;n=n+1)
1816 
           begin
1817 
                if(mode[1])     d0=s1.mem[ n ];
1818 
                else            d0=s0.mem[ n ];
1819 
                if(mode[0])      d1=s1.mem[32'h0000_1000 + n ];
1820 
                else            d1=s0.mem[32'h0000_1000 + n ];
1821 
 
1822 
                if( d1 !== d0 )
1823 
                   begin
1824 
                        $display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
1825 
                        n, d0, d1, $time);
1826 
                        error_cnt = error_cnt + 1;
1827 
                   end
1828 
           end
1829 
 
1830 
 
1831 
        if(ack_cnt != ((tot_sz*2)) )
1832 
           begin
1833 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
1834 
                ((tot_sz*2)), ack_cnt, $time);
1835 
                error_cnt = error_cnt + 1;
1836 
           end
1837 
 
1838 
 
1839 
   end
1840 
end
1841 
 
1842 
s0.delay = 0;
1843 
s1.delay = 0;
1844 
 
1845 
show_errors;
1846 
$display("*****************************************************");
1847 
$display("*** Test DONE ...                                 ***");
1848 
$display("*****************************************************\n\n");
1849 
end
1850 
endtask
1851 
 
1852 
 
1853 
 
1854 
task pt10_rd;
1855 
 
1856 
// Misc Variables
1857 
reg     [31:0]   d0,d1,d2,d3;
1858 
integer         d,n;
1859 
 
1860 
begin
1861 
$display("\n");
1862 
$display("*****************************************************");
1863 
$display("*** Running Path Through 1->0 Read Test ....      ***");
1864 
$display("*****************************************************\n");
1865 
 
1866 
s0.fill_mem(1);
1867 
s1.fill_mem(1);
1868 
d=0;
1869 
n=16;
1870 
 
1871 
for(d=0;d<16;d=d+1)
1872 
 begin
1873 
   $display("INFO: PT10 RD4, delay %0d",d);
1874 
   for(n=0;n<512;n=n+4)
1875 
     begin
1876 
        m0.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3);
1877 
 
1878 
        if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) |
1879 
                (s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) )
1880 
           begin
1881 
                $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
1882 
                $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0);
1883 
                $display("D1: Expected: %x, Got %x", s1.mem[n+1], d1);
1884 
                $display("D2: Expected: %x, Got %x", s1.mem[n+2], d2);
1885 
                $display("D3: Expected: %x, Got %x", s1.mem[n+3], d3);
1886 
                error_cnt = error_cnt + 1;
1887 
           end
1888 
      end
1889 
 end
1890 
 
1891 
 
1892 
$display("\nINFO: PT10 RD1");
1893 
   for(n=0;n<512;n=n+1)
1894 
     begin
1895 
        m0.wb_rd1(n<<2,4'hf,d0);
1896 
 
1897 
        if( s1.mem[n] !== d0 )
1898 
           begin
1899 
                $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
1900 
                $display("D0: Expected: %x, Got %x", s1.mem[n], d0);
1901 
                error_cnt = error_cnt + 1;
1902 
           end
1903 
      end
1904 
 
1905 
 
1906 
show_errors;
1907 
$display("*****************************************************");
1908 
$display("*** Test DONE ...                                 ***");
1909 
$display("*****************************************************\n");
1910 
end
1911 
endtask
1912 
 
1913 
 
1914 
task pt01_rd;
1915 
 
1916 
// Misc Variables
1917 
reg     [31:0]   d0,d1,d2,d3;
1918 
integer         d,n;
1919 
 
1920 
begin
1921 
$display("\n");
1922 
$display("*****************************************************");
1923 
$display("*** Running Path Through 0->1 Read Test ....      ***");
1924 
$display("*****************************************************\n");
1925 
 
1926 
s0.fill_mem(1);
1927 
s1.fill_mem(1);
1928 
 
1929 
d=1;
1930 
n=0;
1931 
for(d=0;d<16;d=d+1)
1932 
 begin
1933 
   $display("INFO: PT01 RD4, delay %0d",d);
1934 
   for(n=0;n<512;n=n+4)
1935 
     begin
1936 
        m1.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3);
1937 
        @(posedge clk);
1938 
 
1939 
        if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) |
1940 
                (s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) )
1941 
           begin
1942 
                $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
1943 
                $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
1944 
                $display("D1: Expected: %x, Got %x", s0.mem[n+1], d1);
1945 
                $display("D2: Expected: %x, Got %x", s0.mem[n+2], d2);
1946 
                $display("D3: Expected: %x, Got %x", s0.mem[n+3], d3);
1947 
                error_cnt = error_cnt + 1;
1948 
           end
1949 
      end
1950 
 end
1951 
 
1952 
$display("\nINFO: PT01 RD1");
1953 
   for(n=0;n<512;n=n+1)
1954 
     begin
1955 
        m1.wb_rd1(n<<2,4'hf,d0);
1956 
 
1957 
        if( s0.mem[n+0] !== d0 )
1958 
           begin
1959 
                $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
1960 
                $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
1961 
                error_cnt = error_cnt + 1;
1962 
           end
1963 
      end
1964 
 
1965 
show_errors;
1966 
$display("*****************************************************");
1967 
$display("*** Test DONE ...                                 ***");
1968 
$display("*****************************************************\n");
1969 
end
1970 
endtask
1971 
 
1972 
 
1973 
 
1974 
 
1975 
task pt10_wr;
1976 
 
1977 
// Misc Variables
1978 
reg     [31:0]   d0,d1,d2,d3;
1979 
integer         d,n;
1980 
 
1981 
begin
1982 
 
1983 
$display("\n");
1984 
$display("*****************************************************");
1985 
$display("*** Running Path Through 1->0 Write Test ....     ***");
1986 
$display("*****************************************************\n");
1987 
 
1988 
 
1989 
s0.fill_mem(1);
1990 
s1.fill_mem(1);
1991 
d=1;
1992 
n=0;
1993 
for(d=0;d<16;d=d+1)
1994 
 begin
1995 
   $display("INFO: PT10 WR4, delay %0d",d);
1996 
   for(n=0;n<512;n=n+4)
1997 
     begin
1998 
 
1999 
        d0 = $random;
2000 
        d1 = $random;
2001 
        d2 = $random;
2002 
        d3 = $random;
2003 
        m0.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3);
2004 
        @(posedge clk);
2005 
 
2006 
        if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) |
2007 
                (s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) )
2008 
           begin
2009 
                $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
2010 
                $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0);
2011 
                $display("D1: Expected: %x, Got %x", s1.mem[n+1], d1);
2012 
                $display("D2: Expected: %x, Got %x", s1.mem[n+2], d2);
2013 
                $display("D3: Expected: %x, Got %x", s1.mem[n+3], d3);
2014 
                error_cnt = error_cnt + 1;
2015 
           end
2016 
      end
2017 
 end
2018 
 
2019 
$display("\nINFO: PT10 WR1");
2020 
   for(n=0;n<512;n=n+1)
2021 
     begin
2022 
        d0 = $random;
2023 
        m0.wb_wr1(n<<2,4'hf,d0);
2024 
        @(posedge clk);
2025 
 
2026 
        if( s1.mem[n+0] !== d0 )
2027 
           begin
2028 
                $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
2029 
                $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0);
2030 
                error_cnt = error_cnt + 1;
2031 
           end
2032 
      end
2033 
 
2034 
show_errors;
2035 
$display("*****************************************************");
2036 
$display("*** Test DONE ...                                 ***");
2037 
$display("*****************************************************\n");
2038 
end
2039 
endtask
2040 
 
2041 
 
2042 
 
2043 
task pt01_wr;
2044 
 
2045 
// Misc Variables
2046 
reg     [31:0]   d0,d1,d2,d3;
2047 
integer         d,n;
2048 
 
2049 
begin
2050 
 
2051 
$display("\n");
2052 
$display("*****************************************************");
2053 
$display("*** Running Path Through 0->1 Write Test ....     ***");
2054 
$display("*****************************************************\n");
2055 
 
2056 
 
2057 
s0.fill_mem(1);
2058 
s1.fill_mem(1);
2059 
 
2060 
d=1;
2061 
n=0;
2062 
for(d=0;d<16;d=d+1)
2063 
 begin
2064 
   $display("INFO: PT01 WR4, delay %0d",d);
2065 
   for(n=0;n<512;n=n+4)
2066 
     begin
2067 
 
2068 
        d0 = $random;
2069 
        d1 = $random;
2070 
        d2 = $random;
2071 
        d3 = $random;
2072 
        m1.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3);
2073 
        @(posedge clk);
2074 
 
2075 
        if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) |
2076 
                (s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) )
2077 
           begin
2078 
                $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
2079 
                $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
2080 
                $display("D1: Expected: %x, Got %x", s0.mem[n+1], d1);
2081 
                $display("D2: Expected: %x, Got %x", s0.mem[n+2], d2);
2082 
                $display("D3: Expected: %x, Got %x", s0.mem[n+3], d3);
2083 
                error_cnt = error_cnt + 1;
2084 
           end
2085 
      end
2086 
 end
2087 
 
2088 
   $display("\nINFO: PT01 WR1");
2089 
   for(n=0;n<512;n=n+1)
2090 
     begin
2091 
        d0 = $random;
2092 
        m1.wb_wr1(n<<2,4'hf,d0);
2093 
        @(posedge clk);
2094 
 
2095 
        if( s0.mem[n+0] !== d0 )
2096 
           begin
2097 
                $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
2098 
                $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
2099 
                error_cnt = error_cnt + 1;
2100 
           end
2101 
      end
2102 
 
2103 
show_errors;
2104 
$display("*****************************************************");
2105 
$display("*** Test DONE ...                                 ***");
2106 
$display("*****************************************************\n");
2107 
end
2108 
endtask
2109 
 
2110 
 
2111 
 
2112 
 
2113 
 
2114 
 
2115 
 
2116 
task show_errors;
2117 
 
2118 
begin
2119 
 
2120 
$display("\n");
2121 
$display("     +--------------------+");
2122 
$display("     |  Total ERRORS: %0d   |", error_cnt);
2123 
$display("     +--------------------+");
2124 
 
2125 
end
2126 
endtask
2127 
 
2128 
 
2129 
 
2130 
task hw_dma4;
2131 
input           quick;
2132 
 
2133 
integer         quick, tot_sz_max, chunk_sz_max, del_max;
2134 
 
2135 
reg     [7:0]    mode;
2136 
reg     [15:0]   chunk_sz, tot_sz;
2137 
integer         i, n,m0, m1, m2, m3, k,rep,del;
2138 
reg     [31:0]   int_src, d0,d1;
2139 
reg             do_rest;
2140 
integer         rest_del;
2141 
integer         rest_del_t;
2142 
 
2143 
begin
2144 
$display("\n\n");
2145 
$display("*****************************************************");
2146 
$display("*** HW DMA No Buffer Ext Descr. REST Test ...     ***");
2147 
$display("*****************************************************\n");
2148 
 
2149 
case(quick)
2150 
        default:
2151 
           begin
2152 
                del_max = 6;
2153 
                tot_sz_max = 200;
2154 
                chunk_sz_max = 8;
2155 
           end
2156 
         1:
2157 
           begin
2158 
                del_max = 4;
2159 
                tot_sz_max = 128;
2160 
                chunk_sz_max = 4;
2161 
           end
2162 
         2:
2163 
           begin
2164 
                del_max = 3;
2165 
                tot_sz_max = 32;
2166 
                chunk_sz_max = 4;
2167 
           end
2168 
endcase
2169 
 
2170 
mode = 1;
2171 
tot_sz = 32;
2172 
chunk_sz=7;
2173 
del = 0;
2174 
do_rest = 1;
2175 
rest_del = 7;
2176 
 
2177 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0);
2178 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0);
2179 
        m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0);
2180 
        m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0);
2181 
 
2182 
        m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
2183 
 
2184 
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz+1)
2185 
begin
2186 
 
2187 
if(tot_sz>4)    tot_sz = tot_sz + 4;
2188 
if(tot_sz>16)   tot_sz = tot_sz + 12;
2189 
if(tot_sz>64)   tot_sz = tot_sz + 48;
2190 
 
2191 
for(del=0;del<del_max;del=del+1)
2192 
//for(mode=0;mode<4;mode=mode+1)
2193 
//for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
2194 
 
2195 
for(rest_del=0;rest_del<16;rest_del=rest_del + 1)
2196 
for(chunk_sz=1;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
2197 
begin
2198 
do_rest = 1;
2199 
        s0.delay = del;
2200 
        s1.delay = del;
2201 
 
2202 
        s0.fill_mem(1);
2203 
        s1.fill_mem(1);
2204 
 
2205 
        s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
2206 
        s0.mem[1] = 32'h0000_0100;
2207 
        s0.mem[2] = 32'h0000_0900;
2208 
        s0.mem[3] = 32'h0000_0010;
2209 
 
2210 
        s0.mem[4] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
2211 
        s0.mem[5] = 32'h0000_0100 + (tot_sz * 4);
2212 
        s0.mem[6] = 32'h0000_0900 + (tot_sz * 4);
2213 
        s0.mem[7] = 32'h0000_0000;
2214 
 
2215 
        s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
2216 
        s0.mem[9] = 32'h0000_1100;
2217 
        s0.mem[10] = 32'h0000_1900;
2218 
        s0.mem[11] = 32'h0000_0030;
2219 
 
2220 
        s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
2221 
        s0.mem[13] = 32'h0000_1100 + (tot_sz * 4);
2222 
        s0.mem[14] = 32'h0000_1900 + (tot_sz * 4);
2223 
        s0.mem[15] = 32'h0000_0000;
2224 
 
2225 
        s0.mem[16] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
2226 
        s0.mem[17] = 32'h0000_2100;
2227 
        s0.mem[18] = 32'h0000_2900;
2228 
        s0.mem[19] = 32'h0000_0050;
2229 
 
2230 
        s0.mem[20] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
2231 
        s0.mem[21] = 32'h0000_2100 + (tot_sz * 4);
2232 
        s0.mem[22] = 32'h0000_2900 + (tot_sz * 4);
2233 
        s0.mem[23] = 32'h0000_0000;
2234 
 
2235 
        s0.mem[24] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
2236 
        s0.mem[25] = 32'h0000_3100;
2237 
        s0.mem[26] = 32'h0000_3900;
2238 
        s0.mem[27] = 32'h0000_0070;
2239 
 
2240 
        s0.mem[28] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
2241 
        s0.mem[29] = 32'h0000_3100 + (tot_sz * 4);
2242 
        s0.mem[30] = 32'h0000_3900 + (tot_sz * 4);
2243 
        s0.mem[31] = 32'h0000_0000;
2244 
 
2245 
        m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
2246 
 
2247 
        m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0000);
2248 
        m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 16'h0fff});
2249 
        m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_ffff);
2250 
        m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_ffff);
2251 
 
2252 
        m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
2253 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
2254 
                        {12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});
2255 
 
2256 
        m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0020);
2257 
        m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 16'h0fff});
2258 
        m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_ffff);
2259 
        m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_ffff);
2260 
 
2261 
        m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
2262 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
2263 
                        {12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});
2264 
 
2265 
        m0.wb_wr1(`REG_BASE + `PTR2, 4'hf, 32'h0000_0040);
2266 
        m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz, 16'h0fff});
2267 
        m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_ffff);
2268 
        m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_ffff);
2269 
 
2270 
        m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
2271 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
2272 
                        {12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});
2273 
 
2274 
        m0.wb_wr1(`REG_BASE + `PTR3, 4'hf, 32'h0000_0060);
2275 
        m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz, 16'h0fff});
2276 
        m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_ffff);
2277 
        m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_ffff);
2278 
 
2279 
        m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
2280 
                        //{25'h0000001, 4'b0111, 2'b00, 1'b1});
2281 
                        {12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});
2282 
 
2283 
 
2284 
        ack_cnt_clr = 1;
2285 
        @(posedge clk);
2286 
        ack_cnt_clr = 0;
2287 
 
2288 
        if(chunk_sz==0)          k = 1;
2289 
        else
2290 
           begin
2291 
                k = tot_sz/chunk_sz;
2292 
                if((k*chunk_sz) != tot_sz)      k = k + 1;
2293 
           end
2294 
 
2295 
//$display("rest_del: %0d, k: %0d", rest_del, k);
2296 
 
2297 
        if(rest_del >= k)       rest_del_t = k - 1;
2298 
        else                    rest_del_t = rest_del;
2299 
 
2300 
        k = k * 2;
2301 
 
2302 
 
2303 
        $write("Total Size: %0d, Delay: %0d REST_del: %0d ",tot_sz, del, rest_del_t);
2304 
        case(mode)
2305 
           0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz);
2306 
           1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz);
2307 
           2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz);
2308 
           3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz);
2309 
        endcase
2310 
 
2311 
 
2312 
 
2313 
//$display("k=%0d",k);
2314 
 
2315 
        fork
2316 
           begin        // Hardware Handshake Channel 0
2317 
                repeat(5)       @(posedge clk);
2318 
                for(m0=0;m0 < k;m0=m0+1)
2319 
                   begin
2320 
                        repeat(del)     @(posedge clk);
2321 
                        #1;
2322 
                        req_i[0] = 1;
2323 
                        while(!ack_o[0]) @(posedge clk);
2324 
                        #1;
2325 
                        req_i[0] = 0;
2326 
                   end
2327 
           end
2328 
 
2329 
           begin        // Hardware Handshake Channel 1
2330 
                repeat(5)       @(posedge clk);
2331 
                for(m1=0;m1 < (k + rest_del_t + 1);m1=m1+1)
2332 
                   begin
2333 
                        repeat(del)     @(posedge clk);
2334 
                        #1;
2335 
                        req_i[1] = 1;
2336 
                        while(!ack_o[1])        @(posedge clk);
2337 
                        #1;
2338 
                        req_i[1] = 0;
2339 
//$display("m1=%0d",m1);
2340 
                        if( (do_rest==1) & (m1==rest_del_t) )
2341 
                        //if( do_rest==1 )
2342 
                           begin
2343 
//$display("Asserting Restart ...");
2344 
                                @(posedge clk);
2345 
                                #1;
2346 
                                rest_i[1] = 1;
2347 
                                @(posedge clk);
2348 
                                #1;
2349 
                                rest_i[1] = 0;
2350 
                                do_rest = 0;
2351 
                                @(posedge clk);
2352 
                                @(posedge clk);
2353 
                           end
2354 
 
2355 
                   end
2356 
           end
2357 
 
2358 
           begin        // Hardware Handshake Channel 2
2359 
                repeat(5)       @(posedge clk);
2360 
                for(m2=0;m2 < k;m2=m2+1)
2361 
                   begin
2362 
                        repeat(del)     @(posedge clk);
2363 
                        #1;
2364 
                        req_i[2] = 1;
2365 
                        while(!ack_o[2])        @(posedge clk);
2366 
                        #1;
2367 
                        req_i[2] = 0;
2368 
                   end
2369 
           end
2370 
 
2371 
           begin        // Hardware Handshake Channel 3
2372 
                repeat(5)       @(posedge clk);
2373 
                for(m3=0;m3 < k;m3=m3+1)
2374 
                   begin
2375 
                        repeat(del)     @(posedge clk);
2376 
                        #1;
2377 
                        req_i[3] = 1;
2378 
                        while(!ack_o[3])        @(posedge clk);
2379 
                        #1;
2380 
                        req_i[3] = 0;
2381 
                   end
2382 
           end
2383 
 
2384 
           for(i=0;i<4;i=i)
2385 
           begin
2386 
                repeat(5)       @(posedge clk);
2387 
                while(!inta_o)  @(posedge clk);
2388 
                m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
2389 
 
2390 
                if(int_src[0])
2391 
                   begin
2392 
                        m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
2393 
                        i=i+1;
2394 
                        for(n=0;n<tot_sz*2;n=n+1)
2395 
                           begin
2396 
                                if(mode[1])     d0=s1.mem[(s0.mem[1]>>2) + n ];
2397 
                                else            d0=s0.mem[(s0.mem[1]>>2) + n ];
2398 
                                if(mode[0])      d1=s1.mem[(s0.mem[2]>>2) + n ];
2399 
                                else            d1=s0.mem[(s0.mem[2]>>2) + n ];
2400 
 
2401 
                                if( d1 !== d0 )
2402 
                                   begin
2403 
                                        $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
2404 
                                        n, d0, d1, $time);
2405 
                                        error_cnt = error_cnt + 1;
2406 
                                   end
2407 
                           end
2408 
                   end
2409 
 
2410 
                if(int_src[1])
2411 
                   begin
2412 
                        m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
2413 
                        i=i+1;
2414 
                        for(n=0;n<tot_sz*2;n=n+1)
2415 
                           begin
2416 
                                if(mode[1])     d0=s1.mem[(s0.mem[9]>>2) + n ];
2417 
                                else            d0=s0.mem[(s0.mem[9]>>2) + n ];
2418 
                                if(mode[0])      d1=s1.mem[(s0.mem[10]>>2) + n ];
2419 
                                else            d1=s0.mem[(s0.mem[10]>>2) + n ];
2420 
 
2421 
                                if( d1 !== d0 )
2422 
                                   begin
2423 
                                        $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
2424 
                                        n, d0, d1, $time);
2425 
                                        error_cnt = error_cnt + 1;
2426 
                                   end
2427 
                           end
2428 
                   end
2429 
 
2430 
                if(int_src[2])
2431 
                   begin
2432 
                        m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
2433 
                        i=i+1;
2434 
                        for(n=0;n<tot_sz*2;n=n+1)
2435 
                           begin
2436 
                                if(mode[1])     d0=s1.mem[(s0.mem[17]>>2) + n ];
2437 
                                else            d0=s0.mem[(s0.mem[17]>>2) + n ];
2438 
                                if(mode[0])      d1=s1.mem[(s0.mem[18]>>2) + n ];
2439 
                                else            d1=s0.mem[(s0.mem[18]>>2) + n ];
2440 
 
2441 
                                if( d1 !== d0 )
2442 
                                   begin
2443 
                                        $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
2444 
                                        n, d0, d1, $time);
2445 
                                        error_cnt = error_cnt + 1;
2446 
                                   end
2447 
                           end
2448 
                   end
2449 
 
2450 
                if(int_src[3])
2451 
                   begin
2452 
                        m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
2453 
                        i=i+1;
2454 
                        for(n=0;n<tot_sz*2;n=n+1)
2455 
                           begin
2456 
                                if(mode[1])     d0=s1.mem[(s0.mem[25]>>2) + n ];
2457 
                                else            d0=s0.mem[(s0.mem[25]>>2) + n ];
2458 
                                if(mode[0])      d1=s1.mem[(s0.mem[26]>>2) + n ];
2459 
                                else            d1=s0.mem[(s0.mem[26]>>2) + n ];
2460 
 
2461 
                                if( d1 !== d0 )
2462 
                                   begin
2463 
                                        $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
2464 
                                        n, d0, d1, $time);
2465 
                                        error_cnt = error_cnt + 1;
2466 
                                   end
2467 
                           end
2468 
                   end
2469 
 
2470 
           end
2471 
 
2472 
        join
2473 
 
2474 
 
2475 
/*
2476 
        if(ack_cnt != ((tot_sz*2*4*2)+(4*4*2)) )
2477 
           begin
2478 
                $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
2479 
                ((tot_sz*2*4*2)+(4*4*2)), ack_cnt, $time);
2480 
                error_cnt = error_cnt + 1;
2481 
           end
2482 
*/
2483 
 
2484 
        repeat(5)       @(posedge clk);
2485 
 
2486 
end
2487 
end
2488 
 
2489 
        s0.delay = 0;
2490 
        s1.delay = 0;
2491 
 
2492 
show_errors;
2493 
$display("*****************************************************");
2494 
$display("*** Test DONE ...                                 ***");
2495 
$display("*****************************************************\n\n");
2496 
end
2497 
 
2498 
endtask
2499 
 
2500 
 
2501 
 
2502 
 

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