URL https://opencores.org/ocsvn/wb_dma/wb_dma/trunk

Subversion Repositories wb_dma

[/] [wb_dma/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 15

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.3 2002-02-01 01:55:44 rudi Exp $
//
//  $Date: 2002-02-01 01:55:44 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/09/07 15:34:36  rudi
//
//               Changed reset to active high.
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.1.1.1  2001/03/19 13:11:34  rudi
//               Initial Release
//
//
//
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   rd_mem[mem_size:0];
reg     [31:0]   wr_mem[mem_size:0];
integer         rd_cnt;
integer         wr_cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        rd_cnt = 0;
        wr_cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
 
task mem_fill;
 
integer n;
begin
rd_cnt = 0;
wr_cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        rd_mem[n] = $random;
        wr_mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
 
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
//      if(n!=0)
                @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + wcount;
end
endtask
 
 
 
 
task wb_wmr;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
wr_cnt = wr_cnt + wcount;
stb=0;
repeat(delay)   @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
rd_cnt = rd_cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
 
cyc = 0;
stb = 0;
we  = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask
 
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + count;
end
endtask
 
endmodule

Browse

Tools

Subversion Repositories wb_dma

[/] [wb_dma/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	15	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17	5	rudi	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	15	rudi	`// $Id: wb_mast_model.v,v 1.3 2002-02-01 01:55:44 rudi Exp $`
42	5	rudi	`//`
43	15	rudi	`// $Date: 2002-02-01 01:55:44 $`
44			`// $Revision: 1.3 $`
45	5	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	15	rudi	`// Revision 1.2 2001/09/07 15:34:36 rudi`
52			`//`
53			`// Changed reset to active high.`
54			`//`
55	9	rudi	`// Revision 1.1 2001/07/29 08:57:02 rudi`
56			`//`
57			`//`
58			`// 1) Changed Directory Structure`
59			`// 2) Added restart signal (REST)`
60			`//`
61	5	rudi	`// Revision 1.1.1.1 2001/03/19 13:11:34 rudi`
62			`// Initial Release`
63			`//`
64			`//`
65	9	rudi	`//`
66	5	rudi
67			`include "wb_model_defines.v"
68
69			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
70
71			`input clk, rst;`
72			`output [31:0] adr;`
73			`input [31:0] din;`
74			`output [31:0] dout;`
75			`output cyc, stb;`
76			`output [3:0] sel;`
77			`output we;`
78			`input ack, err, rty;`
79
80			`////////////////////////////////////////////////////////////////////`
81			`//`
82			`// Local Wires`
83			`//`
84
85	9	rudi	`parameter mem_size = 4096;`
86
87	5	rudi	`reg [31:0] adr;`
88			`reg [31:0] dout;`
89			`reg cyc, stb;`
90			`reg [3:0] sel;`
91			`reg we;`
92
93	9	rudi	`reg [31:0] rd_mem[mem_size:0];`
94			`reg [31:0] wr_mem[mem_size:0];`
95			`integer rd_cnt;`
96			`integer wr_cnt;`
97
98	5	rudi	`////////////////////////////////////////////////////////////////////`
99			`//`
100			`// Memory Logic`
101			`//`
102
103			`initial`
104			`begin`
105			`//adr = 32'hxxxx_xxxx;`
106			`//adr = 0;`
107			`adr = 32'hffff_ffff;`
108			`dout = 32'hxxxx_xxxx;`
109			`cyc = 0;`
110			`stb = 0;`
111			`sel = 4'hx;`
112			`we = 1'hx;`
113	9	rudi	`rd_cnt = 0;`
114			`wr_cnt = 0;`
115	5	rudi	`#1;`
116			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
117			`end`
118
119	9	rudi
120
121			`task mem_fill;`
122
123			`integer n;`
124			`begin`
125			`rd_cnt = 0;`
126			`wr_cnt = 0;`
127			`for(n=0;n<mem_size;n=n+1)`
128			`begin`
129			`rd_mem[n] = $random;`
130			`wr_mem[n] = $random;`
131			`end`
132			`end`
133			`endtask`
134
135	5	rudi	`////////////////////////////////////////////////////////////////////`
136			`//`
137			`// Write 1 Word Task`
138			`//`
139
140			`task wb_wr1;`
141			`input [31:0] a;`
142			`input [3:0] s;`
143			`input [31:0] d;`
144
145			`begin`
146
147			`@(posedge clk);`
148			`#1;`
149			`adr = a;`
150			`dout = d;`
151			`cyc = 1;`
152			`stb = 1;`
153			`we=1;`
154			`sel = s;`
155
156			`@(posedge clk);`
157	9	rudi	`while(~ack & ~err) @(posedge clk);`
158	5	rudi	`#1;`
159			`cyc=0;`
160			`stb=0;`
161			`adr = 32'hxxxx_xxxx;`
162	9	rudi	`//adr = 32'hffff_ffff;`
163			`//adr = 0;`
164	5	rudi	`dout = 32'hxxxx_xxxx;`
165			`we = 1'hx;`
166			`sel = 4'hx;`
167
168			`end`
169			`endtask`
170
171			`////////////////////////////////////////////////////////////////////`
172			`//`
173			`// Write 4 Words Task`
174			`//`
175
176			`task wb_wr4;`
177			`input [31:0] a;`
178			`input [3:0] s;`
179			`input delay;`
180			`input [31:0] d1;`
181			`input [31:0] d2;`
182			`input [31:0] d3;`
183			`input [31:0] d4;`
184
185			`integer delay;`
186
187			`begin`
188
189			`@(posedge clk);`
190			`#1;`
191			`cyc = 1;`
192			`sel = s;`
193
194			`repeat(delay)`
195			`begin`
196			`@(posedge clk);`
197			`#1;`
198			`end`
199			`adr = a;`
200			`dout = d1;`
201			`stb = 1;`
202			`we=1;`
203	9	rudi	`while(~ack & ~err) @(posedge clk);`
204	5	rudi	`#2;`
205			`stb=0;`
206			`we=1'bx;`
207			`dout = 32'hxxxx_xxxx;`
208
209
210			`repeat(delay)`
211			`begin`
212			`@(posedge clk);`
213			`#1;`
214			`end`
215			`stb=1;`
216			`adr = a+4;`
217			`dout = d2;`
218			`we=1;`
219			`@(posedge clk);`
220	9	rudi	`while(~ack & ~err) @(posedge clk);`
221	5	rudi	`#2;`
222			`stb=0;`
223			`we=1'bx;`
224			`dout = 32'hxxxx_xxxx;`
225
226			`repeat(delay)`
227			`begin`
228			`@(posedge clk);`
229			`#1;`
230			`end`
231			`stb=1;`
232			`adr = a+8;`
233			`dout = d3;`
234			`we=1;`
235			`@(posedge clk);`
236	9	rudi	`while(~ack & ~err) @(posedge clk);`
237	5	rudi	`#2;`
238			`stb=0;`
239			`we=1'bx;`
240			`dout = 32'hxxxx_xxxx;`
241
242			`repeat(delay)`
243			`begin`
244			`@(posedge clk);`
245			`#1;`
246			`end`
247			`stb=1;`
248			`adr = a+12;`
249			`dout = d4;`
250			`we=1;`
251			`@(posedge clk);`
252	9	rudi	`while(~ack & ~err) @(posedge clk);`
253	5	rudi	`#1;`
254			`stb=0;`
255			`cyc=0;`
256
257			`adr = 32'hxxxx_xxxx;`
258	9	rudi	`//adr = 0;`
259			`//adr = 32'hffff_ffff;`
260	5	rudi	`dout = 32'hxxxx_xxxx;`
261			`we = 1'hx;`
262			`sel = 4'hx;`
263
264			`end`
265			`endtask`
266
267
268	9	rudi	`task wb_wr_mult;`
269			`input [31:0] a;`
270			`input [3:0] s;`
271			`input delay;`
272			`input count;`
273
274			`integer delay;`
275			`integer count;`
276			`integer n;`
277
278			`begin`
279
280			`@(posedge clk);`
281			`#1;`
282			`cyc = 1;`
283
284			`for(n=0;n<count;n=n+1)`
285			`begin`
286			`repeat(delay)`
287			`begin`
288			`@(posedge clk);`
289			`#1;`
290			`end`
291			`adr = a + (n*4);`
292			`dout = wr_mem[n + wr_cnt];`
293			`stb = 1;`
294			`we=1;`
295			`sel = s;`
296			`if(n!=0) @(posedge clk);`
297			`while(~ack & ~err) @(posedge clk);`
298			`#2;`
299			`stb=0;`
300			`we=1'bx;`
301			`sel = 4'hx;`
302			`dout = 32'hxxxx_xxxx;`
303			`adr = 32'hxxxx_xxxx;`
304			`end`
305
306			`cyc=0;`
307
308			`adr = 32'hxxxx_xxxx;`
309			`//adr = 32'hffff_ffff;`
310
311			`wr_cnt = wr_cnt + count;`
312			`end`
313			`endtask`
314
315
316			`task wb_rmw;`
317			`input [31:0] a;`
318			`input [3:0] s;`
319			`input delay;`
320			`input rcount;`
321			`input wcount;`
322
323			`integer delay;`
324			`integer rcount;`
325			`integer wcount;`
326			`integer n;`
327
328			`begin`
329
330			`@(posedge clk);`
331			`#1;`
332			`cyc = 1;`
333			`we = 0;`
334			`sel = s;`
335			`repeat(delay) @(posedge clk);`
336
337			`for(n=0;n<rcount-1;n=n+1)`
338			`begin`
339			`adr = a + (n*4);`
340			`stb = 1;`
341			`while(~ack & ~err) @(posedge clk);`
342			`rd_mem[n + rd_cnt] = din;`
343			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
344			`#2;`
345			`stb=0;`
346			`we = 1'hx;`
347			`sel = 4'hx;`
348			`adr = 32'hxxxx_xxxx;`
349			`repeat(delay)`
350			`begin`
351			`@(posedge clk);`
352			`#1;`
353			`end`
354			`we = 0;`
355			`sel = s;`
356			`end`
357
358			`adr = a+(n*4);`
359			`stb = 1;`
360			`@(posedge clk);`
361			`while(~ack & ~err) @(posedge clk);`
362			`rd_mem[n + rd_cnt] = din;`
363			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
364			`#1;`
365			`stb=0;`
366			`we = 1'hx;`
367			`sel = 4'hx;`
368			`adr = 32'hxxxx_xxxx;`
369
370			`rd_cnt = rd_cnt + rcount;`
371
372			`//@(posedge clk);`
373
374
375			`for(n=0;n<wcount;n=n+1)`
376			`begin`
377			`repeat(delay)`
378			`begin`
379			`@(posedge clk);`
380			`#1;`
381			`end`
382			`adr = a + (n*4);`
383			`dout = wr_mem[n + wr_cnt];`
384			`stb = 1;`
385			`we=1;`
386			`sel = s;`
387			`// if(n!=0)`
388			`@(posedge clk);`
389			`while(~ack & ~err) @(posedge clk);`
390			`#2;`
391			`stb=0;`
392			`we=1'bx;`
393			`sel = 4'hx;`
394			`dout = 32'hxxxx_xxxx;`
395			`adr = 32'hxxxx_xxxx;`
396			`end`
397
398			`cyc=0;`
399
400			`adr = 32'hxxxx_xxxx;`
401			`//adr = 32'hffff_ffff;`
402
403			`wr_cnt = wr_cnt + wcount;`
404			`end`
405			`endtask`
406
407
408
409
410			`task wb_wmr;`
411			`input [31:0] a;`
412			`input [3:0] s;`
413			`input delay;`
414			`input rcount;`
415			`input wcount;`
416
417			`integer delay;`
418			`integer rcount;`
419			`integer wcount;`
420			`integer n;`
421
422			`begin`
423
424			`@(posedge clk);`
425			`#1;`
426			`cyc = 1;`
427			`we = 1'bx;`
428			`sel = 4'hx;`
429			`sel = s;`
430
431			`for(n=0;n<wcount;n=n+1)`
432			`begin`
433			`repeat(delay)`
434			`begin`
435			`@(posedge clk);`
436			`#1;`
437			`end`
438			`adr = a + (n*4);`
439			`dout = wr_mem[n + wr_cnt];`
440			`stb = 1;`
441			`we=1;`
442			`sel = s;`
443			`@(posedge clk);`
444			`while(~ack & ~err) @(posedge clk);`
445			`#2;`
446			`stb=0;`
447			`we=1'bx;`
448			`sel = 4'hx;`
449			`dout = 32'hxxxx_xxxx;`
450			`adr = 32'hxxxx_xxxx;`
451			`end`
452
453			`wr_cnt = wr_cnt + wcount;`
454			`stb=0;`
455			`repeat(delay) @(posedge clk);`
456			`#1;`
457
458			`sel = s;`
459			`we = 0;`
460			`for(n=0;n<rcount-1;n=n+1)`
461			`begin`
462			`adr = a + (n*4);`
463			`stb = 1;`
464			`while(~ack & ~err) @(posedge clk);`
465			`rd_mem[n + rd_cnt] = din;`
466			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
467			`#2;`
468			`stb=0;`
469			`we = 1'hx;`
470			`sel = 4'hx;`
471			`adr = 32'hxxxx_xxxx;`
472			`repeat(delay)`
473			`begin`
474			`@(posedge clk);`
475			`#1;`
476			`end`
477			`we = 0;`
478			`sel = s;`
479			`end`
480
481			`adr = a+(n*4);`
482			`stb = 1;`
483			`@(posedge clk);`
484			`while(~ack & ~err) @(posedge clk);`
485			`rd_mem[n + rd_cnt] = din;`
486			`rd_cnt = rd_cnt + rcount;`
487			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
488			`#1;`
489
490			`cyc = 0;`
491			`stb = 0;`
492			`we = 1'hx;`
493			`sel = 4'hx;`
494			`adr = 32'hxxxx_xxxx;`
495
496			`end`
497			`endtask`
498
499
500
501
502	5	rudi	`////////////////////////////////////////////////////////////////////`
503			`//`
504			`// Read 1 Word Task`
505			`//`
506
507			`task wb_rd1;`
508			`input [31:0] a;`
509			`input [3:0] s;`
510			`output [31:0] d;`
511
512			`begin`
513
514			`@(posedge clk);`
515			`#1;`
516			`adr = a;`
517			`cyc = 1;`
518			`stb = 1;`
519			`we = 0;`
520			`sel = s;`
521
522			`//@(posedge clk);`
523	9	rudi	`while(~ack & ~err) @(posedge clk);`
524	5	rudi	`d = din;`
525			`#1;`
526			`cyc=0;`
527			`stb=0;`
528			`//adr = 32'hxxxx_xxxx;`
529			`//adr = 0;`
530			`adr = 32'hffff_ffff;`
531			`dout = 32'hxxxx_xxxx;`
532			`we = 1'hx;`
533			`sel = 4'hx;`
534
535			`end`
536			`endtask`
537
538
539			`////////////////////////////////////////////////////////////////////`
540			`//`
541			`// Read 4 Words Task`
542			`//`
543
544
545			`task wb_rd4;`
546			`input [31:0] a;`
547			`input [3:0] s;`
548			`input delay;`
549			`output [31:0] d1;`
550			`output [31:0] d2;`
551			`output [31:0] d3;`
552			`output [31:0] d4;`
553
554			`integer delay;`
555			`begin`
556
557			`@(posedge clk);`
558			`#1;`
559			`cyc = 1;`
560			`we = 0;`
561			`sel = s;`
562			`repeat(delay) @(posedge clk);`
563
564			`adr = a;`
565			`stb = 1;`
566	9	rudi	`while(~ack & ~err) @(posedge clk);`
567	5	rudi	`d1 = din;`
568			`#2;`
569			`stb=0;`
570			`we = 1'hx;`
571			`sel = 4'hx;`
572			`repeat(delay)`
573			`begin`
574			`@(posedge clk);`
575			`#1;`
576			`end`
577			`we = 0;`
578			`sel = s;`
579
580			`adr = a+4;`
581			`stb = 1;`
582			`@(posedge clk);`
583	9	rudi	`while(~ack & ~err) @(posedge clk);`
584	5	rudi	`d2 = din;`
585			`#2;`
586			`stb=0;`
587			`we = 1'hx;`
588			`sel = 4'hx;`
589			`repeat(delay)`
590			`begin`
591			`@(posedge clk);`
592			`#1;`
593			`end`
594			`we = 0;`
595			`sel = s;`
596
597
598			`adr = a+8;`
599			`stb = 1;`
600			`@(posedge clk);`
601	9	rudi	`while(~ack & ~err) @(posedge clk);`
602	5	rudi	`d3 = din;`
603			`#2;`
604			`stb=0;`
605			`we = 1'hx;`
606			`sel = 4'hx;`
607			`repeat(delay)`
608			`begin`
609			`@(posedge clk);`
610			`#1;`
611			`end`
612			`we = 0;`
613			`sel = s;`
614
615			`adr = a+12;`
616			`stb = 1;`
617			`@(posedge clk);`
618	9	rudi	`while(~ack & ~err) @(posedge clk);`
619	5	rudi	`d4 = din;`
620			`#1;`
621			`stb=0;`
622			`cyc=0;`
623			`we = 1'hx;`
624			`sel = 4'hx;`
625			`adr = 32'hffff_ffff;`
626			`end`
627			`endtask`
628
629
630	9	rudi
631			`task wb_rd_mult;`
632			`input [31:0] a;`
633			`input [3:0] s;`
634			`input delay;`
635			`input count;`
636
637			`integer delay;`
638			`integer count;`
639			`integer n;`
640
641			`begin`
642
643			`@(posedge clk);`
644			`#1;`
645			`cyc = 1;`
646			`we = 0;`
647			`sel = s;`
648			`repeat(delay) @(posedge clk);`
649
650			`for(n=0;n<count-1;n=n+1)`
651			`begin`
652			`adr = a + (n*4);`
653			`stb = 1;`
654			`while(~ack & ~err) @(posedge clk);`
655			`rd_mem[n + rd_cnt] = din;`
656			`#2;`
657			`stb=0;`
658			`we = 1'hx;`
659			`sel = 4'hx;`
660			`adr = 32'hxxxx_xxxx;`
661			`repeat(delay)`
662			`begin`
663			`@(posedge clk);`
664			`#1;`
665			`end`
666			`we = 0;`
667			`sel = s;`
668			`end`
669
670			`adr = a+(n*4);`
671			`stb = 1;`
672			`@(posedge clk);`
673			`while(~ack & ~err) @(posedge clk);`
674			`rd_mem[n + rd_cnt] = din;`
675			`#1;`
676			`stb=0;`
677			`cyc=0;`
678			`we = 1'hx;`
679			`sel = 4'hx;`
680			`adr = 32'hffff_ffff;`
681			`adr = 32'hxxxx_xxxx;`
682
683			`rd_cnt = rd_cnt + count;`
684			`end`
685			`endtask`
686
687	5	rudi	`endmodule`