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[/] [wb_dma/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
//
//  $Date: 2001-07-29 08:57:02 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/03/19 13:11:34  rudi
//               Initial Release
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack)     @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
//@(posedge clk);
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack)     @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack)     @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask
 
 
endmodule

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[/] [wb_dma/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_mast_model.v,v 1.1 2001-07-29 08:57:02 rudi Exp $`
41			`//`
42			`// $Date: 2001-07-29 08:57:02 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`// Revision 1.1.1.1 2001/03/19 13:11:34 rudi`
51			`// Initial Release`
52			`//`
53			`//`
54			`//`
55
56			`include "wb_model_defines.v"
57
58			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
59
60			`input clk, rst;`
61			`output [31:0] adr;`
62			`input [31:0] din;`
63			`output [31:0] dout;`
64			`output cyc, stb;`
65			`output [3:0] sel;`
66			`output we;`
67			`input ack, err, rty;`
68
69			`////////////////////////////////////////////////////////////////////`
70			`//`
71			`// Local Wires`
72			`//`
73
74			`reg [31:0] adr;`
75			`reg [31:0] dout;`
76			`reg cyc, stb;`
77			`reg [3:0] sel;`
78			`reg we;`
79
80			`////////////////////////////////////////////////////////////////////`
81			`//`
82			`// Memory Logic`
83			`//`
84
85			`initial`
86			`begin`
87			`//adr = 32'hxxxx_xxxx;`
88			`//adr = 0;`
89			`adr = 32'hffff_ffff;`
90			`dout = 32'hxxxx_xxxx;`
91			`cyc = 0;`
92			`stb = 0;`
93			`sel = 4'hx;`
94			`we = 1'hx;`
95			`#1;`
96			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
97			`end`
98
99			`////////////////////////////////////////////////////////////////////`
100			`//`
101			`// Write 1 Word Task`
102			`//`
103
104			`task wb_wr1;`
105			`input [31:0] a;`
106			`input [3:0] s;`
107			`input [31:0] d;`
108
109			`begin`
110
111			`@(posedge clk);`
112			`#1;`
113			`adr = a;`
114			`dout = d;`
115			`cyc = 1;`
116			`stb = 1;`
117			`we=1;`
118			`sel = s;`
119
120			`@(posedge clk);`
121			`while(~ack) @(posedge clk);`
122			`#1;`
123			`cyc=0;`
124			`stb=0;`
125			`adr = 32'hxxxx_xxxx;`
126			`dout = 32'hxxxx_xxxx;`
127			`we = 1'hx;`
128			`sel = 4'hx;`
129
130			`//@(posedge clk);`
131			`end`
132			`endtask`
133
134
135			`////////////////////////////////////////////////////////////////////`
136			`//`
137			`// Write 4 Words Task`
138			`//`
139
140			`task wb_wr4;`
141			`input [31:0] a;`
142			`input [3:0] s;`
143			`input delay;`
144			`input [31:0] d1;`
145			`input [31:0] d2;`
146			`input [31:0] d3;`
147			`input [31:0] d4;`
148
149			`integer delay;`
150
151			`begin`
152
153			`@(posedge clk);`
154			`#1;`
155			`cyc = 1;`
156			`sel = s;`
157
158			`repeat(delay)`
159			`begin`
160			`@(posedge clk);`
161			`#1;`
162			`end`
163			`adr = a;`
164			`dout = d1;`
165			`stb = 1;`
166			`we=1;`
167			`while(~ack) @(posedge clk);`
168			`#2;`
169			`stb=0;`
170			`we=1'bx;`
171			`dout = 32'hxxxx_xxxx;`
172
173
174			`repeat(delay)`
175			`begin`
176			`@(posedge clk);`
177			`#1;`
178			`end`
179			`stb=1;`
180			`adr = a+4;`
181			`dout = d2;`
182			`we=1;`
183			`@(posedge clk);`
184			`while(~ack) @(posedge clk);`
185			`#2;`
186			`stb=0;`
187			`we=1'bx;`
188			`dout = 32'hxxxx_xxxx;`
189
190			`repeat(delay)`
191			`begin`
192			`@(posedge clk);`
193			`#1;`
194			`end`
195			`stb=1;`
196			`adr = a+8;`
197			`dout = d3;`
198			`we=1;`
199			`@(posedge clk);`
200			`while(~ack) @(posedge clk);`
201			`#2;`
202			`stb=0;`
203			`we=1'bx;`
204			`dout = 32'hxxxx_xxxx;`
205
206			`repeat(delay)`
207			`begin`
208			`@(posedge clk);`
209			`#1;`
210			`end`
211			`stb=1;`
212			`adr = a+12;`
213			`dout = d4;`
214			`we=1;`
215			`@(posedge clk);`
216			`while(~ack) @(posedge clk);`
217			`#1;`
218			`stb=0;`
219			`cyc=0;`
220
221			`adr = 32'hxxxx_xxxx;`
222			`dout = 32'hxxxx_xxxx;`
223			`we = 1'hx;`
224			`sel = 4'hx;`
225
226			`end`
227			`endtask`
228
229
230			`////////////////////////////////////////////////////////////////////`
231			`//`
232			`// Read 1 Word Task`
233			`//`
234
235			`task wb_rd1;`
236			`input [31:0] a;`
237			`input [3:0] s;`
238			`output [31:0] d;`
239
240			`begin`
241
242			`@(posedge clk);`
243			`#1;`
244			`adr = a;`
245			`cyc = 1;`
246			`stb = 1;`
247			`we = 0;`
248			`sel = s;`
249
250			`//@(posedge clk);`
251			`while(~ack) @(posedge clk);`
252			`d = din;`
253			`#1;`
254			`cyc=0;`
255			`stb=0;`
256			`//adr = 32'hxxxx_xxxx;`
257			`//adr = 0;`
258			`adr = 32'hffff_ffff;`
259			`dout = 32'hxxxx_xxxx;`
260			`we = 1'hx;`
261			`sel = 4'hx;`
262
263			`end`
264			`endtask`
265
266
267			`////////////////////////////////////////////////////////////////////`
268			`//`
269			`// Read 4 Words Task`
270			`//`
271
272
273			`task wb_rd4;`
274			`input [31:0] a;`
275			`input [3:0] s;`
276			`input delay;`
277			`output [31:0] d1;`
278			`output [31:0] d2;`
279			`output [31:0] d3;`
280			`output [31:0] d4;`
281
282			`integer delay;`
283			`begin`
284
285			`@(posedge clk);`
286			`#1;`
287			`cyc = 1;`
288			`we = 0;`
289			`sel = s;`
290			`repeat(delay) @(posedge clk);`
291
292			`adr = a;`
293			`stb = 1;`
294			`while(~ack) @(posedge clk);`
295			`d1 = din;`
296			`#2;`
297			`stb=0;`
298			`we = 1'hx;`
299			`sel = 4'hx;`
300			`repeat(delay)`
301			`begin`
302			`@(posedge clk);`
303			`#1;`
304			`end`
305			`we = 0;`
306			`sel = s;`
307
308			`adr = a+4;`
309			`stb = 1;`
310			`@(posedge clk);`
311			`while(~ack) @(posedge clk);`
312			`d2 = din;`
313			`#2;`
314			`stb=0;`
315			`we = 1'hx;`
316			`sel = 4'hx;`
317			`repeat(delay)`
318			`begin`
319			`@(posedge clk);`
320			`#1;`
321			`end`
322			`we = 0;`
323			`sel = s;`
324
325
326			`adr = a+8;`
327			`stb = 1;`
328			`@(posedge clk);`
329			`while(~ack) @(posedge clk);`
330			`d3 = din;`
331			`#2;`
332			`stb=0;`
333			`we = 1'hx;`
334			`sel = 4'hx;`
335			`repeat(delay)`
336			`begin`
337			`@(posedge clk);`
338			`#1;`
339			`end`
340			`we = 0;`
341			`sel = s;`
342
343			`adr = a+12;`
344			`stb = 1;`
345			`@(posedge clk);`
346			`while(~ack) @(posedge clk);`
347			`d4 = din;`
348			`#1;`
349			`stb=0;`
350			`cyc=0;`
351			`we = 1'hx;`
352			`sel = 4'hx;`
353			`adr = 32'hffff_ffff;`
354			`end`
355			`endtask`
356
357
358			`endmodule`