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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE DMA Priority Encoder                              ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_dma_ch_pri_enc.v,v 1.5 2002-02-01 01:54:44 rudi Exp $
//
//  $Date: 2002-02-01 01:54:44 $
//  $Revision: 1.5 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.4  2001/10/19 04:35:04  rudi
//
//               - Made the core parameterized
//
//               Revision 1.3  2001/08/15 05:40:30  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Added Section 3.10, describing DMA restart.
//
//               Revision 1.2  2001/08/07 08:00:43  rudi
//
//
//               Split up priority encoder modules to separate files
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.2  2001/06/05 10:22:36  rudi
//
//
//               - Added Support of up to 31 channels
//               - Added support for 2,4 and 8 priority levels
//               - Now can have up to 31 channels
//               - Added many configuration items
//               - Changed reset to async
//
//               Revision 1.1.1.1  2001/03/19 13:10:50  rudi
//               Initial Release
//
//
//
 
`include "wb_dma_defines.v"
 
// Priority Encoder
//
// Determines the channel with the highest priority, also takes
// the valid bit in consideration
 
module wb_dma_ch_pri_enc(clk, valid,
                pri0, pri1, pri2, pri3,
                pri4, pri5, pri6, pri7,
                pri8, pri9, pri10, pri11,
                pri12, pri13, pri14, pri15,
                pri16, pri17, pri18, pri19,
                pri20, pri21, pri22, pri23,
                pri24, pri25, pri26, pri27,
                pri28, pri29, pri30,
                pri_out);
 
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
 
// chXX_conf = { CBUF, ED, ARS, EN }
parameter       [1:0]    pri_sel = 2'd0;
parameter       [3:0]    ch0_conf = 4'h1;
parameter       [3:0]    ch1_conf = 4'h0;
parameter       [3:0]    ch2_conf = 4'h0;
parameter       [3:0]    ch3_conf = 4'h0;
parameter       [3:0]    ch4_conf = 4'h0;
parameter       [3:0]    ch5_conf = 4'h0;
parameter       [3:0]    ch6_conf = 4'h0;
parameter       [3:0]    ch7_conf = 4'h0;
parameter       [3:0]    ch8_conf = 4'h0;
parameter       [3:0]    ch9_conf = 4'h0;
parameter       [3:0]    ch10_conf = 4'h0;
parameter       [3:0]    ch11_conf = 4'h0;
parameter       [3:0]    ch12_conf = 4'h0;
parameter       [3:0]    ch13_conf = 4'h0;
parameter       [3:0]    ch14_conf = 4'h0;
parameter       [3:0]    ch15_conf = 4'h0;
parameter       [3:0]    ch16_conf = 4'h0;
parameter       [3:0]    ch17_conf = 4'h0;
parameter       [3:0]    ch18_conf = 4'h0;
parameter       [3:0]    ch19_conf = 4'h0;
parameter       [3:0]    ch20_conf = 4'h0;
parameter       [3:0]    ch21_conf = 4'h0;
parameter       [3:0]    ch22_conf = 4'h0;
parameter       [3:0]    ch23_conf = 4'h0;
parameter       [3:0]    ch24_conf = 4'h0;
parameter       [3:0]    ch25_conf = 4'h0;
parameter       [3:0]    ch26_conf = 4'h0;
parameter       [3:0]    ch27_conf = 4'h0;
parameter       [3:0]    ch28_conf = 4'h0;
parameter       [3:0]    ch29_conf = 4'h0;
parameter       [3:0]    ch30_conf = 4'h0;
 
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
 
input           clk;
input   [30:0]   valid;                          // Channel Valid bits
input   [2:0]    pri0, pri1, pri2, pri3;         // Channel Priorities
input   [2:0]    pri4, pri5, pri6, pri7;
input   [2:0]    pri8, pri9, pri10, pri11;
input   [2:0]    pri12, pri13, pri14, pri15;
input   [2:0]    pri16, pri17, pri18, pri19;
input   [2:0]    pri20, pri21, pri22, pri23;
input   [2:0]    pri24, pri25, pri26, pri27;
input   [2:0]    pri28, pri29, pri30;
output  [2:0]    pri_out;                        // Highest unserviced priority
 
wire    [7:0]    pri0_out, pri1_out, pri2_out, pri3_out;
wire    [7:0]    pri4_out, pri5_out, pri6_out, pri7_out;
wire    [7:0]    pri8_out, pri9_out, pri10_out, pri11_out;
wire    [7:0]    pri12_out, pri13_out, pri14_out, pri15_out;
wire    [7:0]    pri16_out, pri17_out, pri18_out, pri19_out;
wire    [7:0]    pri20_out, pri21_out, pri22_out, pri23_out;
wire    [7:0]    pri24_out, pri25_out, pri26_out, pri27_out;
wire    [7:0]    pri28_out, pri29_out, pri30_out;
 
wire    [7:0]    pri_out_tmp;
reg     [2:0]    pri_out;
reg     [2:0]    pri_out2;
reg     [2:0]    pri_out1;
reg     [2:0]    pri_out0;
 
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0(      // Use channel config 1 for channel 0 encoder
                .valid(         valid[0] ),
                .pri_in(        pri0            ),
                .pri_out(       pri0_out        )
                );
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1(
                .valid(         valid[1]        ),
                .pri_in(        pri1            ),
                .pri_out(       pri1_out        )
                );
wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2(
                .valid(         valid[2]        ),
                .pri_in(        pri2            ),
                .pri_out(       pri2_out        )
                );
wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3(
                .valid(         valid[3]        ),
                .pri_in(        pri3            ),
                .pri_out(       pri3_out        )
                );
wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4(
                .valid(         valid[4]        ),
                .pri_in(        pri4            ),
                .pri_out(       pri4_out        )
                );
wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5(
                .valid(         valid[5]        ),
                .pri_in(        pri5            ),
                .pri_out(       pri5_out        )
                );
wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6(
                .valid(         valid[6]        ),
                .pri_in(        pri6            ),
                .pri_out(       pri6_out        )
                );
wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7(
                .valid(         valid[7]        ),
                .pri_in(        pri7            ),
                .pri_out(       pri7_out        )
                );
wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8(
                .valid(         valid[8]        ),
                .pri_in(        pri8            ),
                .pri_out(       pri8_out        )
                );
wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9(
                .valid(         valid[9]        ),
                .pri_in(        pri9            ),
                .pri_out(       pri9_out        )
                );
wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10(
                .valid(         valid[10]       ),
                .pri_in(        pri10           ),
                .pri_out(       pri10_out       )
                );
wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11(
                .valid(         valid[11]       ),
                .pri_in(        pri11           ),
                .pri_out(       pri11_out       )
                );
wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12(
                .valid(         valid[12]       ),
                .pri_in(        pri12           ),
                .pri_out(       pri12_out       )
                );
wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13(
                .valid(         valid[13]       ),
                .pri_in(        pri13           ),
                .pri_out(       pri13_out       )
                );
wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14(
                .valid(         valid[14]       ),
                .pri_in(        pri14           ),
                .pri_out(       pri14_out       )
                );
wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15(
                .valid(         valid[15]       ),
                .pri_in(        pri15           ),
                .pri_out(       pri15_out       )
                );
wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16(
                .valid(         valid[16]       ),
                .pri_in(        pri16           ),
                .pri_out(       pri16_out       )
                );
wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17(
                .valid(         valid[17]       ),
                .pri_in(        pri17           ),
                .pri_out(       pri17_out       )
                );
wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18(
                .valid(         valid[18]       ),
                .pri_in(        pri18           ),
                .pri_out(       pri18_out       )
                );
wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19(
                .valid(         valid[19]       ),
                .pri_in(        pri19           ),
                .pri_out(       pri19_out       )
                );
wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20(
                .valid(         valid[20]       ),
                .pri_in(        pri20           ),
                .pri_out(       pri20_out       )
                );
wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21(
                .valid(         valid[21]       ),
                .pri_in(        pri21           ),
                .pri_out(       pri21_out       )
                );
wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22(
                .valid(         valid[22]       ),
                .pri_in(        pri22           ),
                .pri_out(       pri22_out       )
                );
wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23(
                .valid(         valid[23]       ),
                .pri_in(        pri23           ),
                .pri_out(       pri23_out       )
                );
wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24(
                .valid(         valid[24]       ),
                .pri_in(        pri24           ),
                .pri_out(       pri24_out       )
                );
wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25(
                .valid(         valid[25]       ),
                .pri_in(        pri25           ),
                .pri_out(       pri25_out       )
                );
wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26(
                .valid(         valid[26]       ),
                .pri_in(        pri26           ),
                .pri_out(       pri26_out       )
                );
wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27(
                .valid(         valid[27]       ),
                .pri_in(        pri27           ),
                .pri_out(       pri27_out       )
                );
wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28(
                .valid(         valid[28]       ),
                .pri_in(        pri28           ),
                .pri_out(       pri28_out       )
                );
wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29(
                .valid(         valid[29]       ),
                .pri_in(        pri29           ),
                .pri_out(       pri29_out       )
                );
wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30(
                .valid(         valid[30]       ),
                .pri_in(        pri30           ),
                .pri_out(       pri30_out       )
                );
 
assign pri_out_tmp =    pri0_out | pri1_out | pri2_out | pri3_out |
                        pri4_out | pri5_out | pri6_out | pri7_out |
                        pri8_out | pri9_out | pri10_out | pri11_out |
                        pri12_out | pri13_out | pri14_out | pri15_out |
                        pri16_out | pri17_out | pri18_out | pri19_out |
                        pri20_out | pri21_out | pri22_out | pri23_out |
                        pri24_out | pri25_out | pri26_out | pri27_out |
                        pri28_out | pri29_out | pri30_out;
 
// 8 Priority Levels
always @(posedge clk)
        if(pri_out_tmp[7])      pri_out2 <= #1 3'h7;
        else
        if(pri_out_tmp[6])      pri_out2 <= #1 3'h6;
        else
        if(pri_out_tmp[5])      pri_out2 <= #1 3'h5;
        else
        if(pri_out_tmp[4])      pri_out2 <= #1 3'h4;
        else
        if(pri_out_tmp[3])      pri_out2 <= #1 3'h3;
        else
        if(pri_out_tmp[2])      pri_out2 <= #1 3'h2;
        else
        if(pri_out_tmp[1])      pri_out2 <= #1 3'h1;
        else                    pri_out2 <= #1 3'h0;
 
// 4 Priority Levels
always @(posedge clk)
        if(pri_out_tmp[3])      pri_out1 <= #1 3'h3;
        else
        if(pri_out_tmp[2])      pri_out1 <= #1 3'h2;
        else
        if(pri_out_tmp[1])      pri_out1 <= #1 3'h1;
        else                    pri_out1 <= #1 3'h0;
 
// 2 Priority Levels
always @(posedge clk)
        if(pri_out_tmp[1])      pri_out0 <= #1 3'h1;
        else                    pri_out0 <= #1 3'h0;
 
// Select configured priority
always @(pri_sel or pri_out0 or pri_out1 or  pri_out2)
        case(pri_sel)           // synopsys parallel_case full_case
           2'd0: pri_out = pri_out0;
           2'd1: pri_out = pri_out1;
           2'd2: pri_out = pri_out2;
        endcase
 
endmodule

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE DMA Priority Encoder ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	15	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17	5	rudi	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	15	rudi	`// $Id: wb_dma_ch_pri_enc.v,v 1.5 2002-02-01 01:54:44 rudi Exp $`
42	5	rudi	`//`
43	15	rudi	`// $Date: 2002-02-01 01:54:44 $`
44			`// $Revision: 1.5 $`
45	5	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	15	rudi	`// Revision 1.4 2001/10/19 04:35:04 rudi`
52			`//`
53			`// - Made the core parameterized`
54			`//`
55	10	rudi	`// Revision 1.3 2001/08/15 05:40:30 rudi`
56			`//`
57			`// - Changed IO names to be more clear.`
58			`// - Uniquifyed define names to be core specific.`
59			`// - Added Section 3.10, describing DMA restart.`
60			`//`
61	8	rudi	`// Revision 1.2 2001/08/07 08:00:43 rudi`
62			`//`
63			`//`
64			`// Split up priority encoder modules to separate files`
65			`//`
66	6	rudi	`// Revision 1.1 2001/07/29 08:57:02 rudi`
67			`//`
68			`//`
69			`// 1) Changed Directory Structure`
70			`// 2) Added restart signal (REST)`
71			`//`
72	5	rudi	`// Revision 1.2 2001/06/05 10:22:36 rudi`
73			`//`
74			`//`
75			`// - Added Support of up to 31 channels`
76			`// - Added support for 2,4 and 8 priority levels`
77			`// - Now can have up to 31 channels`
78			`// - Added many configuration items`
79			`// - Changed reset to async`
80			`//`
81			`// Revision 1.1.1.1 2001/03/19 13:10:50 rudi`
82			`// Initial Release`
83			`//`
84			`//`
85			`//`
86
87			`include "wb_dma_defines.v"
88
89			`// Priority Encoder`
90			`//`
91			`// Determines the channel with the highest priority, also takes`
92			`// the valid bit in consideration`
93
94			`module wb_dma_ch_pri_enc(clk, valid,`
95			`pri0, pri1, pri2, pri3,`
96			`pri4, pri5, pri6, pri7,`
97			`pri8, pri9, pri10, pri11,`
98			`pri12, pri13, pri14, pri15,`
99			`pri16, pri17, pri18, pri19,`
100			`pri20, pri21, pri22, pri23,`
101			`pri24, pri25, pri26, pri27,`
102			`pri28, pri29, pri30,`
103			`pri_out);`
104
105	10	rudi	`////////////////////////////////////////////////////////////////////`
106			`//`
107			`// Module Parameters`
108			`//`
109
110			`// chXX_conf = { CBUF, ED, ARS, EN }`
111			`parameter [1:0] pri_sel = 2'd0;`
112			`parameter [3:0] ch0_conf = 4'h1;`
113			`parameter [3:0] ch1_conf = 4'h0;`
114			`parameter [3:0] ch2_conf = 4'h0;`
115			`parameter [3:0] ch3_conf = 4'h0;`
116			`parameter [3:0] ch4_conf = 4'h0;`
117			`parameter [3:0] ch5_conf = 4'h0;`
118			`parameter [3:0] ch6_conf = 4'h0;`
119			`parameter [3:0] ch7_conf = 4'h0;`
120			`parameter [3:0] ch8_conf = 4'h0;`
121			`parameter [3:0] ch9_conf = 4'h0;`
122			`parameter [3:0] ch10_conf = 4'h0;`
123			`parameter [3:0] ch11_conf = 4'h0;`
124			`parameter [3:0] ch12_conf = 4'h0;`
125			`parameter [3:0] ch13_conf = 4'h0;`
126			`parameter [3:0] ch14_conf = 4'h0;`
127			`parameter [3:0] ch15_conf = 4'h0;`
128			`parameter [3:0] ch16_conf = 4'h0;`
129			`parameter [3:0] ch17_conf = 4'h0;`
130			`parameter [3:0] ch18_conf = 4'h0;`
131			`parameter [3:0] ch19_conf = 4'h0;`
132			`parameter [3:0] ch20_conf = 4'h0;`
133			`parameter [3:0] ch21_conf = 4'h0;`
134			`parameter [3:0] ch22_conf = 4'h0;`
135			`parameter [3:0] ch23_conf = 4'h0;`
136			`parameter [3:0] ch24_conf = 4'h0;`
137			`parameter [3:0] ch25_conf = 4'h0;`
138			`parameter [3:0] ch26_conf = 4'h0;`
139			`parameter [3:0] ch27_conf = 4'h0;`
140			`parameter [3:0] ch28_conf = 4'h0;`
141			`parameter [3:0] ch29_conf = 4'h0;`
142			`parameter [3:0] ch30_conf = 4'h0;`
143
144			`////////////////////////////////////////////////////////////////////`
145			`//`
146			`// Module IOs`
147			`//`
148
149	5	rudi	`input clk;`
150			`input [30:0] valid; // Channel Valid bits`
151			`input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities`
152			`input [2:0] pri4, pri5, pri6, pri7;`
153			`input [2:0] pri8, pri9, pri10, pri11;`
154			`input [2:0] pri12, pri13, pri14, pri15;`
155			`input [2:0] pri16, pri17, pri18, pri19;`
156			`input [2:0] pri20, pri21, pri22, pri23;`
157			`input [2:0] pri24, pri25, pri26, pri27;`
158			`input [2:0] pri28, pri29, pri30;`
159			`output [2:0] pri_out; // Highest unserviced priority`
160
161			`wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out;`
162			`wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out;`
163			`wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out;`
164			`wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out;`
165			`wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out;`
166			`wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out;`
167			`wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out;`
168			`wire [7:0] pri28_out, pri29_out, pri30_out;`
169
170			`wire [7:0] pri_out_tmp;`
171			`reg [2:0] pri_out;`
172	10	rudi	`reg [2:0] pri_out2;`
173			`reg [2:0] pri_out1;`
174			`reg [2:0] pri_out0;`
175	5	rudi
176	10	rudi	`wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder`
177	5	rudi	`.valid( valid[0] ),`
178			`.pri_in( pri0 ),`
179			`.pri_out( pri0_out )`
180			`);`
181	10	rudi	`wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1(`
182	5	rudi	`.valid( valid[1] ),`
183			`.pri_in( pri1 ),`
184			`.pri_out( pri1_out )`
185			`);`
186	10	rudi	`wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2(`
187	5	rudi	`.valid( valid[2] ),`
188			`.pri_in( pri2 ),`
189			`.pri_out( pri2_out )`
190			`);`
191	10	rudi	`wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3(`
192	5	rudi	`.valid( valid[3] ),`
193			`.pri_in( pri3 ),`
194			`.pri_out( pri3_out )`
195			`);`
196	10	rudi	`wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4(`
197	5	rudi	`.valid( valid[4] ),`
198			`.pri_in( pri4 ),`
199			`.pri_out( pri4_out )`
200			`);`
201	10	rudi	`wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5(`
202	5	rudi	`.valid( valid[5] ),`
203			`.pri_in( pri5 ),`
204			`.pri_out( pri5_out )`
205			`);`
206	10	rudi	`wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6(`
207	5	rudi	`.valid( valid[6] ),`
208			`.pri_in( pri6 ),`
209			`.pri_out( pri6_out )`
210			`);`
211	10	rudi	`wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7(`
212	5	rudi	`.valid( valid[7] ),`
213			`.pri_in( pri7 ),`
214			`.pri_out( pri7_out )`
215			`);`
216	10	rudi	`wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8(`
217	5	rudi	`.valid( valid[8] ),`
218			`.pri_in( pri8 ),`
219			`.pri_out( pri8_out )`
220			`);`
221	10	rudi	`wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9(`
222	5	rudi	`.valid( valid[9] ),`
223			`.pri_in( pri9 ),`
224			`.pri_out( pri9_out )`
225			`);`
226	10	rudi	`wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10(`
227	5	rudi	`.valid( valid[10] ),`
228			`.pri_in( pri10 ),`
229			`.pri_out( pri10_out )`
230			`);`
231	10	rudi	`wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11(`
232	5	rudi	`.valid( valid[11] ),`
233			`.pri_in( pri11 ),`
234			`.pri_out( pri11_out )`
235			`);`
236	10	rudi	`wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12(`
237	5	rudi	`.valid( valid[12] ),`
238			`.pri_in( pri12 ),`
239			`.pri_out( pri12_out )`
240			`);`
241	10	rudi	`wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13(`
242	5	rudi	`.valid( valid[13] ),`
243			`.pri_in( pri13 ),`
244			`.pri_out( pri13_out )`
245			`);`
246	10	rudi	`wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14(`
247	5	rudi	`.valid( valid[14] ),`
248			`.pri_in( pri14 ),`
249			`.pri_out( pri14_out )`
250			`);`
251	10	rudi	`wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15(`
252	5	rudi	`.valid( valid[15] ),`
253			`.pri_in( pri15 ),`
254			`.pri_out( pri15_out )`
255			`);`
256	10	rudi	`wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16(`
257	5	rudi	`.valid( valid[16] ),`
258			`.pri_in( pri16 ),`
259			`.pri_out( pri16_out )`
260			`);`
261	10	rudi	`wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17(`
262	5	rudi	`.valid( valid[17] ),`
263			`.pri_in( pri17 ),`
264			`.pri_out( pri17_out )`
265			`);`
266	10	rudi	`wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18(`
267	5	rudi	`.valid( valid[18] ),`
268			`.pri_in( pri18 ),`
269			`.pri_out( pri18_out )`
270			`);`
271	10	rudi	`wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19(`
272	5	rudi	`.valid( valid[19] ),`
273			`.pri_in( pri19 ),`
274			`.pri_out( pri19_out )`
275			`);`
276	10	rudi	`wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20(`
277	5	rudi	`.valid( valid[20] ),`
278			`.pri_in( pri20 ),`
279			`.pri_out( pri20_out )`
280			`);`
281	10	rudi	`wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21(`
282	5	rudi	`.valid( valid[21] ),`
283			`.pri_in( pri21 ),`
284			`.pri_out( pri21_out )`
285			`);`
286	10	rudi	`wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22(`
287	5	rudi	`.valid( valid[22] ),`
288			`.pri_in( pri22 ),`
289			`.pri_out( pri22_out )`
290			`);`
291	10	rudi	`wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23(`
292	5	rudi	`.valid( valid[23] ),`
293			`.pri_in( pri23 ),`
294			`.pri_out( pri23_out )`
295			`);`
296	10	rudi	`wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24(`
297	5	rudi	`.valid( valid[24] ),`
298			`.pri_in( pri24 ),`
299			`.pri_out( pri24_out )`
300			`);`
301	10	rudi	`wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25(`
302	5	rudi	`.valid( valid[25] ),`
303			`.pri_in( pri25 ),`
304			`.pri_out( pri25_out )`
305			`);`
306	10	rudi	`wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26(`
307	5	rudi	`.valid( valid[26] ),`
308			`.pri_in( pri26 ),`
309			`.pri_out( pri26_out )`
310			`);`
311	10	rudi	`wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27(`
312	5	rudi	`.valid( valid[27] ),`
313			`.pri_in( pri27 ),`
314			`.pri_out( pri27_out )`
315			`);`
316	10	rudi	`wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28(`
317	5	rudi	`.valid( valid[28] ),`
318			`.pri_in( pri28 ),`
319			`.pri_out( pri28_out )`
320			`);`
321	10	rudi	`wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29(`
322	5	rudi	`.valid( valid[29] ),`
323			`.pri_in( pri29 ),`
324			`.pri_out( pri29_out )`
325			`);`
326	10	rudi	`wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30(`
327	5	rudi	`.valid( valid[30] ),`
328			`.pri_in( pri30 ),`
329			`.pri_out( pri30_out )`
330			`);`
331
332			`assign pri_out_tmp = pri0_out \| pri1_out \| pri2_out \| pri3_out \|`
333			`pri4_out \| pri5_out \| pri6_out \| pri7_out \|`
334			`pri8_out \| pri9_out \| pri10_out \| pri11_out \|`
335			`pri12_out \| pri13_out \| pri14_out \| pri15_out \|`
336			`pri16_out \| pri17_out \| pri18_out \| pri19_out \|`
337			`pri20_out \| pri21_out \| pri22_out \| pri23_out \|`
338			`pri24_out \| pri25_out \| pri26_out \| pri27_out \|`
339			`pri28_out \| pri29_out \| pri30_out;`
340
341	10	rudi	`// 8 Priority Levels`
342	5	rudi	`always @(posedge clk)`
343	10	rudi	`if(pri_out_tmp[7]) pri_out2 <= #1 3'h7;`
344	5	rudi	`else`
345	10	rudi	`if(pri_out_tmp[6]) pri_out2 <= #1 3'h6;`
346	5	rudi	`else`
347	10	rudi	`if(pri_out_tmp[5]) pri_out2 <= #1 3'h5;`
348	5	rudi	`else`
349	10	rudi	`if(pri_out_tmp[4]) pri_out2 <= #1 3'h4;`
350	5	rudi	`else`
351	10	rudi	`if(pri_out_tmp[3]) pri_out2 <= #1 3'h3;`
352	5	rudi	`else`
353	10	rudi	`if(pri_out_tmp[2]) pri_out2 <= #1 3'h2;`
354	5	rudi	`else`
355	10	rudi	`if(pri_out_tmp[1]) pri_out2 <= #1 3'h1;`
356			`else pri_out2 <= #1 3'h0;`
357
358			`// 4 Priority Levels`
359			`always @(posedge clk)`
360			`if(pri_out_tmp[3]) pri_out1 <= #1 3'h3;`
361	5	rudi	`else`
362	10	rudi	`if(pri_out_tmp[2]) pri_out1 <= #1 3'h2;`
363	5	rudi	`else`
364	10	rudi	`if(pri_out_tmp[1]) pri_out1 <= #1 3'h1;`
365			`else pri_out1 <= #1 3'h0;`
366	5	rudi
367	10	rudi	`// 2 Priority Levels`
368			`always @(posedge clk)`
369			`if(pri_out_tmp[1]) pri_out0 <= #1 3'h1;`
370			`else pri_out0 <= #1 3'h0;`
371
372			`// Select configured priority`
373			`always @(pri_sel or pri_out0 or pri_out1 or pri_out2)`
374			`case(pri_sel) // synopsys parallel_case full_case`
375			`2'd0: pri_out = pri_out0;`
376			`2'd1: pri_out = pri_out1;`
377			`2'd2: pri_out = pri_out2;`
378			`endcase`
379
380	5	rudi	`endmodule`

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