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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_ch_pri_enc.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE DMA Priority Encoder                              ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_dma_ch_pri_enc.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
//
//  $Date: 2001-07-29 08:57:02 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/06/05 10:22:36  rudi
//
//
//               - Added Support of up to 31 channels
//               - Added support for 2,4 and 8 priority levels
//               - Now can have up to 31 channels
//               - Added many configuration items
//               - Changed reset to async
//
//               Revision 1.1.1.1  2001/03/19 13:10:50  rudi
//               Initial Release
//
//
//
 
`include "wb_dma_defines.v"
 
// Priority Encoder
//
// Determines the channel with the highest priority, also takes
// the valid bit in consideration
 
module wb_dma_pri_enc_sub(valid, pri_in, pri_out);
input           valid;
input   [2:0]    pri_in;
output  [7:0]    pri_out;
 
reg     [7:0]    pri_out;
 
`ifdef PRI_8
always @(valid or pri_in)
        if(!valid)              pri_out = 8'b0000_0001;
        else
        if(pri_in==3'h0)        pri_out = 8'b0000_0001;
        else
        if(pri_in==3'h1)        pri_out = 8'b0000_0010;
        else
        if(pri_in==3'h2)        pri_out = 8'b0000_0100;
        else
        if(pri_in==3'h3)        pri_out = 8'b0000_1000;
        else
        if(pri_in==3'h4)        pri_out = 8'b0001_0000;
        else
        if(pri_in==3'h5)        pri_out = 8'b0010_0000;
        else
        if(pri_in==3'h6)        pri_out = 8'b0100_0000;
        else                    pri_out = 8'b1000_0000;
`else
`ifdef PRI_4
always @(valid or pri_in)
        if(!valid)              pri_out = 8'b0000_0001;
        else
        if(pri_in==3'h0)        pri_out = 8'b0000_0001;
        else
        if(pri_in==3'h1)        pri_out = 8'b0000_0010;
        else
        if(pri_in==3'h2)        pri_out = 8'b0000_0100;
        else                    pri_out = 8'b0000_1000;
`else
always @(valid or pri_in)
        if(!valid)              pri_out = 8'b0000_0001;
        else
        if(pri_in==3'h0)        pri_out = 8'b0000_0001;
        else                    pri_out = 8'b0000_0010;
`endif
`endif
 
endmodule
 
 
module wb_dma_ch_pri_enc(clk, valid,
                pri0, pri1, pri2, pri3,
                pri4, pri5, pri6, pri7,
                pri8, pri9, pri10, pri11,
                pri12, pri13, pri14, pri15,
                pri16, pri17, pri18, pri19,
                pri20, pri21, pri22, pri23,
                pri24, pri25, pri26, pri27,
                pri28, pri29, pri30,
                pri_out);
 
input           clk;
input   [30:0]   valid;                          // Channel Valid bits
input   [2:0]    pri0, pri1, pri2, pri3;         // Channel Priorities
input   [2:0]    pri4, pri5, pri6, pri7;
input   [2:0]    pri8, pri9, pri10, pri11;
input   [2:0]    pri12, pri13, pri14, pri15;
input   [2:0]    pri16, pri17, pri18, pri19;
input   [2:0]    pri20, pri21, pri22, pri23;
input   [2:0]    pri24, pri25, pri26, pri27;
input   [2:0]    pri28, pri29, pri30;
output  [2:0]    pri_out;                        // Highest unserviced priority
 
wire    [7:0]    pri0_out, pri1_out, pri2_out, pri3_out;
wire    [7:0]    pri4_out, pri5_out, pri6_out, pri7_out;
wire    [7:0]    pri8_out, pri9_out, pri10_out, pri11_out;
wire    [7:0]    pri12_out, pri13_out, pri14_out, pri15_out;
wire    [7:0]    pri16_out, pri17_out, pri18_out, pri19_out;
wire    [7:0]    pri20_out, pri21_out, pri22_out, pri23_out;
wire    [7:0]    pri24_out, pri25_out, pri26_out, pri27_out;
wire    [7:0]    pri28_out, pri29_out, pri30_out;
 
wire    [7:0]    pri_out_tmp;
reg     [2:0]    pri_out;
 
`ifdef HAVE_CH1
wb_dma_pri_enc_sub u0(
                .valid(         valid[0] ),
                .pri_in(        pri0            ),
                .pri_out(       pri0_out        )
                );
 
wb_dma_pri_enc_sub u1(
                .valid(         valid[1]        ),
                .pri_in(        pri1            ),
                .pri_out(       pri1_out        )
                );
`else
assign pri0_out = 0;
assign pri1_out = 0;
`endif
 
`ifdef HAVE_CH2
wb_dma_pri_enc_sub u2(
                .valid(         valid[2]        ),
                .pri_in(        pri2            ),
                .pri_out(       pri2_out        )
                );
`else
assign pri2_out = 0;
`endif
 
`ifdef HAVE_CH3
wb_dma_pri_enc_sub u3(
                .valid(         valid[3]        ),
                .pri_in(        pri3            ),
                .pri_out(       pri3_out        )
                );
`else
assign pri3_out = 0;
`endif
 
`ifdef HAVE_CH4
wb_dma_pri_enc_sub u4(
                .valid(         valid[4]        ),
                .pri_in(        pri4            ),
                .pri_out(       pri4_out        )
                );
`else
assign pri4_out = 0;
`endif
 
`ifdef HAVE_CH5
wb_dma_pri_enc_sub u5(
                .valid(         valid[5]        ),
                .pri_in(        pri5            ),
                .pri_out(       pri5_out        )
                );
`else
assign pri5_out = 0;
`endif
 
`ifdef HAVE_CH6
wb_dma_pri_enc_sub u6(
                .valid(         valid[6]        ),
                .pri_in(        pri6            ),
                .pri_out(       pri6_out        )
                );
`else
assign pri6_out = 0;
`endif
 
`ifdef HAVE_CH7
wb_dma_pri_enc_sub u7(
                .valid(         valid[7]        ),
                .pri_in(        pri7            ),
                .pri_out(       pri7_out        )
                );
`else
assign pri7_out = 0;
`endif
 
`ifdef HAVE_CH8
wb_dma_pri_enc_sub u8(
                .valid(         valid[8]        ),
                .pri_in(        pri8            ),
                .pri_out(       pri8_out        )
                );
`else
assign pri8_out = 0;
`endif
 
`ifdef HAVE_CH9
wb_dma_pri_enc_sub u9(
                .valid(         valid[9]        ),
                .pri_in(        pri9            ),
                .pri_out(       pri9_out        )
                );
`else
assign pri9_out = 0;
`endif
 
`ifdef HAVE_CH10
wb_dma_pri_enc_sub u10(
                .valid(         valid[10]       ),
                .pri_in(        pri10           ),
                .pri_out(       pri10_out       )
                );
`else
assign pri10_out = 0;
`endif
 
`ifdef HAVE_CH11
wb_dma_pri_enc_sub u11(
                .valid(         valid[11]       ),
                .pri_in(        pri11           ),
                .pri_out(       pri11_out       )
                );
`else
assign pri11_out = 0;
`endif
 
`ifdef HAVE_CH12
wb_dma_pri_enc_sub u12(
                .valid(         valid[12]       ),
                .pri_in(        pri12           ),
                .pri_out(       pri12_out       )
                );
`else
assign pri12_out = 0;
`endif
 
`ifdef HAVE_CH13
wb_dma_pri_enc_sub u13(
                .valid(         valid[13]       ),
                .pri_in(        pri13           ),
                .pri_out(       pri13_out       )
                );
`else
assign pri13_out = 0;
`endif
 
`ifdef HAVE_CH14
wb_dma_pri_enc_sub u14(
                .valid(         valid[14]       ),
                .pri_in(        pri14           ),
                .pri_out(       pri14_out       )
                );
`else
assign pri14_out = 0;
`endif
 
`ifdef HAVE_CH15
wb_dma_pri_enc_sub u15(
                .valid(         valid[15]       ),
                .pri_in(        pri15           ),
                .pri_out(       pri15_out       )
                );
`else
assign pri15_out = 0;
`endif
 
`ifdef HAVE_CH16
wb_dma_pri_enc_sub u16(
                .valid(         valid[16]       ),
                .pri_in(        pri16           ),
                .pri_out(       pri16_out       )
                );
`else
assign pri16_out = 0;
`endif
 
`ifdef HAVE_CH17
wb_dma_pri_enc_sub u17(
                .valid(         valid[17]       ),
                .pri_in(        pri17           ),
                .pri_out(       pri17_out       )
                );
`else
assign pri17_out = 0;
`endif
 
`ifdef HAVE_CH18
wb_dma_pri_enc_sub u18(
                .valid(         valid[18]       ),
                .pri_in(        pri18           ),
                .pri_out(       pri18_out       )
                );
`else
assign pri18_out = 0;
`endif
 
`ifdef HAVE_CH19
wb_dma_pri_enc_sub u19(
                .valid(         valid[19]       ),
                .pri_in(        pri19           ),
                .pri_out(       pri19_out       )
                );
`else
assign pri19_out = 0;
`endif
 
`ifdef HAVE_CH20
wb_dma_pri_enc_sub u20(
                .valid(         valid[20]       ),
                .pri_in(        pri20           ),
                .pri_out(       pri20_out       )
                );
`else
assign pri20_out = 0;
`endif
 
`ifdef HAVE_CH21
wb_dma_pri_enc_sub u21(
                .valid(         valid[21]       ),
                .pri_in(        pri21           ),
                .pri_out(       pri21_out       )
                );
`else
assign pri21_out = 0;
`endif
 
`ifdef HAVE_CH22
wb_dma_pri_enc_sub u22(
                .valid(         valid[22]       ),
                .pri_in(        pri22           ),
                .pri_out(       pri22_out       )
                );
`else
assign pri22_out = 0;
`endif
 
`ifdef HAVE_CH23
wb_dma_pri_enc_sub u23(
                .valid(         valid[23]       ),
                .pri_in(        pri23           ),
                .pri_out(       pri23_out       )
                );
`else
assign pri23_out = 0;
`endif
 
`ifdef HAVE_CH24
wb_dma_pri_enc_sub u24(
                .valid(         valid[24]       ),
                .pri_in(        pri24           ),
                .pri_out(       pri24_out       )
                );
`else
assign pri24_out = 0;
`endif
 
`ifdef HAVE_CH25
wb_dma_pri_enc_sub u25(
                .valid(         valid[25]       ),
                .pri_in(        pri25           ),
                .pri_out(       pri25_out       )
                );
`else
assign pri25_out = 0;
`endif
 
`ifdef HAVE_CH26
wb_dma_pri_enc_sub u26(
                .valid(         valid[26]       ),
                .pri_in(        pri26           ),
                .pri_out(       pri26_out       )
                );
`else
assign pri26_out = 0;
`endif
 
`ifdef HAVE_CH27
wb_dma_pri_enc_sub u27(
                .valid(         valid[27]       ),
                .pri_in(        pri27           ),
                .pri_out(       pri27_out       )
                );
`else
assign pri27_out = 0;
`endif
 
`ifdef HAVE_CH28
wb_dma_pri_enc_sub u28(
                .valid(         valid[28]       ),
                .pri_in(        pri28           ),
                .pri_out(       pri28_out       )
                );
`else
assign pri28_out = 0;
`endif
 
`ifdef HAVE_CH29
wb_dma_pri_enc_sub u29(
                .valid(         valid[29]       ),
                .pri_in(        pri29           ),
                .pri_out(       pri29_out       )
                );
`else
assign pri29_out = 0;
`endif
 
`ifdef HAVE_CH30
wb_dma_pri_enc_sub u30(
                .valid(         valid[30]       ),
                .pri_in(        pri30           ),
                .pri_out(       pri30_out       )
                );
`else
assign pri30_out = 0;
`endif
 
assign pri_out_tmp =    pri0_out | pri1_out | pri2_out | pri3_out |
                        pri4_out | pri5_out | pri6_out | pri7_out |
                        pri8_out | pri9_out | pri10_out | pri11_out |
                        pri12_out | pri13_out | pri14_out | pri15_out |
                        pri16_out | pri17_out | pri18_out | pri19_out |
                        pri20_out | pri21_out | pri22_out | pri23_out |
                        pri24_out | pri25_out | pri26_out | pri27_out |
                        pri28_out | pri29_out | pri30_out;
 
always @(posedge clk)
`ifdef PRI_8
        if(pri_out_tmp[7])      pri_out <= #1 3'h7;
        else
        if(pri_out_tmp[6])      pri_out <= #1 3'h6;
        else
        if(pri_out_tmp[5])      pri_out <= #1 3'h5;
        else
        if(pri_out_tmp[4])      pri_out <= #1 3'h4;
        else
        if(pri_out_tmp[3])      pri_out <= #1 3'h3;
        else
        if(pri_out_tmp[2])      pri_out <= #1 3'h2;
        else
`endif
`ifdef PRI_4
        if(pri_out_tmp[3])      pri_out <= #1 3'h3;
        else
        if(pri_out_tmp[2])      pri_out <= #1 3'h2;
        else
`endif
        if(pri_out_tmp[1])      pri_out <= #1 3'h1;
        else                    pri_out <= #1 3'h0;
 
endmodule

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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_ch_pri_enc.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE DMA Priority Encoder ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_dma_ch_pri_enc.v,v 1.1 2001-07-29 08:57:02 rudi Exp $`
41			`//`
42			`// $Date: 2001-07-29 08:57:02 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`// Revision 1.2 2001/06/05 10:22:36 rudi`
51			`//`
52			`//`
53			`// - Added Support of up to 31 channels`
54			`// - Added support for 2,4 and 8 priority levels`
55			`// - Now can have up to 31 channels`
56			`// - Added many configuration items`
57			`// - Changed reset to async`
58			`//`
59			`// Revision 1.1.1.1 2001/03/19 13:10:50 rudi`
60			`// Initial Release`
61			`//`
62			`//`
63			`//`
64
65			`include "wb_dma_defines.v"
66
67			`// Priority Encoder`
68			`//`
69			`// Determines the channel with the highest priority, also takes`
70			`// the valid bit in consideration`
71
72			`module wb_dma_pri_enc_sub(valid, pri_in, pri_out);`
73			`input valid;`
74			`input [2:0] pri_in;`
75			`output [7:0] pri_out;`
76
77			`reg [7:0] pri_out;`
78
79			`ifdef PRI_8
80			`always @(valid or pri_in)`
81			`if(!valid) pri_out = 8'b0000_0001;`
82			`else`
83			`if(pri_in==3'h0) pri_out = 8'b0000_0001;`
84			`else`
85			`if(pri_in==3'h1) pri_out = 8'b0000_0010;`
86			`else`
87			`if(pri_in==3'h2) pri_out = 8'b0000_0100;`
88			`else`
89			`if(pri_in==3'h3) pri_out = 8'b0000_1000;`
90			`else`
91			`if(pri_in==3'h4) pri_out = 8'b0001_0000;`
92			`else`
93			`if(pri_in==3'h5) pri_out = 8'b0010_0000;`
94			`else`
95			`if(pri_in==3'h6) pri_out = 8'b0100_0000;`
96			`else pri_out = 8'b1000_0000;`
97			`else
98			`ifdef PRI_4
99			`always @(valid or pri_in)`
100			`if(!valid) pri_out = 8'b0000_0001;`
101			`else`
102			`if(pri_in==3'h0) pri_out = 8'b0000_0001;`
103			`else`
104			`if(pri_in==3'h1) pri_out = 8'b0000_0010;`
105			`else`
106			`if(pri_in==3'h2) pri_out = 8'b0000_0100;`
107			`else pri_out = 8'b0000_1000;`
108			`else
109			`always @(valid or pri_in)`
110			`if(!valid) pri_out = 8'b0000_0001;`
111			`else`
112			`if(pri_in==3'h0) pri_out = 8'b0000_0001;`
113			`else pri_out = 8'b0000_0010;`
114			`endif
115			`endif
116
117			`endmodule`
118
119
120			`module wb_dma_ch_pri_enc(clk, valid,`
121			`pri0, pri1, pri2, pri3,`
122			`pri4, pri5, pri6, pri7,`
123			`pri8, pri9, pri10, pri11,`
124			`pri12, pri13, pri14, pri15,`
125			`pri16, pri17, pri18, pri19,`
126			`pri20, pri21, pri22, pri23,`
127			`pri24, pri25, pri26, pri27,`
128			`pri28, pri29, pri30,`
129			`pri_out);`
130
131			`input clk;`
132			`input [30:0] valid; // Channel Valid bits`
133			`input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities`
134			`input [2:0] pri4, pri5, pri6, pri7;`
135			`input [2:0] pri8, pri9, pri10, pri11;`
136			`input [2:0] pri12, pri13, pri14, pri15;`
137			`input [2:0] pri16, pri17, pri18, pri19;`
138			`input [2:0] pri20, pri21, pri22, pri23;`
139			`input [2:0] pri24, pri25, pri26, pri27;`
140			`input [2:0] pri28, pri29, pri30;`
141			`output [2:0] pri_out; // Highest unserviced priority`
142
143			`wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out;`
144			`wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out;`
145			`wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out;`
146			`wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out;`
147			`wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out;`
148			`wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out;`
149			`wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out;`
150			`wire [7:0] pri28_out, pri29_out, pri30_out;`
151
152			`wire [7:0] pri_out_tmp;`
153			`reg [2:0] pri_out;`
154
155			`ifdef HAVE_CH1
156			`wb_dma_pri_enc_sub u0(`
157			`.valid( valid[0] ),`
158			`.pri_in( pri0 ),`
159			`.pri_out( pri0_out )`
160			`);`
161
162			`wb_dma_pri_enc_sub u1(`
163			`.valid( valid[1] ),`
164			`.pri_in( pri1 ),`
165			`.pri_out( pri1_out )`
166			`);`
167			`else
168			`assign pri0_out = 0;`
169			`assign pri1_out = 0;`
170			`endif
171
172			`ifdef HAVE_CH2
173			`wb_dma_pri_enc_sub u2(`
174			`.valid( valid[2] ),`
175			`.pri_in( pri2 ),`
176			`.pri_out( pri2_out )`
177			`);`
178			`else
179			`assign pri2_out = 0;`
180			`endif
181
182			`ifdef HAVE_CH3
183			`wb_dma_pri_enc_sub u3(`
184			`.valid( valid[3] ),`
185			`.pri_in( pri3 ),`
186			`.pri_out( pri3_out )`
187			`);`
188			`else
189			`assign pri3_out = 0;`
190			`endif
191
192			`ifdef HAVE_CH4
193			`wb_dma_pri_enc_sub u4(`
194			`.valid( valid[4] ),`
195			`.pri_in( pri4 ),`
196			`.pri_out( pri4_out )`
197			`);`
198			`else
199			`assign pri4_out = 0;`
200			`endif
201
202			`ifdef HAVE_CH5
203			`wb_dma_pri_enc_sub u5(`
204			`.valid( valid[5] ),`
205			`.pri_in( pri5 ),`
206			`.pri_out( pri5_out )`
207			`);`
208			`else
209			`assign pri5_out = 0;`
210			`endif
211
212			`ifdef HAVE_CH6
213			`wb_dma_pri_enc_sub u6(`
214			`.valid( valid[6] ),`
215			`.pri_in( pri6 ),`
216			`.pri_out( pri6_out )`
217			`);`
218			`else
219			`assign pri6_out = 0;`
220			`endif
221
222			`ifdef HAVE_CH7
223			`wb_dma_pri_enc_sub u7(`
224			`.valid( valid[7] ),`
225			`.pri_in( pri7 ),`
226			`.pri_out( pri7_out )`
227			`);`
228			`else
229			`assign pri7_out = 0;`
230			`endif
231
232			`ifdef HAVE_CH8
233			`wb_dma_pri_enc_sub u8(`
234			`.valid( valid[8] ),`
235			`.pri_in( pri8 ),`
236			`.pri_out( pri8_out )`
237			`);`
238			`else
239			`assign pri8_out = 0;`
240			`endif
241
242			`ifdef HAVE_CH9
243			`wb_dma_pri_enc_sub u9(`
244			`.valid( valid[9] ),`
245			`.pri_in( pri9 ),`
246			`.pri_out( pri9_out )`
247			`);`
248			`else
249			`assign pri9_out = 0;`
250			`endif
251
252			`ifdef HAVE_CH10
253			`wb_dma_pri_enc_sub u10(`
254			`.valid( valid[10] ),`
255			`.pri_in( pri10 ),`
256			`.pri_out( pri10_out )`
257			`);`
258			`else
259			`assign pri10_out = 0;`
260			`endif
261
262			`ifdef HAVE_CH11
263			`wb_dma_pri_enc_sub u11(`
264			`.valid( valid[11] ),`
265			`.pri_in( pri11 ),`
266			`.pri_out( pri11_out )`
267			`);`
268			`else
269			`assign pri11_out = 0;`
270			`endif
271
272			`ifdef HAVE_CH12
273			`wb_dma_pri_enc_sub u12(`
274			`.valid( valid[12] ),`
275			`.pri_in( pri12 ),`
276			`.pri_out( pri12_out )`
277			`);`
278			`else
279			`assign pri12_out = 0;`
280			`endif
281
282			`ifdef HAVE_CH13
283			`wb_dma_pri_enc_sub u13(`
284			`.valid( valid[13] ),`
285			`.pri_in( pri13 ),`
286			`.pri_out( pri13_out )`
287			`);`
288			`else
289			`assign pri13_out = 0;`
290			`endif
291
292			`ifdef HAVE_CH14
293			`wb_dma_pri_enc_sub u14(`
294			`.valid( valid[14] ),`
295			`.pri_in( pri14 ),`
296			`.pri_out( pri14_out )`
297			`);`
298			`else
299			`assign pri14_out = 0;`
300			`endif
301
302			`ifdef HAVE_CH15
303			`wb_dma_pri_enc_sub u15(`
304			`.valid( valid[15] ),`
305			`.pri_in( pri15 ),`
306			`.pri_out( pri15_out )`
307			`);`
308			`else
309			`assign pri15_out = 0;`
310			`endif
311
312			`ifdef HAVE_CH16
313			`wb_dma_pri_enc_sub u16(`
314			`.valid( valid[16] ),`
315			`.pri_in( pri16 ),`
316			`.pri_out( pri16_out )`
317			`);`
318			`else
319			`assign pri16_out = 0;`
320			`endif
321
322			`ifdef HAVE_CH17
323			`wb_dma_pri_enc_sub u17(`
324			`.valid( valid[17] ),`
325			`.pri_in( pri17 ),`
326			`.pri_out( pri17_out )`
327			`);`
328			`else
329			`assign pri17_out = 0;`
330			`endif
331
332			`ifdef HAVE_CH18
333			`wb_dma_pri_enc_sub u18(`
334			`.valid( valid[18] ),`
335			`.pri_in( pri18 ),`
336			`.pri_out( pri18_out )`
337			`);`
338			`else
339			`assign pri18_out = 0;`
340			`endif
341
342			`ifdef HAVE_CH19
343			`wb_dma_pri_enc_sub u19(`
344			`.valid( valid[19] ),`
345			`.pri_in( pri19 ),`
346			`.pri_out( pri19_out )`
347			`);`
348			`else
349			`assign pri19_out = 0;`
350			`endif
351
352			`ifdef HAVE_CH20
353			`wb_dma_pri_enc_sub u20(`
354			`.valid( valid[20] ),`
355			`.pri_in( pri20 ),`
356			`.pri_out( pri20_out )`
357			`);`
358			`else
359			`assign pri20_out = 0;`
360			`endif
361
362			`ifdef HAVE_CH21
363			`wb_dma_pri_enc_sub u21(`
364			`.valid( valid[21] ),`
365			`.pri_in( pri21 ),`
366			`.pri_out( pri21_out )`
367			`);`
368			`else
369			`assign pri21_out = 0;`
370			`endif
371
372			`ifdef HAVE_CH22
373			`wb_dma_pri_enc_sub u22(`
374			`.valid( valid[22] ),`
375			`.pri_in( pri22 ),`
376			`.pri_out( pri22_out )`
377			`);`
378			`else
379			`assign pri22_out = 0;`
380			`endif
381
382			`ifdef HAVE_CH23
383			`wb_dma_pri_enc_sub u23(`
384			`.valid( valid[23] ),`
385			`.pri_in( pri23 ),`
386			`.pri_out( pri23_out )`
387			`);`
388			`else
389			`assign pri23_out = 0;`
390			`endif
391
392			`ifdef HAVE_CH24
393			`wb_dma_pri_enc_sub u24(`
394			`.valid( valid[24] ),`
395			`.pri_in( pri24 ),`
396			`.pri_out( pri24_out )`
397			`);`
398			`else
399			`assign pri24_out = 0;`
400			`endif
401
402			`ifdef HAVE_CH25
403			`wb_dma_pri_enc_sub u25(`
404			`.valid( valid[25] ),`
405			`.pri_in( pri25 ),`
406			`.pri_out( pri25_out )`
407			`);`
408			`else
409			`assign pri25_out = 0;`
410			`endif
411
412			`ifdef HAVE_CH26
413			`wb_dma_pri_enc_sub u26(`
414			`.valid( valid[26] ),`
415			`.pri_in( pri26 ),`
416			`.pri_out( pri26_out )`
417			`);`
418			`else
419			`assign pri26_out = 0;`
420			`endif
421
422			`ifdef HAVE_CH27
423			`wb_dma_pri_enc_sub u27(`
424			`.valid( valid[27] ),`
425			`.pri_in( pri27 ),`
426			`.pri_out( pri27_out )`
427			`);`
428			`else
429			`assign pri27_out = 0;`
430			`endif
431
432			`ifdef HAVE_CH28
433			`wb_dma_pri_enc_sub u28(`
434			`.valid( valid[28] ),`
435			`.pri_in( pri28 ),`
436			`.pri_out( pri28_out )`
437			`);`
438			`else
439			`assign pri28_out = 0;`
440			`endif
441
442			`ifdef HAVE_CH29
443			`wb_dma_pri_enc_sub u29(`
444			`.valid( valid[29] ),`
445			`.pri_in( pri29 ),`
446			`.pri_out( pri29_out )`
447			`);`
448			`else
449			`assign pri29_out = 0;`
450			`endif
451
452			`ifdef HAVE_CH30
453			`wb_dma_pri_enc_sub u30(`
454			`.valid( valid[30] ),`
455			`.pri_in( pri30 ),`
456			`.pri_out( pri30_out )`
457			`);`
458			`else
459			`assign pri30_out = 0;`
460			`endif
461
462			`assign pri_out_tmp = pri0_out \| pri1_out \| pri2_out \| pri3_out \|`
463			`pri4_out \| pri5_out \| pri6_out \| pri7_out \|`
464			`pri8_out \| pri9_out \| pri10_out \| pri11_out \|`
465			`pri12_out \| pri13_out \| pri14_out \| pri15_out \|`
466			`pri16_out \| pri17_out \| pri18_out \| pri19_out \|`
467			`pri20_out \| pri21_out \| pri22_out \| pri23_out \|`
468			`pri24_out \| pri25_out \| pri26_out \| pri27_out \|`
469			`pri28_out \| pri29_out \| pri30_out;`
470
471			`always @(posedge clk)`
472			`ifdef PRI_8
473			`if(pri_out_tmp[7]) pri_out <= #1 3'h7;`
474			`else`
475			`if(pri_out_tmp[6]) pri_out <= #1 3'h6;`
476			`else`
477			`if(pri_out_tmp[5]) pri_out <= #1 3'h5;`
478			`else`
479			`if(pri_out_tmp[4]) pri_out <= #1 3'h4;`
480			`else`
481			`if(pri_out_tmp[3]) pri_out <= #1 3'h3;`
482			`else`
483			`if(pri_out_tmp[2]) pri_out <= #1 3'h2;`
484			`else`
485			`endif
486			`ifdef PRI_4
487			`if(pri_out_tmp[3]) pri_out <= #1 3'h3;`
488			`else`
489			`if(pri_out_tmp[2]) pri_out <= #1 3'h2;`
490			`else`
491			`endif
492			`if(pri_out_tmp[1]) pri_out <= #1 3'h1;`
493			`else pri_out <= #1 3'h0;`
494
495			`endmodule`