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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE DMA One Channel Register File                     ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_dma_ch_rf.v,v 1.3 2001-10-19 04:35:04 rudi Exp $
//
//  $Date: 2001-10-19 04:35:04 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/08/15 05:40:30  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Added Section 3.10, describing DMA restart.
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.3  2001/06/14 08:50:01  rudi
//
//               Changed Module Name to match file name.
//
//               Revision 1.2  2001/06/13 02:26:48  rudi
//
//
//               Small changes after running lint.
//
//               Revision 1.1  2001/06/05 10:25:27  rudi
//
//
//               Initial checkin of register file for one channel.
//
//
//
//
 
`include "wb_dma_defines.v"
 
module wb_dma_ch_rf(    clk, rst,
                        pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
                        ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
 
                        wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
 
                        // DMA Registers Write Back Channel Select
                        ch_sel, ndnr,
 
                        // DMA Engine Status
                        dma_busy, dma_err, dma_done, dma_done_all,
 
                        // DMA Engine Reg File Update ctrl signals
                        de_csr, de_txsz, de_adr0, de_adr1,
                        de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
                        de_fetch_descr, dma_rest,
                        ptr_set
 
                );
 
parameter       [4:0]    CH_NO    = 5'h0;  // This Instances Channel ID
parameter       [0:0]     CH_EN    = 1'b1;  // This channel exists
parameter       [0:0]     HAVE_ARS = 1'b1;  // 1=this Instance Supports ARS
parameter       [0:0]     HAVE_ED  = 1'b1;  // 1=this Instance Supports External Descriptors
parameter       [0:0]     HAVE_CBUF= 1'b1;  // 1=this Instance Supports Cyclic Buffers
 
input           clk, rst;
 
output  [31:0]   pointer;
output  [31:0]   pointer_s;
output  [31:0]   ch_csr;
output  [31:0]   ch_txsz;
output  [31:0]   ch_adr0;
output  [31:0]   ch_adr1;
output  [31:0]   ch_am0;
output  [31:0]   ch_am1;
output  [31:0]   sw_pointer;
output          ch_stop;
output          ch_dis;
output          int;
 
input   [31:0]   wb_rf_din;
input   [7:0]    wb_rf_adr;
input           wb_rf_we;
input           wb_rf_re;
 
input   [4:0]    ch_sel;
input           ndnr;
 
// DMA Engine Status
input           dma_busy, dma_err, dma_done, dma_done_all;
 
// DMA Engine Reg File Update ctrl signals
input   [31:0]   de_csr;
input   [11:0]   de_txsz;
input   [31:0]   de_adr0;
input   [31:0]   de_adr1;
input           de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input           de_fetch_descr;
input           dma_rest;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
wire    [31:0]   pointer;
reg     [27:0]   pointer_r;
reg     [27:0]   pointer_sr;
reg             ptr_valid;
reg             ch_eol;
 
wire    [31:0]   ch_csr, ch_txsz;
 
reg     [8:0]    ch_csr_r;
reg     [2:0]    ch_csr_r2;
reg     [2:0]    ch_csr_r3;
reg     [2:0]    int_src_r;
reg             ch_err_r;
reg             ch_stop;
reg             ch_busy;
reg             ch_done;
reg             ch_err;
reg             rest_en;
 
reg     [10:0]   ch_chk_sz_r;
reg     [11:0]   ch_tot_sz_r;
reg     [22:0]   ch_txsz_s;
reg             ch_sz_inf;
 
wire    [31:0]   ch_adr0, ch_adr1;
reg     [29:0]   ch_adr0_r, ch_adr1_r;
wire    [31:0]   ch_am0, ch_am1;
reg     [27:0]   ch_am0_r, ch_am1_r;
 
reg     [29:0]   ch_adr0_s, ch_adr1_s;
 
reg     [29:0]   sw_pointer_r;
wire            sw_pointer_we;
wire    [28:0]   cmp_adr;
reg             ch_dis;
wire            ch_enable;
 
wire            pointer_we;
wire            ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we;
wire            ch_am0_we, ch_am1_we;
reg             ch_rl;
wire            ch_done_we;
wire            ch_err_we;
wire            chunk_done_we;
 
wire            ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe;
 
wire            this_ptr_set;
wire            ptr_inv;
 
////////////////////////////////////////////////////////////////////
//
// Aliases
//
 
assign ch_adr0          = CH_EN ? {ch_adr0_r, 2'h0}   : 32'h0;
assign ch_adr1          = CH_EN ? {ch_adr1_r, 2'h0}   : 32'h0;
assign ch_am0           = CH_EN ? {ch_am0_r, 4'h0}    : 32'h0;
assign ch_am1           = CH_EN ? {ch_am1_r, 4'h0}    : 32'h0;
assign sw_pointer       = CH_EN ? {sw_pointer_r,2'h0} : 32'h0;
 
assign pointer          = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
assign pointer_s        = CH_EN ? {pointer_sr, 4'h0}  : 32'h0;
assign ch_csr           = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
                                        ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
assign ch_txsz          = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0;
 
assign ch_enable        = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
 
////////////////////////////////////////////////////////////////////
//
// CH0 control signals
//
 
parameter       [4:0]    CH_ADR = CH_NO + 5'h1;
 
assign ch_csr_we        = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_csr_re        = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_txsz_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);
assign ch_adr0_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);
assign ch_am0_we        = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);
assign ch_adr1_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);
assign ch_am1_we        = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
assign pointer_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
assign sw_pointer_we    = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
 
assign ch_done_we       = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
                          (ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
assign chunk_done_we    = CH_EN & (ch_sel==CH_NO) & dma_done;
assign ch_err_we        = CH_EN & (ch_sel==CH_NO) & dma_err;
assign ch_csr_dewe      = CH_EN & de_csr_we & (ch_sel==CH_NO);
assign ch_txsz_dewe     = CH_EN & de_txsz_we & (ch_sel==CH_NO);
assign ch_adr0_dewe     = CH_EN & de_adr0_we & (ch_sel==CH_NO);
assign ch_adr1_dewe     = CH_EN & de_adr1_we & (ch_sel==CH_NO);
 
assign ptr_inv          = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr;
assign this_ptr_set     = CH_EN & ptr_set & (ch_sel==CH_NO);
 
always @(posedge clk)
        ch_rl <= #1     CH_EN & HAVE_ARS & (
                        (rest_en & dma_rest) |
                        ((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
                        );
 
// ---------------------------------------------------
// Pointers
 
always @(posedge clk or negedge rst)
        if(!rst)                        ptr_valid <= #1 1'b0;
        else
        if(CH_EN & HAVE_ED)
           begin
                if( this_ptr_set | (rest_en & dma_rest) )
                                        ptr_valid <= #1 1'b1;
                else
                if(ptr_inv)             ptr_valid <= #1 1'b0;
           end
        else                            ptr_valid <= #1 1'b0;
 
always @(posedge clk or negedge rst)
        if(!rst)                        ch_eol <= #1 1'b0;
        else
        if(CH_EN & HAVE_ED)
           begin
                if(ch_csr_dewe)         ch_eol <= #1 de_csr[`WDMA_ED_EOL];
                else
                if(ch_done_we)          ch_eol <= #1 1'b0;
           end
        else                            ch_eol <= #1 1'b0;
 
always @(posedge clk)
        if(CH_EN & HAVE_ED)
           begin
                if(pointer_we)          pointer_r <= #1 wb_rf_din[31:4];
                else
                if(this_ptr_set)        pointer_r <= #1 de_csr[31:4];
           end
        else                            pointer_r <= #1 1'b0;
 
always @(posedge clk)
        if(CH_EN & HAVE_ED)
           begin
                if(this_ptr_set)        pointer_sr <= #1 pointer_r;
           end
        else                            pointer_sr <= #1 1'b0;
 
// ---------------------------------------------------
// CSR
 
always @(posedge clk or negedge rst)
        if(!rst)                        ch_csr_r <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_csr_we)           ch_csr_r <= #1 wb_rf_din[8:0];
                else
                   begin
                        if(ch_done_we)  ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
                        if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
                   end
           end
 
// done bit
always @(posedge clk or negedge rst)
        if(!rst)                ch_done <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_csr_we)           ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
                else
                if(ch_done_we)          ch_done <= #1 1'b1;
           end
 
// busy bit
always @(posedge clk)
        ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;
 
// stop bit
always @(posedge clk)
        ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
 
// error bit
always @(posedge clk or negedge rst)
        if(!rst)                        ch_err <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_err_we)           ch_err <= #1 1'b1;
                else
                if(ch_csr_re)           ch_err <= #1 1'b0;
           end
 
// Priority Bits
always @(posedge clk or negedge rst)
        if(!rst)                        ch_csr_r2 <= #1 3'h0;
        else
        if(CH_EN & ch_csr_we)           ch_csr_r2 <= #1 wb_rf_din[15:13];
 
// Restart Enable Bit (REST)
always @(posedge clk or negedge rst)
        if(!rst)                        rest_en <= #1 1'b0;
        else
        if(CH_EN & ch_csr_we)           rest_en <= #1 wb_rf_din[16];
 
// INT Mask
always @(posedge clk or negedge rst)
        if(!rst)                        ch_csr_r3 <= #1 3'h0;
        else
        if(CH_EN & ch_csr_we)           ch_csr_r3 <= #1 wb_rf_din[19:17];
 
// INT Source
always @(posedge clk or negedge rst)
        if(!rst)                        int_src_r[2] <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(chunk_done_we)       int_src_r[2] <= #1 1'b1;
                else
                if(ch_csr_re)           int_src_r[2] <= #1 1'b0;
           end
 
always @(posedge clk or negedge rst)
        if(!rst)                        int_src_r[1] <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_done_we)          int_src_r[1] <= #1 1'b1;
                else
                if(ch_csr_re)           int_src_r[1] <= #1 1'b0;
           end
 
always @(posedge clk or negedge rst)
        if(!rst)                        int_src_r[0] <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_err_we)           int_src_r[0] <= #1 1'b1;
                else
                if(ch_csr_re)           int_src_r[0] <= #1 1'b0;
           end
 
// Interrupt Output
assign int = |(int_src_r & ch_csr_r3);
 
// ---------------------------------------------------
// TXZS
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_txsz_we)
                        {ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
                else
                if(ch_txsz_dewe)
                        ch_tot_sz_r <= #1 de_txsz;
                else
                if(ch_rl)
                        {ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
           end
 
// txsz shadow register
always @(posedge clk)
        if(CH_EN & HAVE_ARS)
           begin
 
                if(ch_txsz_we)  ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
                else
                if(rest_en & ch_txsz_dewe & de_fetch_descr)
                                ch_txsz_s[11:0] <= #1 de_txsz[11:0];
           end
 
// Infinite Size indicator
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_txsz_we)          ch_sz_inf <= #1 wb_rf_din[15];
           end
 
// ---------------------------------------------------
// ADR0
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_adr0_we)          ch_adr0_r <= #1 wb_rf_din[31:2];
                else
                if(ch_adr0_dewe)        ch_adr0_r <= #1 de_adr0[31:2];
                else
                if(ch_rl)               ch_adr0_r <= #1 ch_adr0_s;
           end
 
// Adr0 shadow register
always @(posedge clk)
        if(CH_EN & HAVE_ARS)
           begin
                if(ch_adr0_we)  ch_adr0_s <= #1 wb_rf_din[31:2];
                else
                if(rest_en & ch_adr0_dewe & de_fetch_descr)
                                ch_adr0_s <= #1 de_adr0[31:2];
           end
 
// ---------------------------------------------------
// AM0
always @(posedge clk or negedge rst)
        if(!rst)                        ch_am0_r <= #1 28'hfffffff;
        else
        if(ch_am0_we & HAVE_CBUF)       ch_am0_r <= #1 wb_rf_din[31:4];
 
// ---------------------------------------------------
// ADR1
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_adr1_we)          ch_adr1_r <= #1 wb_rf_din[31:2];
                else
                if(ch_adr1_dewe)        ch_adr1_r <= #1 de_adr1[31:2];
                else
                if(ch_rl)               ch_adr1_r <= #1 ch_adr1_s;
           end
 
// Adr1 shadow register
always @(posedge clk)
        if(CH_EN & HAVE_ARS)
           begin
                if(ch_adr1_we)  ch_adr1_s <= #1 wb_rf_din[31:2];
                else
                if(rest_en & ch_adr1_dewe & de_fetch_descr)
                                ch_adr1_s <= #1 de_adr1[31:2];
           end
 
// ---------------------------------------------------
// AM1
always @(posedge clk or negedge rst)
        if(!rst)                                ch_am1_r <= #1 28'hfffffff;
        else
        if(ch_am1_we & CH_EN & HAVE_CBUF)       ch_am1_r <= #1 wb_rf_din[31:4];
 
// ---------------------------------------------------
// Software Pointer
always @(posedge clk or negedge rst)
        if(!rst)                                sw_pointer_r <= #1 28'h0;
        else
        if(sw_pointer_we & CH_EN & HAVE_CBUF)   sw_pointer_r <= #1 wb_rf_din[31:4];
 
// ---------------------------------------------------
// Software Pointer Match logic
 
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
 
always @(posedge clk)
        ch_dis <= #1 (CH_EN & HAVE_CBUF) ? ((sw_pointer[30:2] == cmp_adr) & sw_pointer[31]) : 1'b0;
 
endmodule
 
 
module wb_dma_ch_rf_dummy(clk, rst,
                        pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
                        ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
 
                        wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
 
                        // DMA Registers Write Back Channel Select
                        ch_sel, ndnr,
 
                        // DMA Engine Status
                        dma_busy, dma_err, dma_done, dma_done_all,
 
                        // DMA Engine Reg File Update ctrl signals
                        de_csr, de_txsz, de_adr0, de_adr1,
                        de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
                        de_fetch_descr, dma_rest,
                        ptr_set
 
                );
 
parameter       CH_NO = 0;
parameter       HAVE_ARS = 1;
parameter       HAVE_ED  = 1;
parameter       HAVE_CBUF= 1;
 
input           clk, rst;
 
output  [31:0]   pointer;
output  [31:0]   pointer_s;
output  [31:0]   ch_csr;
output  [31:0]   ch_txsz;
output  [31:0]   ch_adr0;
output  [31:0]   ch_adr1;
output  [31:0]   ch_am0;
output  [31:0]   ch_am1;
output  [31:0]   sw_pointer;
output          ch_stop;
output          ch_dis;
output          int;
 
input   [31:0]   wb_rf_din;
input   [7:0]    wb_rf_adr;
input           wb_rf_we;
input           wb_rf_re;
 
input   [4:0]    ch_sel;
input           ndnr;
 
// DMA Engine Status
input           dma_busy, dma_err, dma_done, dma_done_all;
 
// DMA Engine Reg File Update ctrl signals
input   [31:0]   de_csr;
input   [11:0]   de_txsz;
input   [31:0]   de_adr0;
input   [31:0]   de_adr1;
input           de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input           de_fetch_descr;
input           dma_rest;
 
assign          pointer = 32'h0;
assign          pointer_s = 32'h0;
assign          ch_csr = 32'h0;
assign          ch_txsz = 32'h0;
assign          ch_adr0 = 32'h0;
assign          ch_adr1 = 32'h0;
assign          ch_am0 = 32'h0;
assign          ch_am1 = 32'h0;
assign          sw_pointer = 32'h0;
assign          ch_stop = 1'b0;
assign          ch_dis = 1'b0;
assign          int = 1'b0;
 
endmodule

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE DMA One Channel Register File ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	10	rudi	`// $Id: wb_dma_ch_rf.v,v 1.3 2001-10-19 04:35:04 rudi Exp $`
41	5	rudi	`//`
42	10	rudi	`// $Date: 2001-10-19 04:35:04 $`
43			`// $Revision: 1.3 $`
44	5	rudi	`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	10	rudi	`// Revision 1.2 2001/08/15 05:40:30 rudi`
51			`//`
52			`// - Changed IO names to be more clear.`
53			`// - Uniquifyed define names to be core specific.`
54			`// - Added Section 3.10, describing DMA restart.`
55			`//`
56	8	rudi	`// Revision 1.1 2001/07/29 08:57:02 rudi`
57			`//`
58			`//`
59			`// 1) Changed Directory Structure`
60			`// 2) Added restart signal (REST)`
61			`//`
62	5	rudi	`// Revision 1.3 2001/06/14 08:50:01 rudi`
63			`//`
64			`// Changed Module Name to match file name.`
65			`//`
66			`// Revision 1.2 2001/06/13 02:26:48 rudi`
67			`//`
68			`//`
69			`// Small changes after running lint.`
70			`//`
71			`// Revision 1.1 2001/06/05 10:25:27 rudi`
72			`//`
73			`//`
74			`// Initial checkin of register file for one channel.`
75			`//`
76			`//`
77			`//`
78			`//`
79
80			`include "wb_dma_defines.v"
81
82			`module wb_dma_ch_rf( clk, rst,`
83			`pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,`
84			`ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,`
85
86			`wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,`
87
88			`// DMA Registers Write Back Channel Select`
89			`ch_sel, ndnr,`
90
91			`// DMA Engine Status`
92			`dma_busy, dma_err, dma_done, dma_done_all,`
93
94			`// DMA Engine Reg File Update ctrl signals`
95			`de_csr, de_txsz, de_adr0, de_adr1,`
96			`de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,`
97			`de_fetch_descr, dma_rest,`
98			`ptr_set`
99
100			`);`
101
102			`parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID`
103	10	rudi	`parameter [0:0] CH_EN = 1'b1; // This channel exists`
104	5	rudi	`parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS`
105			`parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors`
106			`parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers`
107
108			`input clk, rst;`
109
110			`output [31:0] pointer;`
111			`output [31:0] pointer_s;`
112			`output [31:0] ch_csr;`
113			`output [31:0] ch_txsz;`
114			`output [31:0] ch_adr0;`
115			`output [31:0] ch_adr1;`
116			`output [31:0] ch_am0;`
117			`output [31:0] ch_am1;`
118			`output [31:0] sw_pointer;`
119			`output ch_stop;`
120			`output ch_dis;`
121			`output int;`
122
123			`input [31:0] wb_rf_din;`
124			`input [7:0] wb_rf_adr;`
125			`input wb_rf_we;`
126			`input wb_rf_re;`
127
128			`input [4:0] ch_sel;`
129			`input ndnr;`
130
131			`// DMA Engine Status`
132			`input dma_busy, dma_err, dma_done, dma_done_all;`
133
134			`// DMA Engine Reg File Update ctrl signals`
135			`input [31:0] de_csr;`
136			`input [11:0] de_txsz;`
137			`input [31:0] de_adr0;`
138			`input [31:0] de_adr1;`
139			`input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;`
140			`input de_fetch_descr;`
141			`input dma_rest;`
142
143			`////////////////////////////////////////////////////////////////////`
144			`//`
145			`// Local Wires and Registers`
146			`//`
147
148			`wire [31:0] pointer;`
149			`reg [27:0] pointer_r;`
150			`reg [27:0] pointer_sr;`
151			`reg ptr_valid;`
152			`reg ch_eol;`
153
154			`wire [31:0] ch_csr, ch_txsz;`
155
156			`reg [8:0] ch_csr_r;`
157			`reg [2:0] ch_csr_r2;`
158			`reg [2:0] ch_csr_r3;`
159			`reg [2:0] int_src_r;`
160			`reg ch_err_r;`
161			`reg ch_stop;`
162			`reg ch_busy;`
163			`reg ch_done;`
164			`reg ch_err;`
165			`reg rest_en;`
166
167			`reg [10:0] ch_chk_sz_r;`
168			`reg [11:0] ch_tot_sz_r;`
169			`reg [22:0] ch_txsz_s;`
170			`reg ch_sz_inf;`
171
172			`wire [31:0] ch_adr0, ch_adr1;`
173			`reg [29:0] ch_adr0_r, ch_adr1_r;`
174			`wire [31:0] ch_am0, ch_am1;`
175			`reg [27:0] ch_am0_r, ch_am1_r;`
176
177			`reg [29:0] ch_adr0_s, ch_adr1_s;`
178
179			`reg [29:0] sw_pointer_r;`
180			`wire sw_pointer_we;`
181			`wire [28:0] cmp_adr;`
182			`reg ch_dis;`
183			`wire ch_enable;`
184
185			`wire pointer_we;`
186			`wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we;`
187			`wire ch_am0_we, ch_am1_we;`
188			`reg ch_rl;`
189			`wire ch_done_we;`
190			`wire ch_err_we;`
191			`wire chunk_done_we;`
192
193			`wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe;`
194
195			`wire this_ptr_set;`
196			`wire ptr_inv;`
197
198			`////////////////////////////////////////////////////////////////////`
199			`//`
200			`// Aliases`
201			`//`
202
203	10	rudi	`assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0;`
204			`assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0;`
205			`assign ch_am0 = CH_EN ? {ch_am0_r, 4'h0} : 32'h0;`
206			`assign ch_am1 = CH_EN ? {ch_am1_r, 4'h0} : 32'h0;`
207			`assign sw_pointer = CH_EN ? {sw_pointer_r,2'h0} : 32'h0;`
208	5	rudi
209	10	rudi	`assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;`
210			`assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;`
211			`assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,`
212			`ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;`
213			`assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0;`
214	5	rudi
215	10	rudi	assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
216	5	rudi
217			`////////////////////////////////////////////////////////////////////`
218			`//`
219			`// CH0 control signals`
220			`//`
221
222			`parameter [4:0] CH_ADR = CH_NO + 5'h1;`
223
224	10	rudi	`assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);`
225			`assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);`
226			`assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);`
227			`assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);`
228			`assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);`
229			`assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);`
230			`assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);`
231			`assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);`
232			`assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);`
233	5	rudi
234	10	rudi	`assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) \| ndnr) &`
235	8	rudi	(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
236	10	rudi	`assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done;`
237			`assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err;`
238			`assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO);`
239			`assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO);`
240			`assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO);`
241			`assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO);`
242	5	rudi
243	10	rudi	`assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) \| ndnr;`
244			`assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO);`
245	5	rudi
246			`always @(posedge clk)`
247	10	rudi	`ch_rl <= #1 CH_EN & HAVE_ARS & (`
248	5	rudi	`(rest_en & dma_rest) \|`
249	8	rudi	((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
250	5	rudi	`);`
251
252			`// ---------------------------------------------------`
253			`// Pointers`
254
255			`always @(posedge clk or negedge rst)`
256			`if(!rst) ptr_valid <= #1 1'b0;`
257			`else`
258	10	rudi	`if(CH_EN & HAVE_ED)`
259	5	rudi	`begin`
260			`if( this_ptr_set \| (rest_en & dma_rest) )`
261			`ptr_valid <= #1 1'b1;`
262			`else`
263			`if(ptr_inv) ptr_valid <= #1 1'b0;`
264			`end`
265			`else ptr_valid <= #1 1'b0;`
266
267			`always @(posedge clk or negedge rst)`
268			`if(!rst) ch_eol <= #1 1'b0;`
269			`else`
270	10	rudi	`if(CH_EN & HAVE_ED)`
271	5	rudi	`begin`
272	8	rudi	if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
273	5	rudi	`else`
274			`if(ch_done_we) ch_eol <= #1 1'b0;`
275			`end`
276			`else ch_eol <= #1 1'b0;`
277
278			`always @(posedge clk)`
279	10	rudi	`if(CH_EN & HAVE_ED)`
280	5	rudi	`begin`
281			`if(pointer_we) pointer_r <= #1 wb_rf_din[31:4];`
282			`else`
283			`if(this_ptr_set) pointer_r <= #1 de_csr[31:4];`
284			`end`
285			`else pointer_r <= #1 1'b0;`
286
287			`always @(posedge clk)`
288	10	rudi	`if(CH_EN & HAVE_ED)`
289	5	rudi	`begin`
290			`if(this_ptr_set) pointer_sr <= #1 pointer_r;`
291			`end`
292			`else pointer_sr <= #1 1'b0;`
293
294			`// ---------------------------------------------------`
295			`// CSR`
296
297			`always @(posedge clk or negedge rst)`
298	10	rudi	`if(!rst) ch_csr_r <= #1 1'b0;`
299	5	rudi	`else`
300	10	rudi	`if(CH_EN)`
301	5	rudi	`begin`
302	10	rudi	`if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];`
303			`else`
304			`begin`
305			if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
306			`if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];`
307			`end`
308	5	rudi	`end`
309
310			`// done bit`
311			`always @(posedge clk or negedge rst)`
312			`if(!rst) ch_done <= #1 1'b0;`
313			`else`
314	10	rudi	`if(CH_EN)`
315			`begin`
316			if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
317			`else`
318			`if(ch_done_we) ch_done <= #1 1'b1;`
319			`end`
320	5	rudi
321			`// busy bit`
322			`always @(posedge clk)`
323	10	rudi	`ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;`
324	5	rudi
325			`// stop bit`
326			`always @(posedge clk)`
327	10	rudi	ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
328	5	rudi
329			`// error bit`
330			`always @(posedge clk or negedge rst)`
331	10	rudi	`if(!rst) ch_err <= #1 1'b0;`
332	5	rudi	`else`
333	10	rudi	`if(CH_EN)`
334			`begin`
335			`if(ch_err_we) ch_err <= #1 1'b1;`
336			`else`
337			`if(ch_csr_re) ch_err <= #1 1'b0;`
338			`end`
339	5	rudi
340			`// Priority Bits`
341			`always @(posedge clk or negedge rst)`
342	10	rudi	`if(!rst) ch_csr_r2 <= #1 3'h0;`
343	5	rudi	`else`
344	10	rudi	`if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13];`
345	5	rudi
346			`// Restart Enable Bit (REST)`
347			`always @(posedge clk or negedge rst)`
348	10	rudi	`if(!rst) rest_en <= #1 1'b0;`
349	5	rudi	`else`
350	10	rudi	`if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16];`
351	5	rudi
352			`// INT Mask`
353			`always @(posedge clk or negedge rst)`
354	10	rudi	`if(!rst) ch_csr_r3 <= #1 3'h0;`
355	5	rudi	`else`
356	10	rudi	`if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17];`
357	5	rudi
358			`// INT Source`
359			`always @(posedge clk or negedge rst)`
360	10	rudi	`if(!rst) int_src_r[2] <= #1 1'b0;`
361	5	rudi	`else`
362	10	rudi	`if(CH_EN)`
363			`begin`
364			`if(chunk_done_we) int_src_r[2] <= #1 1'b1;`
365			`else`
366			`if(ch_csr_re) int_src_r[2] <= #1 1'b0;`
367			`end`
368	5	rudi
369			`always @(posedge clk or negedge rst)`
370	10	rudi	`if(!rst) int_src_r[1] <= #1 1'b0;`
371	5	rudi	`else`
372	10	rudi	`if(CH_EN)`
373			`begin`
374			`if(ch_done_we) int_src_r[1] <= #1 1'b1;`
375			`else`
376			`if(ch_csr_re) int_src_r[1] <= #1 1'b0;`
377			`end`
378	5	rudi
379			`always @(posedge clk or negedge rst)`
380	10	rudi	`if(!rst) int_src_r[0] <= #1 1'b0;`
381	5	rudi	`else`
382	10	rudi	`if(CH_EN)`
383			`begin`
384			`if(ch_err_we) int_src_r[0] <= #1 1'b1;`
385			`else`
386			`if(ch_csr_re) int_src_r[0] <= #1 1'b0;`
387			`end`
388	5	rudi
389			`// Interrupt Output`
390			`assign int = \|(int_src_r & ch_csr_r3);`
391
392			`// ---------------------------------------------------`
393			`// TXZS`
394			`always @(posedge clk)`
395	10	rudi	`if(CH_EN)`
396			`begin`
397			`if(ch_txsz_we)`
398			`{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};`
399			`else`
400			`if(ch_txsz_dewe)`
401			`ch_tot_sz_r <= #1 de_txsz;`
402			`else`
403			`if(ch_rl)`
404			`{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;`
405			`end`
406	5	rudi
407			`// txsz shadow register`
408			`always @(posedge clk)`
409	10	rudi	`if(CH_EN & HAVE_ARS)`
410	5	rudi	`begin`
411
412			`if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};`
413			`else`
414			`if(rest_en & ch_txsz_dewe & de_fetch_descr)`
415			`ch_txsz_s[11:0] <= #1 de_txsz[11:0];`
416			`end`
417
418			`// Infinite Size indicator`
419			`always @(posedge clk)`
420	10	rudi	`if(CH_EN)`
421			`begin`
422			`if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];`
423			`end`
424	5	rudi
425			`// ---------------------------------------------------`
426			`// ADR0`
427			`always @(posedge clk)`
428	10	rudi	`if(CH_EN)`
429			`begin`
430			`if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2];`
431			`else`
432			`if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];`
433			`else`
434			`if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;`
435			`end`
436	5	rudi
437			`// Adr0 shadow register`
438			`always @(posedge clk)`
439	10	rudi	`if(CH_EN & HAVE_ARS)`
440	5	rudi	`begin`
441			`if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];`
442			`else`
443			`if(rest_en & ch_adr0_dewe & de_fetch_descr)`
444			`ch_adr0_s <= #1 de_adr0[31:2];`
445			`end`
446
447			`// ---------------------------------------------------`
448			`// AM0`
449			`always @(posedge clk or negedge rst)`
450			`if(!rst) ch_am0_r <= #1 28'hfffffff;`
451			`else`
452			`if(ch_am0_we & HAVE_CBUF) ch_am0_r <= #1 wb_rf_din[31:4];`
453
454			`// ---------------------------------------------------`
455			`// ADR1`
456			`always @(posedge clk)`
457	10	rudi	`if(CH_EN)`
458			`begin`
459			`if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2];`
460			`else`
461			`if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];`
462			`else`
463			`if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;`
464			`end`
465	5	rudi
466			`// Adr1 shadow register`
467			`always @(posedge clk)`
468	10	rudi	`if(CH_EN & HAVE_ARS)`
469	5	rudi	`begin`
470			`if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];`
471			`else`
472			`if(rest_en & ch_adr1_dewe & de_fetch_descr)`
473			`ch_adr1_s <= #1 de_adr1[31:2];`
474			`end`
475
476			`// ---------------------------------------------------`
477			`// AM1`
478			`always @(posedge clk or negedge rst)`
479	10	rudi	`if(!rst) ch_am1_r <= #1 28'hfffffff;`
480	5	rudi	`else`
481	10	rudi	`if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4];`
482	5	rudi
483			`// ---------------------------------------------------`
484			`// Software Pointer`
485			`always @(posedge clk or negedge rst)`
486	10	rudi	`if(!rst) sw_pointer_r <= #1 28'h0;`
487	5	rudi	`else`
488	10	rudi	`if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4];`
489	5	rudi
490			`// ---------------------------------------------------`
491			`// Software Pointer Match logic`
492
493			`assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];`
494
495			`always @(posedge clk)`
496	10	rudi	`ch_dis <= #1 (CH_EN & HAVE_CBUF) ? ((sw_pointer[30:2] == cmp_adr) & sw_pointer[31]) : 1'b0;`
497	5	rudi
498			`endmodule`
499
500

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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_ch_rf.v] - Blame information for rev 10