OpenCores
URL https://opencores.org/ocsvn/wb_dma/wb_dma/trunk

Subversion Repositories wb_dma

[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_ch_sel.v] - Blame information for rev 17

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 rudi 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
3 
////  WISHBONE DMA Channel Select                                ////
4 
////                                                             ////
5 
////                                                             ////
6 
////  Author: Rudolf Usselmann                                   ////
7 
////          rudi@asics.ws                                      ////
8 
////                                                             ////
9 
////                                                             ////
10 
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
11 
////                                                             ////
12 
/////////////////////////////////////////////////////////////////////
13 
////                                                             ////
14 15 rudi 
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
15 
////                         www.asics.ws                        ////
16 
////                         rudi@asics.ws                       ////
17 5 rudi 
////                                                             ////
18 
//// This source file may be used and distributed without        ////
19 
//// restriction provided that this copyright statement is not   ////
20 
//// removed from the file and that any derivative work contains ////
21 
//// the original copyright notice and the associated disclaimer.////
22 
////                                                             ////
23 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
24 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
25 
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
26 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
27 
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
28 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
29 
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
30 
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
31 
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
32 
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
33 
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
34 
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
35 
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
36 
////                                                             ////
37 
/////////////////////////////////////////////////////////////////////
38 
 
39 
//  CVS Log
40 
//
41 15 rudi 
//  $Id: wb_dma_ch_sel.v,v 1.4 2002-02-01 01:54:45 rudi Exp $
42 5 rudi 
//
43 15 rudi 
//  $Date: 2002-02-01 01:54:45 $
44 
//  $Revision: 1.4 $
45 5 rudi 
//  $Author: rudi $
46 
//  $Locker:  $
47 
//  $State: Exp $
48 
//
49 
// Change History:
50 
//               $Log: not supported by cvs2svn $
51 15 rudi 
//               Revision 1.3  2001/10/19 04:35:04  rudi
52 
//
53 
//               - Made the core parameterized
54 
//
55 10 rudi 
//               Revision 1.2  2001/08/15 05:40:30  rudi
56 
//
57 
//               - Changed IO names to be more clear.
58 
//               - Uniquifyed define names to be core specific.
59 
//               - Added Section 3.10, describing DMA restart.
60 
//
61 8 rudi 
//               Revision 1.1  2001/07/29 08:57:02  rudi
62 
//
63 
//
64 
//               1) Changed Directory Structure
65 
//               2) Added restart signal (REST)
66 
//
67 5 rudi 
//               Revision 1.4  2001/06/14 08:52:00  rudi
68 
//
69 
//
70 
//               Changed arbiter module name.
71 
//
72 
//               Revision 1.3  2001/06/13 02:26:48  rudi
73 
//
74 
//
75 
//               Small changes after running lint.
76 
//
77 
//               Revision 1.2  2001/06/05 10:22:36  rudi
78 
//
79 
//
80 
//               - Added Support of up to 31 channels
81 
//               - Added support for 2,4 and 8 priority levels
82 
//               - Now can have up to 31 channels
83 
//               - Added many configuration items
84 
//               - Changed reset to async
85 
//
86 
//               Revision 1.1.1.1  2001/03/19 13:10:35  rudi
87 
//               Initial Release
88 
//
89 
//
90 
//
91 
 
92 
`include "wb_dma_defines.v"
93 
 
94 
module wb_dma_ch_sel(clk, rst,
95 
 
96 
        // DMA Request Lines
97 
        req_i, ack_o, nd_i,
98 
 
99 
        // DMA Registers Inputs
100 
        pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1,
101 
        pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1,
102 
        pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1,
103 
        pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1,
104 
        pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1,
105 
        pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1,
106 
        pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1,
107 
        pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1,
108 
        pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1,
109 
        pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1,
110 
        pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1,
111 
        pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1,
112 
        pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1,
113 
        pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1,
114 
        pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1,
115 
        pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1,
116 
        pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1,
117 
        pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1,
118 
        pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1,
119 
        pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1,
120 
        pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1,
121 
        pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1,
122 
        pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1,
123 
        pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1,
124 
        pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1,
125 
        pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1,
126 
        pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1,
127 
        pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1,
128 
        pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1,
129 
        pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1,
130 
        pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1,
131 
 
132 
        // DMA Registers Write Back Channel Select
133 
        ch_sel, ndnr,
134 
 
135 
        // DMA Engine Interface
136 
        de_start, ndr, csr, pointer, txsz, adr0, adr1, am0, am1,
137 
        pointer_s, next_ch, de_ack, dma_busy
138 
        );
139 
 
140 10 rudi 
////////////////////////////////////////////////////////////////////
141 
//
142 
// Module Parameters
143 
//
144 
 
145 
// chXX_conf = { CBUF, ED, ARS, EN }
146 
parameter       [1:0]    pri_sel  = 2'h0;
147 
parameter       [3:0]    ch0_conf = 4'h1;
148 
parameter       [3:0]    ch1_conf = 4'h0;
149 
parameter       [3:0]    ch2_conf = 4'h0;
150 
parameter       [3:0]    ch3_conf = 4'h0;
151 
parameter       [3:0]    ch4_conf = 4'h0;
152 
parameter       [3:0]    ch5_conf = 4'h0;
153 
parameter       [3:0]    ch6_conf = 4'h0;
154 
parameter       [3:0]    ch7_conf = 4'h0;
155 
parameter       [3:0]    ch8_conf = 4'h0;
156 
parameter       [3:0]    ch9_conf = 4'h0;
157 
parameter       [3:0]    ch10_conf = 4'h0;
158 
parameter       [3:0]    ch11_conf = 4'h0;
159 
parameter       [3:0]    ch12_conf = 4'h0;
160 
parameter       [3:0]    ch13_conf = 4'h0;
161 
parameter       [3:0]    ch14_conf = 4'h0;
162 
parameter       [3:0]    ch15_conf = 4'h0;
163 
parameter       [3:0]    ch16_conf = 4'h0;
164 
parameter       [3:0]    ch17_conf = 4'h0;
165 
parameter       [3:0]    ch18_conf = 4'h0;
166 
parameter       [3:0]    ch19_conf = 4'h0;
167 
parameter       [3:0]    ch20_conf = 4'h0;
168 
parameter       [3:0]    ch21_conf = 4'h0;
169 
parameter       [3:0]    ch22_conf = 4'h0;
170 
parameter       [3:0]    ch23_conf = 4'h0;
171 
parameter       [3:0]    ch24_conf = 4'h0;
172 
parameter       [3:0]    ch25_conf = 4'h0;
173 
parameter       [3:0]    ch26_conf = 4'h0;
174 
parameter       [3:0]    ch27_conf = 4'h0;
175 
parameter       [3:0]    ch28_conf = 4'h0;
176 
parameter       [3:0]    ch29_conf = 4'h0;
177 
parameter       [3:0]    ch30_conf = 4'h0;
178 
 
179 
////////////////////////////////////////////////////////////////////
180 
//
181 
// Module IOs
182 
//
183 
 
184 5 rudi 
input           clk, rst;
185 
 
186 
// DMA Request Lines
187 
input   [30:0]   req_i;
188 
output  [30:0]   ack_o;
189 
input   [30:0]   nd_i;
190 
 
191 
// Channel Registers Inputs
192 
input   [31:0]   pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;
193 
input   [31:0]   pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;
194 
input   [31:0]   pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;
195 
input   [31:0]   pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;
196 
input   [31:0]   pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;
197 
input   [31:0]   pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;
198 
input   [31:0]   pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;
199 
input   [31:0]   pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;
200 
input   [31:0]   pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;
201 
input   [31:0]   pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;
202 
input   [31:0]   pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;
203 
input   [31:0]   pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;
204 
input   [31:0]   pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;
205 
input   [31:0]   pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;
206 
input   [31:0]   pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;
207 
input   [31:0]   pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;
208 
input   [31:0]   pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;
209 
input   [31:0]   pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;
210 
input   [31:0]   pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;
211 
input   [31:0]   pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;
212 
input   [31:0]   pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;
213 
input   [31:0]   pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;
214 
input   [31:0]   pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;
215 
input   [31:0]   pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;
216 
input   [31:0]   pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;
217 
input   [31:0]   pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;
218 
input   [31:0]   pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;
219 
input   [31:0]   pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;
220 
input   [31:0]   pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;
221 
input   [31:0]   pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;
222 
input   [31:0]   pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;
223 
 
224 
output  [4:0]    ch_sel;         // Write Back Channel Select
225 
output  [30:0]   ndnr;           // Next Descriptor No Request
226 
 
227 
output          de_start;       // Start DMA Engine Indicator
228 
output          ndr;            // Next Descriptor With Request (for current channel)
229 
output  [31:0]   csr;            // Selected Channel CSR
230 
output  [31:0]   pointer;        // LL Descriptor pointer
231 
output  [31:0]   pointer_s;      // LL Descriptor previous pointer
232 
output  [31:0]   txsz;           // Selected Channel Transfer Size
233 
output  [31:0]   adr0, adr1;     // Selected Channel Addresses
234 
output  [31:0]   am0, am1;       // Selected Channel Address Masks
235 
 
236 
input           next_ch;        // Indicates the DMA Engine is done
237 
                                // with current transfer
238 
input           de_ack;         // DMA engine ack output
239 
 
240 
input           dma_busy;
241 
 
242 
////////////////////////////////////////////////////////////////////
243 
//
244 
// Local Wires and Registers
245 
//
246 
 
247 
reg     [30:0]   ack_o;
248 
wire    [30:0]   valid;          // Indicates which channel is valid
249 
reg             valid_sel;
250 
reg     [30:0]   req_r;          // Channel Request inputs
251 
reg     [30:0]   ndr_r;          // Next Descriptor Registered (and Request)
252 
reg     [30:0]   ndnr;           // Next Descriptor Registered (and Not Request)
253 
wire    [2:0]    pri_out;        // Highest unserviced priority
254 
wire    [2:0]    pri0, pri1, pri2, pri3;         // Channel Priorities
255 
wire    [2:0]    pri4, pri5, pri6, pri7;
256 
wire    [2:0]    pri8, pri9, pri10, pri11;
257 
wire    [2:0]    pri12, pri13, pri14, pri15;
258 
wire    [2:0]    pri16, pri17, pri18, pri19;
259 
wire    [2:0]    pri20, pri21, pri22, pri23;
260 
wire    [2:0]    pri24, pri25, pri26, pri27;
261 
wire    [2:0]    pri28, pri29, pri30;
262 
reg     [4:0]    ch_sel_d;
263 
reg     [4:0]    ch_sel_r;
264 
 
265 
reg             ndr;
266 
reg             next_start;
267 
reg             de_start_r;
268 
reg     [31:0]   csr;            // Selected Channel CSR
269 
reg     [31:0]   pointer;
270 
reg     [31:0]   pointer_s;
271 
reg     [31:0]   txsz;           // Selected Channel Transfer Size
272 
reg     [31:0]   adr0, adr1;     // Selected Channel Addresses
273 
reg     [31:0]   am0, am1;       // Selected Channel Address Masks
274 
 
275 
                                // Arbiter Request Inputs
276 
wire    [30:0]   req_p0, req_p1, req_p2, req_p3;
277 
wire    [30:0]   req_p4, req_p5, req_p6, req_p7;
278 
wire    [30:0]   req_p8, req_p9, req_p10, req_p11;
279 
wire    [30:0]   req_p12, req_p13, req_p14, req_p15;
280 
wire    [30:0]   req_p16, req_p17, req_p18, req_p19;
281 
wire    [30:0]   req_p20, req_p21, req_p22, req_p23;
282 
wire    [30:0]   req_p24, req_p25, req_p26, req_p27;
283 
wire    [30:0]   req_p28, req_p29, req_p30;
284 
                                // Arbiter Grant Outputs
285 10 rudi 
wire    [4:0]    gnt_p0_d, gnt_p1_d, gnt_p2_d, gnt_p3_d;
286 
wire    [4:0]    gnt_p4_d, gnt_p5_d, gnt_p6_d, gnt_p7_d;
287 5 rudi 
wire    [4:0]    gnt_p0, gnt_p1, gnt_p2, gnt_p3;
288 
wire    [4:0]    gnt_p4, gnt_p5, gnt_p6, gnt_p7;
289 
wire    [4:0]    gnt_p8, gnt_p9, gnt_p10, gnt_p11;
290 
wire    [4:0]    gnt_p12, gnt_p13, gnt_p14, gnt_p15;
291 
wire    [4:0]    gnt_p16, gnt_p17, gnt_p18, gnt_p19;
292 
wire    [4:0]    gnt_p20, gnt_p21, gnt_p22, gnt_p23;
293 
wire    [4:0]    gnt_p24, gnt_p25, gnt_p26, gnt_p27;
294 
wire    [4:0]    gnt_p28, gnt_p29, gnt_p30;
295 
 
296 
 
297 
////////////////////////////////////////////////////////////////////
298 
//
299 
// Aliases
300 
//
301 
 
302 10 rudi 
assign pri0[0] = ch0_csr[13];
303 
assign pri0[1] = (pri_sel == 2'd0) ? 1'b0 : ch0_csr[14];
304 
assign pri0[2] = (pri_sel == 2'd2) ? ch0_csr[15] : 1'b0;
305 
assign pri1[0] = ch1_csr[13];
306 
assign pri1[1] = (pri_sel == 2'd0) ? 1'b0 : ch1_csr[14];
307 
assign pri1[2] = (pri_sel == 2'd2) ? ch1_csr[15] : 1'b0;
308 
assign pri2[0] = ch2_csr[13];
309 
assign pri2[1] = (pri_sel == 2'd0) ? 1'b0 : ch2_csr[14];
310 
assign pri2[2] = (pri_sel == 2'd2) ? ch2_csr[15] : 1'b0;
311 
assign pri3[0] = ch3_csr[13];
312 
assign pri3[1] = (pri_sel == 2'd0) ? 1'b0 : ch3_csr[14];
313 
assign pri3[2] = (pri_sel == 2'd2) ? ch3_csr[15] : 1'b0;
314 
assign pri4[0] = ch4_csr[13];
315 
assign pri4[1] = (pri_sel == 2'd0) ? 1'b0 : ch4_csr[14];
316 
assign pri4[2] = (pri_sel == 2'd2) ? ch4_csr[15] : 1'b0;
317 
assign pri5[0] = ch5_csr[13];
318 
assign pri5[1] = (pri_sel == 2'd0) ? 1'b0 : ch5_csr[14];
319 
assign pri5[2] = (pri_sel == 2'd2) ? ch5_csr[15] : 1'b0;
320 
assign pri6[0] = ch6_csr[13];
321 
assign pri6[1] = (pri_sel == 2'd0) ? 1'b0 : ch6_csr[14];
322 
assign pri6[2] = (pri_sel == 2'd2) ? ch6_csr[15] : 1'b0;
323 
assign pri7[0] = ch7_csr[13];
324 
assign pri7[1] = (pri_sel == 2'd0) ? 1'b0 : ch7_csr[14];
325 
assign pri7[2] = (pri_sel == 2'd2) ? ch7_csr[15] : 1'b0;
326 
assign pri8[0] = ch8_csr[13];
327 
assign pri8[1] = (pri_sel == 2'd0) ? 1'b0 : ch8_csr[14];
328 
assign pri8[2] = (pri_sel == 2'd2) ? ch8_csr[15] : 1'b0;
329 
assign pri9[0] = ch9_csr[13];
330 
assign pri9[1] = (pri_sel == 2'd0) ? 1'b0 : ch9_csr[14];
331 
assign pri9[2] = (pri_sel == 2'd2) ? ch9_csr[15] : 1'b0;
332 
assign pri10[0] = ch10_csr[13];
333 
assign pri10[1] = (pri_sel == 2'd0) ? 1'b0 : ch10_csr[14];
334 
assign pri10[2] = (pri_sel == 2'd2) ? ch10_csr[15] : 1'b0;
335 
assign pri11[0] = ch11_csr[13];
336 
assign pri11[1] = (pri_sel == 2'd0) ? 1'b0 : ch11_csr[14];
337 
assign pri11[2] = (pri_sel == 2'd2) ? ch11_csr[15] : 1'b0;
338 
assign pri12[0] = ch12_csr[13];
339 
assign pri12[1] = (pri_sel == 2'd0) ? 1'b0 : ch12_csr[14];
340 
assign pri12[2] = (pri_sel == 2'd2) ? ch12_csr[15] : 1'b0;
341 
assign pri13[0] = ch13_csr[13];
342 
assign pri13[1] = (pri_sel == 2'd0) ? 1'b0 : ch13_csr[14];
343 
assign pri13[2] = (pri_sel == 2'd2) ? ch13_csr[15] : 1'b0;
344 
assign pri14[0] = ch14_csr[13];
345 
assign pri14[1] = (pri_sel == 2'd0) ? 1'b0 : ch14_csr[14];
346 
assign pri14[2] = (pri_sel == 2'd2) ? ch14_csr[15] : 1'b0;
347 
assign pri15[0] = ch15_csr[13];
348 
assign pri15[1] = (pri_sel == 2'd0) ? 1'b0 : ch15_csr[14];
349 
assign pri15[2] = (pri_sel == 2'd2) ? ch15_csr[15] : 1'b0;
350 
assign pri16[0] = ch16_csr[13];
351 
assign pri16[1] = (pri_sel == 2'd0) ? 1'b0 : ch16_csr[14];
352 
assign pri16[2] = (pri_sel == 2'd2) ? ch16_csr[15] : 1'b0;
353 
assign pri17[0] = ch17_csr[13];
354 
assign pri17[1] = (pri_sel == 2'd0) ? 1'b0 : ch17_csr[14];
355 
assign pri17[2] = (pri_sel == 2'd2) ? ch17_csr[15] : 1'b0;
356 
assign pri18[0] = ch18_csr[13];
357 
assign pri18[1] = (pri_sel == 2'd0) ? 1'b0 : ch18_csr[14];
358 
assign pri18[2] = (pri_sel == 2'd2) ? ch18_csr[15] : 1'b0;
359 
assign pri19[0] = ch19_csr[13];
360 
assign pri19[1] = (pri_sel == 2'd0) ? 1'b0 : ch19_csr[14];
361 
assign pri19[2] = (pri_sel == 2'd2) ? ch19_csr[15] : 1'b0;
362 
assign pri20[0] = ch20_csr[13];
363 
assign pri20[1] = (pri_sel == 2'd0) ? 1'b0 : ch20_csr[14];
364 
assign pri20[2] = (pri_sel == 2'd2) ? ch20_csr[15] : 1'b0;
365 
assign pri21[0] = ch21_csr[13];
366 
assign pri21[1] = (pri_sel == 2'd0) ? 1'b0 : ch21_csr[14];
367 
assign pri21[2] = (pri_sel == 2'd2) ? ch21_csr[15] : 1'b0;
368 
assign pri22[0] = ch22_csr[13];
369 
assign pri22[1] = (pri_sel == 2'd0) ? 1'b0 : ch22_csr[14];
370 
assign pri22[2] = (pri_sel == 2'd2) ? ch22_csr[15] : 1'b0;
371 
assign pri23[0] = ch23_csr[13];
372 
assign pri23[1] = (pri_sel == 2'd0) ? 1'b0 : ch23_csr[14];
373 
assign pri23[2] = (pri_sel == 2'd2) ? ch23_csr[15] : 1'b0;
374 
assign pri24[0] = ch24_csr[13];
375 
assign pri24[1] = (pri_sel == 2'd0) ? 1'b0 : ch24_csr[14];
376 
assign pri24[2] = (pri_sel == 2'd2) ? ch24_csr[15] : 1'b0;
377 
assign pri25[0] = ch25_csr[13];
378 
assign pri25[1] = (pri_sel == 2'd0) ? 1'b0 : ch25_csr[14];
379 
assign pri25[2] = (pri_sel == 2'd2) ? ch25_csr[15] : 1'b0;
380 
assign pri26[0] = ch26_csr[13];
381 
assign pri26[1] = (pri_sel == 2'd0) ? 1'b0 : ch26_csr[14];
382 
assign pri26[2] = (pri_sel == 2'd2) ? ch26_csr[15] : 1'b0;
383 
assign pri27[0] = ch27_csr[13];
384 
assign pri27[1] = (pri_sel == 2'd0) ? 1'b0 : ch27_csr[14];
385 
assign pri27[2] = (pri_sel == 2'd2) ? ch27_csr[15] : 1'b0;
386 
assign pri28[0] = ch28_csr[13];
387 
assign pri28[1] = (pri_sel == 2'd0) ? 1'b0 : ch28_csr[14];
388 
assign pri28[2] = (pri_sel == 2'd2) ? ch28_csr[15] : 1'b0;
389 
assign pri29[0] = ch29_csr[13];
390 
assign pri29[1] = (pri_sel == 2'd0) ? 1'b0 : ch29_csr[14];
391 
assign pri29[2] = (pri_sel == 2'd2) ? ch29_csr[15] : 1'b0;
392 
assign pri30[0] = ch30_csr[13];
393 
assign pri30[1] = (pri_sel == 2'd0) ? 1'b0 : ch30_csr[14];
394 
assign pri30[2] = (pri_sel == 2'd2) ? ch30_csr[15] : 1'b0;
395 5 rudi 
 
396 
////////////////////////////////////////////////////////////////////
397 
//
398 
// Misc logic
399 
//
400 
 
401 
// Chanel Valid flag
402 
// The valid flag is asserted when the channel is enabled,
403 
// and is either in "normal mode" (software control) or
404 
// "hw handshake mode" (reqN control)
405 
// validN = ch_enabled & (sw_mode | (hw_mode & reqN) )
406 
 
407 
always @(posedge clk)
408 
        req_r <= #1 req_i & ~ack_o;
409 
 
410 10 rudi 
assign valid[0] = ch0_conf[0] & ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1);
411 
assign valid[1] = ch1_conf[0] & ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1);
412 
assign valid[2] = ch2_conf[0] & ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1);
413 
assign valid[3] = ch3_conf[0] & ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1);
414 
assign valid[4] = ch4_conf[0] & ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1);
415 
assign valid[5] = ch5_conf[0] & ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1);
416 
assign valid[6] = ch6_conf[0] & ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1);
417 
assign valid[7] = ch7_conf[0] & ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1);
418 
assign valid[8] = ch8_conf[0] & ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1);
419 
assign valid[9] = ch9_conf[0] & ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1);
420 
assign valid[10] = ch10_conf[0] & ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1);
421 
assign valid[11] = ch11_conf[0] & ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1);
422 
assign valid[12] = ch12_conf[0] & ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1);
423 
assign valid[13] = ch13_conf[0] & ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1);
424 
assign valid[14] = ch14_conf[0] & ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1);
425 
assign valid[15] = ch15_conf[0] & ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1);
426 
assign valid[16] = ch16_conf[0] & ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1);
427 
assign valid[17] = ch17_conf[0] & ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1);
428 
assign valid[18] = ch18_conf[0] & ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1);
429 
assign valid[19] = ch19_conf[0] & ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1);
430 
assign valid[20] = ch20_conf[0] & ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1);
431 
assign valid[21] = ch21_conf[0] & ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1);
432 
assign valid[22] = ch22_conf[0] & ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1);
433 
assign valid[23] = ch23_conf[0] & ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1);
434 
assign valid[24] = ch24_conf[0] & ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1);
435 
assign valid[25] = ch25_conf[0] & ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1);
436 
assign valid[26] = ch26_conf[0] & ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1);
437 
assign valid[27] = ch27_conf[0] & ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1);
438 
assign valid[28] = ch28_conf[0] & ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1);
439 
assign valid[29] = ch29_conf[0] & ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1);
440 
assign valid[30] = ch30_conf[0] & ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1);
441 5 rudi 
 
442 
always @(posedge clk)
443 
        ndr_r <= #1 nd_i & req_i;
444 
 
445 
always @(posedge clk)
446 
        ndnr <= #1 nd_i & ~req_i;
447 
 
448 
// Start Signal for DMA engine
449 
assign de_start = (valid_sel & !de_start_r ) | next_start;
450 
 
451 
always @(posedge clk)
452 
        de_start_r <= #1 valid_sel;
453 
 
454 
always @(posedge clk)
455 
        next_start <= #1 next_ch & valid_sel;
456 
 
457 
// Ack outputs for HW handshake mode
458 
always @(posedge clk)
459 10 rudi 
        ack_o[0] <= #1 ch0_conf[0] & (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack;
460 5 rudi 
 
461 
always @(posedge clk)
462 10 rudi 
        ack_o[1] <= #1 ch1_conf[0] & (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack;
463 5 rudi 
 
464 
always @(posedge clk)
465 10 rudi 
        ack_o[2] <= #1 ch2_conf[0] & (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack;
466 5 rudi 
 
467 
always @(posedge clk)
468 10 rudi 
        ack_o[3] <= #1 ch3_conf[0] & (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack;
469 5 rudi 
 
470 
always @(posedge clk)
471 10 rudi 
        ack_o[4] <= #1 ch4_conf[0] & (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack;
472 5 rudi 
 
473 
always @(posedge clk)
474 10 rudi 
        ack_o[5] <= #1 ch5_conf[0] & (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack;
475 5 rudi 
 
476 
always @(posedge clk)
477 10 rudi 
        ack_o[6] <= #1 ch6_conf[0] & (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack;
478 5 rudi 
 
479 
always @(posedge clk)
480 10 rudi 
        ack_o[7] <= #1 ch7_conf[0] & (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack;
481 5 rudi 
 
482 
always @(posedge clk)
483 10 rudi 
        ack_o[8] <= #1 ch8_conf[0] & (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack;
484 5 rudi 
 
485 
always @(posedge clk)
486 10 rudi 
        ack_o[9] <= #1 ch9_conf[0] & (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack;
487 5 rudi 
 
488 
always @(posedge clk)
489 10 rudi 
        ack_o[10] <= #1 ch10_conf[0] & (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack;
490 5 rudi 
 
491 
always @(posedge clk)
492 10 rudi 
        ack_o[11] <= #1 ch11_conf[0] & (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack;
493 5 rudi 
 
494 
always @(posedge clk)
495 10 rudi 
        ack_o[12] <= #1 ch12_conf[0] & (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack;
496 5 rudi 
 
497 
always @(posedge clk)
498 10 rudi 
        ack_o[13] <= #1 ch13_conf[0] & (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack;
499 5 rudi 
 
500 
always @(posedge clk)
501 10 rudi 
        ack_o[14] <= #1 ch14_conf[0] & (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack;
502 5 rudi 
 
503 
always @(posedge clk)
504 10 rudi 
        ack_o[15] <= #1 ch15_conf[0] & (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack;
505 5 rudi 
 
506 
always @(posedge clk)
507 10 rudi 
        ack_o[16] <= #1 ch16_conf[0] & (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack;
508 5 rudi 
 
509 
always @(posedge clk)
510 10 rudi 
        ack_o[17] <= #1 ch17_conf[0] & (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack;
511 5 rudi 
 
512 
always @(posedge clk)
513 10 rudi 
        ack_o[18] <= #1 ch18_conf[0] & (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack;
514 5 rudi 
 
515 
always @(posedge clk)
516 10 rudi 
        ack_o[19] <= #1 ch19_conf[0] & (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack;
517 5 rudi 
 
518 
always @(posedge clk)
519 10 rudi 
        ack_o[20] <= #1 ch20_conf[0] & (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack;
520 5 rudi 
 
521 
always @(posedge clk)
522 10 rudi 
        ack_o[21] <= #1 ch21_conf[0] & (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack;
523 5 rudi 
 
524 
always @(posedge clk)
525 10 rudi 
        ack_o[22] <= #1 ch22_conf[0] & (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack;
526 5 rudi 
 
527 
always @(posedge clk)
528 10 rudi 
        ack_o[23] <= #1 ch23_conf[0] & (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack;
529 5 rudi 
 
530 
always @(posedge clk)
531 10 rudi 
        ack_o[24] <= #1 ch24_conf[0] & (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack;
532 5 rudi 
 
533 
always @(posedge clk)
534 10 rudi 
        ack_o[25] <= #1 ch25_conf[0] & (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack;
535 5 rudi 
 
536 
always @(posedge clk)
537 10 rudi 
        ack_o[26] <= #1 ch26_conf[0] & (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack;
538 5 rudi 
 
539 
always @(posedge clk)
540 10 rudi 
        ack_o[27] <= #1 ch27_conf[0] & (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack;
541 5 rudi 
 
542 
always @(posedge clk)
543 10 rudi 
        ack_o[28] <= #1 ch28_conf[0] & (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack;
544 5 rudi 
 
545 
always @(posedge clk)
546 10 rudi 
        ack_o[29] <= #1 ch29_conf[0] & (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack;
547 5 rudi 
 
548 
always @(posedge clk)
549 10 rudi 
        ack_o[30] <= #1 ch30_conf[0] & (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack;
550 5 rudi 
 
551 
// Channel Select
552 
always @(posedge clk or negedge rst)
553 
        if(!rst)        ch_sel_r <= #1 0;
554 
        else
555 
        if(de_start)    ch_sel_r <= #1 ch_sel_d;
556 
 
557 
assign ch_sel = !dma_busy ? ch_sel_d : ch_sel_r;
558 
 
559 
////////////////////////////////////////////////////////////////////
560 
//
561 
// Select Registers based on arbiter (and priority) outputs
562 
//
563 
 
564 
always @(ch_sel or valid)
565 
        case(ch_sel)            // synopsys parallel_case full_case
566 
           5'h0:        valid_sel = valid[0];
567 
           5'h1:        valid_sel = valid[1];
568 
           5'h2:        valid_sel = valid[2];
569 
           5'h3:        valid_sel = valid[3];
570 
           5'h4:        valid_sel = valid[4];
571 
           5'h5:        valid_sel = valid[5];
572 
           5'h6:        valid_sel = valid[6];
573 
           5'h7:        valid_sel = valid[7];
574 
           5'h8:        valid_sel = valid[8];
575 
           5'h9:        valid_sel = valid[9];
576 
           5'ha:        valid_sel = valid[10];
577 
           5'hb:        valid_sel = valid[11];
578 
           5'hc:        valid_sel = valid[12];
579 
           5'hd:        valid_sel = valid[13];
580 
           5'he:        valid_sel = valid[14];
581 
           5'hf:        valid_sel = valid[15];
582 
           5'h10:       valid_sel = valid[16];
583 
           5'h11:       valid_sel = valid[17];
584 
           5'h12:       valid_sel = valid[18];
585 
           5'h13:       valid_sel = valid[19];
586 
           5'h14:       valid_sel = valid[20];
587 
           5'h15:       valid_sel = valid[21];
588 
           5'h16:       valid_sel = valid[22];
589 
           5'h17:       valid_sel = valid[23];
590 
           5'h18:       valid_sel = valid[24];
591 
           5'h19:       valid_sel = valid[25];
592 
           5'h1a:       valid_sel = valid[26];
593 
           5'h1b:       valid_sel = valid[27];
594 
           5'h1c:       valid_sel = valid[28];
595 
           5'h1d:       valid_sel = valid[29];
596 
           5'h1e:       valid_sel = valid[30];
597 
        endcase
598 
 
599 
always @(ch_sel or ndr_r)
600 
        case(ch_sel)            // synopsys parallel_case full_case
601 
           5'h0:        ndr = ndr_r[0];
602 
           5'h1:        ndr = ndr_r[1];
603 
           5'h2:        ndr = ndr_r[2];
604 
           5'h3:        ndr = ndr_r[3];
605 
           5'h4:        ndr = ndr_r[4];
606 
           5'h5:        ndr = ndr_r[5];
607 
           5'h6:        ndr = ndr_r[6];
608 
           5'h7:        ndr = ndr_r[7];
609 
           5'h8:        ndr = ndr_r[8];
610 
           5'h9:        ndr = ndr_r[9];
611 
           5'ha:        ndr = ndr_r[10];
612 
           5'hb:        ndr = ndr_r[11];
613 
           5'hc:        ndr = ndr_r[12];
614 
           5'hd:        ndr = ndr_r[13];
615 
           5'he:        ndr = ndr_r[14];
616 
           5'hf:        ndr = ndr_r[15];
617 
           5'h10:       ndr = ndr_r[16];
618 
           5'h11:       ndr = ndr_r[17];
619 
           5'h12:       ndr = ndr_r[18];
620 
           5'h13:       ndr = ndr_r[19];
621 
           5'h14:       ndr = ndr_r[20];
622 
           5'h15:       ndr = ndr_r[21];
623 
           5'h16:       ndr = ndr_r[22];
624 
           5'h17:       ndr = ndr_r[23];
625 
           5'h18:       ndr = ndr_r[24];
626 
           5'h19:       ndr = ndr_r[25];
627 
           5'h1a:       ndr = ndr_r[26];
628 
           5'h1b:       ndr = ndr_r[27];
629 
           5'h1c:       ndr = ndr_r[28];
630 
           5'h1d:       ndr = ndr_r[29];
631 
           5'h1e:       ndr = ndr_r[30];
632 
        endcase
633 
 
634 
always @(ch_sel or pointer0 or pointer1 or pointer2 or pointer3 or pointer4
635 
                or pointer5 or pointer6 or pointer7 or pointer8 or pointer9
636 
                or pointer10 or pointer11 or pointer12 or pointer13 or pointer14
637 
                or pointer15 or pointer16 or pointer17 or pointer18 or pointer19
638 
                or pointer20 or pointer21 or pointer22 or pointer23 or pointer24
639 
                or pointer25 or pointer26 or pointer27 or pointer28 or pointer29
640 
                or pointer30 )
641 
        case(ch_sel)            // synopsys parallel_case full_case
642 
           5'h0:        pointer = pointer0;
643 
           5'h1:        pointer = pointer1;
644 
           5'h2:        pointer = pointer2;
645 
           5'h3:        pointer = pointer3;
646 
           5'h4:        pointer = pointer4;
647 
           5'h5:        pointer = pointer5;
648 
           5'h6:        pointer = pointer6;
649 
           5'h7:        pointer = pointer7;
650 
           5'h8:        pointer = pointer8;
651 
           5'h9:        pointer = pointer9;
652 
           5'ha:        pointer = pointer10;
653 
           5'hb:        pointer = pointer11;
654 
           5'hc:        pointer = pointer12;
655 
           5'hd:        pointer = pointer13;
656 
           5'he:        pointer = pointer14;
657 
           5'hf:        pointer = pointer15;
658 
           5'h10:       pointer = pointer16;
659 
           5'h11:       pointer = pointer17;
660 
           5'h12:       pointer = pointer18;
661 
           5'h13:       pointer = pointer19;
662 
           5'h14:       pointer = pointer20;
663 
           5'h15:       pointer = pointer21;
664 
           5'h16:       pointer = pointer22;
665 
           5'h17:       pointer = pointer23;
666 
           5'h18:       pointer = pointer24;
667 
           5'h19:       pointer = pointer25;
668 
           5'h1a:       pointer = pointer26;
669 
           5'h1b:       pointer = pointer27;
670 
           5'h1c:       pointer = pointer28;
671 
           5'h1d:       pointer = pointer29;
672 
           5'h1e:       pointer = pointer30;
673 
        endcase
674 
 
675 
always @(ch_sel or pointer0_s or pointer1_s or pointer2_s or pointer3_s or pointer4_s
676 
                or pointer5_s or pointer6_s or pointer7_s or pointer8_s or pointer9_s
677 
                or pointer10_s or pointer11_s or pointer12_s or pointer13_s or pointer14_s
678 
                or pointer15_s or pointer16_s or pointer17_s or pointer18_s or pointer19_s
679 
                or pointer20_s or pointer21_s or pointer22_s or pointer23_s or pointer24_s
680 
                or pointer25_s or pointer26_s or pointer27_s or pointer28_s or pointer29_s
681 
                or pointer30_s )
682 
        case(ch_sel)            // synopsys parallel_case full_case
683 
           5'h0:        pointer_s = pointer0_s;
684 
           5'h1:        pointer_s = pointer1_s;
685 
           5'h2:        pointer_s = pointer2_s;
686 
           5'h3:        pointer_s = pointer3_s;
687 
           5'h4:        pointer_s = pointer4_s;
688 
           5'h5:        pointer_s = pointer5_s;
689 
           5'h6:        pointer_s = pointer6_s;
690 
           5'h7:        pointer_s = pointer7_s;
691 
           5'h8:        pointer_s = pointer8_s;
692 
           5'h9:        pointer_s = pointer9_s;
693 
           5'ha:        pointer_s = pointer10_s;
694 
           5'hb:        pointer_s = pointer11_s;
695 
           5'hc:        pointer_s = pointer12_s;
696 
           5'hd:        pointer_s = pointer13_s;
697 
           5'he:        pointer_s = pointer14_s;
698 
           5'hf:        pointer_s = pointer15_s;
699 
           5'h10:       pointer_s = pointer16_s;
700 
           5'h11:       pointer_s = pointer17_s;
701 
           5'h12:       pointer_s = pointer18_s;
702 
           5'h13:       pointer_s = pointer19_s;
703 
           5'h14:       pointer_s = pointer20_s;
704 
           5'h15:       pointer_s = pointer21_s;
705 
           5'h16:       pointer_s = pointer22_s;
706 
           5'h17:       pointer_s = pointer23_s;
707 
           5'h18:       pointer_s = pointer24_s;
708 
           5'h19:       pointer_s = pointer25_s;
709 
           5'h1a:       pointer_s = pointer26_s;
710 
           5'h1b:       pointer_s = pointer27_s;
711 
           5'h1c:       pointer_s = pointer28_s;
712 
           5'h1d:       pointer_s = pointer29_s;
713 
           5'h1e:       pointer_s = pointer30_s;
714 
        endcase
715 
 
716 
always @(ch_sel or ch0_csr or ch1_csr or ch2_csr or ch3_csr or ch4_csr
717 
                or ch5_csr or ch6_csr or ch7_csr or ch8_csr or ch9_csr
718 
                or ch10_csr or ch11_csr or ch12_csr or ch13_csr or ch14_csr
719 
                or ch15_csr or ch16_csr or ch17_csr or ch18_csr or ch19_csr
720 
                or ch20_csr or ch21_csr or ch22_csr or ch23_csr or ch24_csr
721 
                or ch25_csr or ch26_csr or ch27_csr or ch28_csr or ch29_csr
722 
                or ch30_csr )
723 
        case(ch_sel)            // synopsys parallel_case full_case
724 
           5'h0:        csr = ch0_csr;
725 
           5'h1:        csr = ch1_csr;
726 
           5'h2:        csr = ch2_csr;
727 
           5'h3:        csr = ch3_csr;
728 
           5'h4:        csr = ch4_csr;
729 
           5'h5:        csr = ch5_csr;
730 
           5'h6:        csr = ch6_csr;
731 
           5'h7:        csr = ch7_csr;
732 
           5'h8:        csr = ch8_csr;
733 
           5'h9:        csr = ch9_csr;
734 
           5'ha:        csr = ch10_csr;
735 
           5'hb:        csr = ch11_csr;
736 
           5'hc:        csr = ch12_csr;
737 
           5'hd:        csr = ch13_csr;
738 
           5'he:        csr = ch14_csr;
739 
           5'hf:        csr = ch15_csr;
740 
           5'h10:       csr = ch16_csr;
741 
           5'h11:       csr = ch17_csr;
742 
           5'h12:       csr = ch18_csr;
743 
           5'h13:       csr = ch19_csr;
744 
           5'h14:       csr = ch20_csr;
745 
           5'h15:       csr = ch21_csr;
746 
           5'h16:       csr = ch22_csr;
747 
           5'h17:       csr = ch23_csr;
748 
           5'h18:       csr = ch24_csr;
749 
           5'h19:       csr = ch25_csr;
750 
           5'h1a:       csr = ch26_csr;
751 
           5'h1b:       csr = ch27_csr;
752 
           5'h1c:       csr = ch28_csr;
753 
           5'h1d:       csr = ch29_csr;
754 
           5'h1e:       csr = ch30_csr;
755 
        endcase
756 
 
757 
always @(ch_sel or ch0_txsz or ch1_txsz or ch2_txsz or ch3_txsz or ch4_txsz
758 
                or ch5_txsz or ch6_txsz or ch7_txsz or ch8_txsz or ch9_txsz
759 
                or ch10_txsz or ch11_txsz or ch12_txsz or ch13_txsz or ch14_txsz
760 
                or ch15_txsz or ch16_txsz or ch17_txsz or ch18_txsz or ch19_txsz
761 
                or ch20_txsz or ch21_txsz or ch22_txsz or ch23_txsz or ch24_txsz
762 
                or ch25_txsz or ch26_txsz or ch27_txsz or ch28_txsz or ch29_txsz
763 
                or ch30_txsz )
764 
        case(ch_sel)            // synopsys parallel_case full_case
765 
           5'h0:        txsz = ch0_txsz;
766 
           5'h1:        txsz = ch1_txsz;
767 
           5'h2:        txsz = ch2_txsz;
768 
           5'h3:        txsz = ch3_txsz;
769 
           5'h4:        txsz = ch4_txsz;
770 
           5'h5:        txsz = ch5_txsz;
771 
           5'h6:        txsz = ch6_txsz;
772 
           5'h7:        txsz = ch7_txsz;
773 
           5'h8:        txsz = ch8_txsz;
774 
           5'h9:        txsz = ch9_txsz;
775 
           5'ha:        txsz = ch10_txsz;
776 
           5'hb:        txsz = ch11_txsz;
777 
           5'hc:        txsz = ch12_txsz;
778 
           5'hd:        txsz = ch13_txsz;
779 
           5'he:        txsz = ch14_txsz;
780 
           5'hf:        txsz = ch15_txsz;
781 
           5'h10:       txsz = ch16_txsz;
782 
           5'h11:       txsz = ch17_txsz;
783 
           5'h12:       txsz = ch18_txsz;
784 
           5'h13:       txsz = ch19_txsz;
785 
           5'h14:       txsz = ch20_txsz;
786 
           5'h15:       txsz = ch21_txsz;
787 
           5'h16:       txsz = ch22_txsz;
788 
           5'h17:       txsz = ch23_txsz;
789 
           5'h18:       txsz = ch24_txsz;
790 
           5'h19:       txsz = ch25_txsz;
791 
           5'h1a:       txsz = ch26_txsz;
792 
           5'h1b:       txsz = ch27_txsz;
793 
           5'h1c:       txsz = ch28_txsz;
794 
           5'h1d:       txsz = ch29_txsz;
795 
           5'h1e:       txsz = ch30_txsz;
796 
        endcase
797 
 
798 
always @(ch_sel or ch0_adr0 or ch1_adr0 or ch2_adr0 or ch3_adr0 or ch4_adr0
799 
                or ch5_adr0 or ch6_adr0 or ch7_adr0 or ch8_adr0 or ch9_adr0
800 
                or ch10_adr0 or ch11_adr0 or ch12_adr0 or ch13_adr0 or ch14_adr0
801 
                or ch15_adr0 or ch16_adr0 or ch17_adr0 or ch18_adr0 or ch19_adr0
802 
                or ch20_adr0 or ch21_adr0 or ch22_adr0 or ch23_adr0 or ch24_adr0
803 
                or ch25_adr0 or ch26_adr0 or ch27_adr0 or ch28_adr0 or ch29_adr0
804 
                or ch30_adr0 )
805 
        case(ch_sel)            // synopsys parallel_case full_case
806 
           5'h0:        adr0 = ch0_adr0;
807 
           5'h1:        adr0 = ch1_adr0;
808 
           5'h2:        adr0 = ch2_adr0;
809 
           5'h3:        adr0 = ch3_adr0;
810 
           5'h4:        adr0 = ch4_adr0;
811 
           5'h5:        adr0 = ch5_adr0;
812 
           5'h6:        adr0 = ch6_adr0;
813 
           5'h7:        adr0 = ch7_adr0;
814 
           5'h8:        adr0 = ch8_adr0;
815 
           5'h9:        adr0 = ch9_adr0;
816 
           5'ha:        adr0 = ch10_adr0;
817 
           5'hb:        adr0 = ch11_adr0;
818 
           5'hc:        adr0 = ch12_adr0;
819 
           5'hd:        adr0 = ch13_adr0;
820 
           5'he:        adr0 = ch14_adr0;
821 
           5'hf:        adr0 = ch15_adr0;
822 
           5'h10:       adr0 = ch16_adr0;
823 
           5'h11:       adr0 = ch17_adr0;
824 
           5'h12:       adr0 = ch18_adr0;
825 
           5'h13:       adr0 = ch19_adr0;
826 
           5'h14:       adr0 = ch20_adr0;
827 
           5'h15:       adr0 = ch21_adr0;
828 
           5'h16:       adr0 = ch22_adr0;
829 
           5'h17:       adr0 = ch23_adr0;
830 
           5'h18:       adr0 = ch24_adr0;
831 
           5'h19:       adr0 = ch25_adr0;
832 
           5'h1a:       adr0 = ch26_adr0;
833 
           5'h1b:       adr0 = ch27_adr0;
834 
           5'h1c:       adr0 = ch28_adr0;
835 
           5'h1d:       adr0 = ch29_adr0;
836 
           5'h1e:       adr0 = ch30_adr0;
837 
        endcase
838 
 
839 
always @(ch_sel or ch0_adr1 or ch1_adr1 or ch2_adr1 or ch3_adr1 or ch4_adr1
840 
                or ch5_adr1 or ch6_adr1 or ch7_adr1 or ch8_adr1 or ch9_adr1
841 
                or ch10_adr1 or ch11_adr1 or ch12_adr1 or ch13_adr1 or ch14_adr1
842 
                or ch15_adr1 or ch16_adr1 or ch17_adr1 or ch18_adr1 or ch19_adr1
843 
                or ch20_adr1 or ch21_adr1 or ch22_adr1 or ch23_adr1 or ch24_adr1
844 
                or ch25_adr1 or ch26_adr1 or ch27_adr1 or ch28_adr1 or ch29_adr1
845 
                or ch30_adr1 )
846 
        case(ch_sel)            // synopsys parallel_case full_case
847 
           5'h0:        adr1 = ch0_adr1;
848 
           5'h1:        adr1 = ch1_adr1;
849 
           5'h2:        adr1 = ch2_adr1;
850 
           5'h3:        adr1 = ch3_adr1;
851 
           5'h4:        adr1 = ch4_adr1;
852 
           5'h5:        adr1 = ch5_adr1;
853 
           5'h6:        adr1 = ch6_adr1;
854 
           5'h7:        adr1 = ch7_adr1;
855 
           5'h8:        adr1 = ch8_adr1;
856 
           5'h9:        adr1 = ch9_adr1;
857 
           5'ha:        adr1 = ch10_adr1;
858 
           5'hb:        adr1 = ch11_adr1;
859 
           5'hc:        adr1 = ch12_adr1;
860 
           5'hd:        adr1 = ch13_adr1;
861 
           5'he:        adr1 = ch14_adr1;
862 
           5'hf:        adr1 = ch15_adr1;
863 
           5'h10:       adr1 = ch16_adr1;
864 
           5'h11:       adr1 = ch17_adr1;
865 
           5'h12:       adr1 = ch18_adr1;
866 
           5'h13:       adr1 = ch19_adr1;
867 
           5'h14:       adr1 = ch20_adr1;
868 
           5'h15:       adr1 = ch21_adr1;
869 
           5'h16:       adr1 = ch22_adr1;
870 
           5'h17:       adr1 = ch23_adr1;
871 
           5'h18:       adr1 = ch24_adr1;
872 
           5'h19:       adr1 = ch25_adr1;
873 
           5'h1a:       adr1 = ch26_adr1;
874 
           5'h1b:       adr1 = ch27_adr1;
875 
           5'h1c:       adr1 = ch28_adr1;
876 
           5'h1d:       adr1 = ch29_adr1;
877 
           5'h1e:       adr1 = ch30_adr1;
878 
        endcase
879 
 
880 
always @(ch_sel or ch0_am0 or ch1_am0 or ch2_am0 or ch3_am0 or ch4_am0
881 
                or ch5_am0 or ch6_am0 or ch7_am0 or ch8_am0 or ch9_am0
882 
                or ch10_am0 or ch11_am0 or ch12_am0 or ch13_am0 or ch14_am0
883 
                or ch15_am0 or ch16_am0 or ch17_am0 or ch18_am0 or ch19_am0
884 
                or ch20_am0 or ch21_am0 or ch22_am0 or ch23_am0 or ch24_am0
885 
                or ch25_am0 or ch26_am0 or ch27_am0 or ch28_am0 or ch29_am0
886 
                or ch30_am0 )
887 
        case(ch_sel)            // synopsys parallel_case full_case
888 
           5'h0:        am0 = ch0_am0;
889 
           5'h1:        am0 = ch1_am0;
890 
           5'h2:        am0 = ch2_am0;
891 
           5'h3:        am0 = ch3_am0;
892 
           5'h4:        am0 = ch4_am0;
893 
           5'h5:        am0 = ch5_am0;
894 
           5'h6:        am0 = ch6_am0;
895 
           5'h7:        am0 = ch7_am0;
896 
           5'h8:        am0 = ch8_am0;
897 
           5'h9:        am0 = ch9_am0;
898 
           5'ha:        am0 = ch10_am0;
899 
           5'hb:        am0 = ch11_am0;
900 
           5'hc:        am0 = ch12_am0;
901 
           5'hd:        am0 = ch13_am0;
902 
           5'he:        am0 = ch14_am0;
903 
           5'hf:        am0 = ch15_am0;
904 
           5'h10:       am0 = ch16_am0;
905 
           5'h11:       am0 = ch17_am0;
906 
           5'h12:       am0 = ch18_am0;
907 
           5'h13:       am0 = ch19_am0;
908 
           5'h14:       am0 = ch20_am0;
909 
           5'h15:       am0 = ch21_am0;
910 
           5'h16:       am0 = ch22_am0;
911 
           5'h17:       am0 = ch23_am0;
912 
           5'h18:       am0 = ch24_am0;
913 
           5'h19:       am0 = ch25_am0;
914 
           5'h1a:       am0 = ch26_am0;
915 
           5'h1b:       am0 = ch27_am0;
916 
           5'h1c:       am0 = ch28_am0;
917 
           5'h1d:       am0 = ch29_am0;
918 
           5'h1e:       am0 = ch30_am0;
919 
        endcase
920 
 
921 
always @(ch_sel or ch0_am1 or ch1_am1 or ch2_am1 or ch3_am1 or ch4_am1
922 
                or ch5_am1 or ch6_am1 or ch7_am1 or ch8_am1 or ch9_am1
923 
                or ch10_am1 or ch11_am1 or ch12_am1 or ch13_am1 or ch14_am1
924 
                or ch15_am1 or ch16_am1 or ch17_am1 or ch18_am1 or ch19_am1
925 
                or ch20_am1 or ch21_am1 or ch22_am1 or ch23_am1 or ch24_am1
926 
                or ch25_am1 or ch26_am1 or ch27_am1 or ch28_am1 or ch29_am1
927 
                or ch30_am1 )
928 
        case(ch_sel)            // synopsys parallel_case full_case
929 
           5'h0:        am1 = ch0_am1;
930 
           5'h1:        am1 = ch1_am1;
931 
           5'h2:        am1 = ch2_am1;
932 
           5'h3:        am1 = ch3_am1;
933 
           5'h4:        am1 = ch4_am1;
934 
           5'h5:        am1 = ch5_am1;
935 
           5'h6:        am1 = ch6_am1;
936 
           5'h7:        am1 = ch7_am1;
937 
           5'h8:        am1 = ch8_am1;
938 
           5'h9:        am1 = ch9_am1;
939 
           5'ha:        am1 = ch10_am1;
940 
           5'hb:        am1 = ch11_am1;
941 
           5'hc:        am1 = ch12_am1;
942 
           5'hd:        am1 = ch13_am1;
943 
           5'he:        am1 = ch14_am1;
944 
           5'hf:        am1 = ch15_am1;
945 
           5'h10:       am1 = ch16_am1;
946 
           5'h11:       am1 = ch17_am1;
947 
           5'h12:       am1 = ch18_am1;
948 
           5'h13:       am1 = ch19_am1;
949 
           5'h14:       am1 = ch20_am1;
950 
           5'h15:       am1 = ch21_am1;
951 
           5'h16:       am1 = ch22_am1;
952 
           5'h17:       am1 = ch23_am1;
953 
           5'h18:       am1 = ch24_am1;
954 
           5'h19:       am1 = ch25_am1;
955 
           5'h1a:       am1 = ch26_am1;
956 
           5'h1b:       am1 = ch27_am1;
957 
           5'h1c:       am1 = ch28_am1;
958 
           5'h1d:       am1 = ch29_am1;
959 
           5'h1e:       am1 = ch30_am1;
960 
        endcase
961 
 
962 
////////////////////////////////////////////////////////////////////
963 
//
964 
// Actual Chanel Arbiter and Priority Encoder
965 
//
966 
 
967 
// Select the arbiter for current highest priority
968 
always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3 or gnt_p4
969 
                or gnt_p5 or gnt_p6 or gnt_p7 )
970 
        case(pri_out)           // synopsys parallel_case full_case
971 
           3'h0:        ch_sel_d = gnt_p0;
972 
           3'h1:        ch_sel_d = gnt_p1;
973 
           3'h2:        ch_sel_d = gnt_p2;
974 
           3'h3:        ch_sel_d = gnt_p3;
975 
           3'h4:        ch_sel_d = gnt_p4;
976 
           3'h5:        ch_sel_d = gnt_p5;
977 
           3'h6:        ch_sel_d = gnt_p6;
978 
           3'h7:        ch_sel_d = gnt_p7;
979 
        endcase
980 
 
981 
 
982 
// Priority Encoder
983 10 rudi 
wb_dma_ch_pri_enc
984 
        #(      pri_sel,
985 
                ch0_conf,
986 
                ch1_conf,
987 
                ch2_conf,
988 
                ch3_conf,
989 
                ch4_conf,
990 
                ch5_conf,
991 
                ch6_conf,
992 
                ch7_conf,
993 
                ch8_conf,
994 
                ch9_conf,
995 
                ch10_conf,
996 
                ch11_conf,
997 
                ch12_conf,
998 
                ch13_conf,
999 
                ch14_conf,
1000 
                ch15_conf,
1001 
                ch16_conf,
1002 
                ch17_conf,
1003 
                ch18_conf,
1004 
                ch19_conf,
1005 
                ch20_conf,
1006 
                ch21_conf,
1007 
                ch22_conf,
1008 
                ch23_conf,
1009 
                ch24_conf,
1010 
                ch25_conf,
1011 
                ch26_conf,
1012 
                ch27_conf,
1013 
                ch28_conf,
1014 
                ch29_conf,
1015 
                ch30_conf)
1016 
                u0(
1017 5 rudi 
                .clk(           clk             ),
1018 
                .valid(         valid           ),
1019 
                .pri0(          pri0            ),
1020 
                .pri1(          pri1            ),
1021 
                .pri2(          pri2            ),
1022 
                .pri3(          pri3            ),
1023 
                .pri4(          pri4            ),
1024 
                .pri5(          pri5            ),
1025 
                .pri6(          pri6            ),
1026 
                .pri7(          pri7            ),
1027 
                .pri8(          pri8            ),
1028 
                .pri9(          pri9            ),
1029 
                .pri10(         pri10           ),
1030 
                .pri11(         pri11           ),
1031 
                .pri12(         pri12           ),
1032 
                .pri13(         pri13           ),
1033 
                .pri14(         pri14           ),
1034 
                .pri15(         pri15           ),
1035 
                .pri16(         pri16           ),
1036 
                .pri17(         pri17           ),
1037 
                .pri18(         pri18           ),
1038 
                .pri19(         pri19           ),
1039 
                .pri20(         pri20           ),
1040 
                .pri21(         pri21           ),
1041 
                .pri22(         pri22           ),
1042 
                .pri23(         pri23           ),
1043 
                .pri24(         pri24           ),
1044 
                .pri25(         pri25           ),
1045 
                .pri26(         pri26           ),
1046 
                .pri27(         pri27           ),
1047 
                .pri28(         pri28           ),
1048 
                .pri29(         pri29           ),
1049 
                .pri30(         pri30           ),
1050 
                .pri_out(       pri_out         )
1051 
                );
1052 
 
1053 
// Arbiter request lines
1054 
// Generate request depending on priority and valid bits
1055 
 
1056 
assign req_p0[0] = valid[0] & (pri0==3'h0);
1057 
assign req_p0[1] = valid[1] & (pri1==3'h0);
1058 
assign req_p0[2] = valid[2] & (pri2==3'h0);
1059 
assign req_p0[3] = valid[3] & (pri3==3'h0);
1060 
assign req_p0[4] = valid[4] & (pri4==3'h0);
1061 
assign req_p0[5] = valid[5] & (pri5==3'h0);
1062 
assign req_p0[6] = valid[6] & (pri6==3'h0);
1063 
assign req_p0[7] = valid[7] & (pri7==3'h0);
1064 
assign req_p0[8] = valid[8] & (pri8==3'h0);
1065 
assign req_p0[9] = valid[9] & (pri9==3'h0);
1066 
assign req_p0[10] = valid[10] & (pri10==3'h0);
1067 
assign req_p0[11] = valid[11] & (pri11==3'h0);
1068 
assign req_p0[12] = valid[12] & (pri12==3'h0);
1069 
assign req_p0[13] = valid[13] & (pri13==3'h0);
1070 
assign req_p0[14] = valid[14] & (pri14==3'h0);
1071 
assign req_p0[15] = valid[15] & (pri15==3'h0);
1072 
assign req_p0[16] = valid[16] & (pri16==3'h0);
1073 
assign req_p0[17] = valid[17] & (pri17==3'h0);
1074 
assign req_p0[18] = valid[18] & (pri18==3'h0);
1075 
assign req_p0[19] = valid[19] & (pri19==3'h0);
1076 
assign req_p0[20] = valid[20] & (pri20==3'h0);
1077 
assign req_p0[21] = valid[21] & (pri21==3'h0);
1078 
assign req_p0[22] = valid[22] & (pri22==3'h0);
1079 
assign req_p0[23] = valid[23] & (pri23==3'h0);
1080 
assign req_p0[24] = valid[24] & (pri24==3'h0);
1081 
assign req_p0[25] = valid[25] & (pri25==3'h0);
1082 
assign req_p0[26] = valid[26] & (pri26==3'h0);
1083 
assign req_p0[27] = valid[27] & (pri27==3'h0);
1084 
assign req_p0[28] = valid[28] & (pri28==3'h0);
1085 
assign req_p0[29] = valid[29] & (pri29==3'h0);
1086 
assign req_p0[30] = valid[30] & (pri30==3'h0);
1087 
 
1088 
assign req_p1[0] = valid[0] & (pri0==3'h1);
1089 
assign req_p1[1] = valid[1] & (pri1==3'h1);
1090 
assign req_p1[2] = valid[2] & (pri2==3'h1);
1091 
assign req_p1[3] = valid[3] & (pri3==3'h1);
1092 
assign req_p1[4] = valid[4] & (pri4==3'h1);
1093 
assign req_p1[5] = valid[5] & (pri5==3'h1);
1094 
assign req_p1[6] = valid[6] & (pri6==3'h1);
1095 
assign req_p1[7] = valid[7] & (pri7==3'h1);
1096 
assign req_p1[8] = valid[8] & (pri8==3'h1);
1097 
assign req_p1[9] = valid[9] & (pri9==3'h1);
1098 
assign req_p1[10] = valid[10] & (pri10==3'h1);
1099 
assign req_p1[11] = valid[11] & (pri11==3'h1);
1100 
assign req_p1[12] = valid[12] & (pri12==3'h1);
1101 
assign req_p1[13] = valid[13] & (pri13==3'h1);
1102 
assign req_p1[14] = valid[14] & (pri14==3'h1);
1103 
assign req_p1[15] = valid[15] & (pri15==3'h1);
1104 
assign req_p1[16] = valid[16] & (pri16==3'h1);
1105 
assign req_p1[17] = valid[17] & (pri17==3'h1);
1106 
assign req_p1[18] = valid[18] & (pri18==3'h1);
1107 
assign req_p1[19] = valid[19] & (pri19==3'h1);
1108 
assign req_p1[20] = valid[20] & (pri20==3'h1);
1109 
assign req_p1[21] = valid[21] & (pri21==3'h1);
1110 
assign req_p1[22] = valid[22] & (pri22==3'h1);
1111 
assign req_p1[23] = valid[23] & (pri23==3'h1);
1112 
assign req_p1[24] = valid[24] & (pri24==3'h1);
1113 
assign req_p1[25] = valid[25] & (pri25==3'h1);
1114 
assign req_p1[26] = valid[26] & (pri26==3'h1);
1115 
assign req_p1[27] = valid[27] & (pri27==3'h1);
1116 
assign req_p1[28] = valid[28] & (pri28==3'h1);
1117 
assign req_p1[29] = valid[29] & (pri29==3'h1);
1118 
assign req_p1[30] = valid[30] & (pri30==3'h1);
1119 
 
1120 
assign req_p2[0] = valid[0] & (pri0==3'h2);
1121 
assign req_p2[1] = valid[1] & (pri1==3'h2);
1122 
assign req_p2[2] = valid[2] & (pri2==3'h2);
1123 
assign req_p2[3] = valid[3] & (pri3==3'h2);
1124 
assign req_p2[4] = valid[4] & (pri4==3'h2);
1125 
assign req_p2[5] = valid[5] & (pri5==3'h2);
1126 
assign req_p2[6] = valid[6] & (pri6==3'h2);
1127 
assign req_p2[7] = valid[7] & (pri7==3'h2);
1128 
assign req_p2[8] = valid[8] & (pri8==3'h2);
1129 
assign req_p2[9] = valid[9] & (pri9==3'h2);
1130 
assign req_p2[10] = valid[10] & (pri10==3'h2);
1131 
assign req_p2[11] = valid[11] & (pri11==3'h2);
1132 
assign req_p2[12] = valid[12] & (pri12==3'h2);
1133 
assign req_p2[13] = valid[13] & (pri13==3'h2);
1134 
assign req_p2[14] = valid[14] & (pri14==3'h2);
1135 
assign req_p2[15] = valid[15] & (pri15==3'h2);
1136 
assign req_p2[16] = valid[16] & (pri16==3'h2);
1137 
assign req_p2[17] = valid[17] & (pri17==3'h2);
1138 
assign req_p2[18] = valid[18] & (pri18==3'h2);
1139 
assign req_p2[19] = valid[19] & (pri19==3'h2);
1140 
assign req_p2[20] = valid[20] & (pri20==3'h2);
1141 
assign req_p2[21] = valid[21] & (pri21==3'h2);
1142 
assign req_p2[22] = valid[22] & (pri22==3'h2);
1143 
assign req_p2[23] = valid[23] & (pri23==3'h2);
1144 
assign req_p2[24] = valid[24] & (pri24==3'h2);
1145 
assign req_p2[25] = valid[25] & (pri25==3'h2);
1146 
assign req_p2[26] = valid[26] & (pri26==3'h2);
1147 
assign req_p2[27] = valid[27] & (pri27==3'h2);
1148 
assign req_p2[28] = valid[28] & (pri28==3'h2);
1149 
assign req_p2[29] = valid[29] & (pri29==3'h2);
1150 
assign req_p2[30] = valid[30] & (pri30==3'h2);
1151 
 
1152 
assign req_p3[0] = valid[0] & (pri0==3'h3);
1153 
assign req_p3[1] = valid[1] & (pri1==3'h3);
1154 
assign req_p3[2] = valid[2] & (pri2==3'h3);
1155 
assign req_p3[3] = valid[3] & (pri3==3'h3);
1156 
assign req_p3[4] = valid[4] & (pri4==3'h3);
1157 
assign req_p3[5] = valid[5] & (pri5==3'h3);
1158 
assign req_p3[6] = valid[6] & (pri6==3'h3);
1159 
assign req_p3[7] = valid[7] & (pri7==3'h3);
1160 
assign req_p3[8] = valid[8] & (pri8==3'h3);
1161 
assign req_p3[9] = valid[9] & (pri9==3'h3);
1162 
assign req_p3[10] = valid[10] & (pri10==3'h3);
1163 
assign req_p3[11] = valid[11] & (pri11==3'h3);
1164 
assign req_p3[12] = valid[12] & (pri12==3'h3);
1165 
assign req_p3[13] = valid[13] & (pri13==3'h3);
1166 
assign req_p3[14] = valid[14] & (pri14==3'h3);
1167 
assign req_p3[15] = valid[15] & (pri15==3'h3);
1168 
assign req_p3[16] = valid[16] & (pri16==3'h3);
1169 
assign req_p3[17] = valid[17] & (pri17==3'h3);
1170 
assign req_p3[18] = valid[18] & (pri18==3'h3);
1171 
assign req_p3[19] = valid[19] & (pri19==3'h3);
1172 
assign req_p3[20] = valid[20] & (pri20==3'h3);
1173 
assign req_p3[21] = valid[21] & (pri21==3'h3);
1174 
assign req_p3[22] = valid[22] & (pri22==3'h3);
1175 
assign req_p3[23] = valid[23] & (pri23==3'h3);
1176 
assign req_p3[24] = valid[24] & (pri24==3'h3);
1177 
assign req_p3[25] = valid[25] & (pri25==3'h3);
1178 
assign req_p3[26] = valid[26] & (pri26==3'h3);
1179 
assign req_p3[27] = valid[27] & (pri27==3'h3);
1180 
assign req_p3[28] = valid[28] & (pri28==3'h3);
1181 
assign req_p3[29] = valid[29] & (pri29==3'h3);
1182 
assign req_p3[30] = valid[30] & (pri30==3'h3);
1183 
 
1184 
assign req_p4[0] = valid[0] & (pri0==3'h4);
1185 
assign req_p4[1] = valid[1] & (pri1==3'h4);
1186 
assign req_p4[2] = valid[2] & (pri2==3'h4);
1187 
assign req_p4[3] = valid[3] & (pri3==3'h4);
1188 
assign req_p4[4] = valid[4] & (pri4==3'h4);
1189 
assign req_p4[5] = valid[5] & (pri5==3'h4);
1190 
assign req_p4[6] = valid[6] & (pri6==3'h4);
1191 
assign req_p4[7] = valid[7] & (pri7==3'h4);
1192 
assign req_p4[8] = valid[8] & (pri8==3'h4);
1193 
assign req_p4[9] = valid[9] & (pri9==3'h4);
1194 
assign req_p4[10] = valid[10] & (pri10==3'h4);
1195 
assign req_p4[11] = valid[11] & (pri11==3'h4);
1196 
assign req_p4[12] = valid[12] & (pri12==3'h4);
1197 
assign req_p4[13] = valid[13] & (pri13==3'h4);
1198 
assign req_p4[14] = valid[14] & (pri14==3'h4);
1199 
assign req_p4[15] = valid[15] & (pri15==3'h4);
1200 
assign req_p4[16] = valid[16] & (pri16==3'h4);
1201 
assign req_p4[17] = valid[17] & (pri17==3'h4);
1202 
assign req_p4[18] = valid[18] & (pri18==3'h4);
1203 
assign req_p4[19] = valid[19] & (pri19==3'h4);
1204 
assign req_p4[20] = valid[20] & (pri20==3'h4);
1205 
assign req_p4[21] = valid[21] & (pri21==3'h4);
1206 
assign req_p4[22] = valid[22] & (pri22==3'h4);
1207 
assign req_p4[23] = valid[23] & (pri23==3'h4);
1208 
assign req_p4[24] = valid[24] & (pri24==3'h4);
1209 
assign req_p4[25] = valid[25] & (pri25==3'h4);
1210 
assign req_p4[26] = valid[26] & (pri26==3'h4);
1211 
assign req_p4[27] = valid[27] & (pri27==3'h4);
1212 
assign req_p4[28] = valid[28] & (pri28==3'h4);
1213 
assign req_p4[29] = valid[29] & (pri29==3'h4);
1214 
assign req_p4[30] = valid[30] & (pri30==3'h4);
1215 
 
1216 
assign req_p5[0] = valid[0] & (pri0==3'h5);
1217 
assign req_p5[1] = valid[1] & (pri1==3'h5);
1218 
assign req_p5[2] = valid[2] & (pri2==3'h5);
1219 
assign req_p5[3] = valid[3] & (pri3==3'h5);
1220 
assign req_p5[4] = valid[4] & (pri4==3'h5);
1221 
assign req_p5[5] = valid[5] & (pri5==3'h5);
1222 
assign req_p5[6] = valid[6] & (pri6==3'h5);
1223 
assign req_p5[7] = valid[7] & (pri7==3'h5);
1224 
assign req_p5[8] = valid[8] & (pri8==3'h5);
1225 
assign req_p5[9] = valid[9] & (pri9==3'h5);
1226 
assign req_p5[10] = valid[10] & (pri10==3'h5);
1227 
assign req_p5[11] = valid[11] & (pri11==3'h5);
1228 
assign req_p5[12] = valid[12] & (pri12==3'h5);
1229 
assign req_p5[13] = valid[13] & (pri13==3'h5);
1230 
assign req_p5[14] = valid[14] & (pri14==3'h5);
1231 
assign req_p5[15] = valid[15] & (pri15==3'h5);
1232 
assign req_p5[16] = valid[16] & (pri16==3'h5);
1233 
assign req_p5[17] = valid[17] & (pri17==3'h5);
1234 
assign req_p5[18] = valid[18] & (pri18==3'h5);
1235 
assign req_p5[19] = valid[19] & (pri19==3'h5);
1236 
assign req_p5[20] = valid[20] & (pri20==3'h5);
1237 
assign req_p5[21] = valid[21] & (pri21==3'h5);
1238 
assign req_p5[22] = valid[22] & (pri22==3'h5);
1239 
assign req_p5[23] = valid[23] & (pri23==3'h5);
1240 
assign req_p5[24] = valid[24] & (pri24==3'h5);
1241 
assign req_p5[25] = valid[25] & (pri25==3'h5);
1242 
assign req_p5[26] = valid[26] & (pri26==3'h5);
1243 
assign req_p5[27] = valid[27] & (pri27==3'h5);
1244 
assign req_p5[28] = valid[28] & (pri28==3'h5);
1245 
assign req_p5[29] = valid[29] & (pri29==3'h5);
1246 
assign req_p5[30] = valid[30] & (pri30==3'h5);
1247 
 
1248 
assign req_p6[0] = valid[0] & (pri0==3'h6);
1249 
assign req_p6[1] = valid[1] & (pri1==3'h6);
1250 
assign req_p6[2] = valid[2] & (pri2==3'h6);
1251 
assign req_p6[3] = valid[3] & (pri3==3'h6);
1252 
assign req_p6[4] = valid[4] & (pri4==3'h6);
1253 
assign req_p6[5] = valid[5] & (pri5==3'h6);
1254 
assign req_p6[6] = valid[6] & (pri6==3'h6);
1255 
assign req_p6[7] = valid[7] & (pri7==3'h6);
1256 
assign req_p6[8] = valid[8] & (pri8==3'h6);
1257 
assign req_p6[9] = valid[9] & (pri9==3'h6);
1258 
assign req_p6[10] = valid[10] & (pri10==3'h6);
1259 
assign req_p6[11] = valid[11] & (pri11==3'h6);
1260 
assign req_p6[12] = valid[12] & (pri12==3'h6);
1261 
assign req_p6[13] = valid[13] & (pri13==3'h6);
1262 
assign req_p6[14] = valid[14] & (pri14==3'h6);
1263 
assign req_p6[15] = valid[15] & (pri15==3'h6);
1264 
assign req_p6[16] = valid[16] & (pri16==3'h6);
1265 
assign req_p6[17] = valid[17] & (pri17==3'h6);
1266 
assign req_p6[18] = valid[18] & (pri18==3'h6);
1267 
assign req_p6[19] = valid[19] & (pri19==3'h6);
1268 
assign req_p6[20] = valid[20] & (pri20==3'h6);
1269 
assign req_p6[21] = valid[21] & (pri21==3'h6);
1270 
assign req_p6[22] = valid[22] & (pri22==3'h6);
1271 
assign req_p6[23] = valid[23] & (pri23==3'h6);
1272 
assign req_p6[24] = valid[24] & (pri24==3'h6);
1273 
assign req_p6[25] = valid[25] & (pri25==3'h6);
1274 
assign req_p6[26] = valid[26] & (pri26==3'h6);
1275 
assign req_p6[27] = valid[27] & (pri27==3'h6);
1276 
assign req_p6[28] = valid[28] & (pri28==3'h6);
1277 
assign req_p6[29] = valid[29] & (pri29==3'h6);
1278 
assign req_p6[30] = valid[30] & (pri30==3'h6);
1279 
 
1280 
assign req_p7[0] = valid[0] & (pri0==3'h7);
1281 
assign req_p7[1] = valid[1] & (pri1==3'h7);
1282 
assign req_p7[2] = valid[2] & (pri2==3'h7);
1283 
assign req_p7[3] = valid[3] & (pri3==3'h7);
1284 
assign req_p7[4] = valid[4] & (pri4==3'h7);
1285 
assign req_p7[5] = valid[5] & (pri5==3'h7);
1286 
assign req_p7[6] = valid[6] & (pri6==3'h7);
1287 
assign req_p7[7] = valid[7] & (pri7==3'h7);
1288 
assign req_p7[8] = valid[8] & (pri8==3'h7);
1289 
assign req_p7[9] = valid[9] & (pri9==3'h7);
1290 
assign req_p7[10] = valid[10] & (pri10==3'h7);
1291 
assign req_p7[11] = valid[11] & (pri11==3'h7);
1292 
assign req_p7[12] = valid[12] & (pri12==3'h7);
1293 
assign req_p7[13] = valid[13] & (pri13==3'h7);
1294 
assign req_p7[14] = valid[14] & (pri14==3'h7);
1295 
assign req_p7[15] = valid[15] & (pri15==3'h7);
1296 
assign req_p7[16] = valid[16] & (pri16==3'h7);
1297 
assign req_p7[17] = valid[17] & (pri17==3'h7);
1298 
assign req_p7[18] = valid[18] & (pri18==3'h7);
1299 
assign req_p7[19] = valid[19] & (pri19==3'h7);
1300 
assign req_p7[20] = valid[20] & (pri20==3'h7);
1301 
assign req_p7[21] = valid[21] & (pri21==3'h7);
1302 
assign req_p7[22] = valid[22] & (pri22==3'h7);
1303 
assign req_p7[23] = valid[23] & (pri23==3'h7);
1304 
assign req_p7[24] = valid[24] & (pri24==3'h7);
1305 
assign req_p7[25] = valid[25] & (pri25==3'h7);
1306 
assign req_p7[26] = valid[26] & (pri26==3'h7);
1307 
assign req_p7[27] = valid[27] & (pri27==3'h7);
1308 
assign req_p7[28] = valid[28] & (pri28==3'h7);
1309 
assign req_p7[29] = valid[29] & (pri29==3'h7);
1310 
assign req_p7[30] = valid[30] & (pri30==3'h7);
1311 
 
1312 
// RR Arbiter for priority 0
1313 
wb_dma_ch_arb u1(
1314 
        .clk(           clk             ),
1315 
        .rst(           rst             ),
1316 
        .req(           req_p0          ),
1317 10 rudi 
        .gnt(           gnt_p0_d        ),
1318 5 rudi 
        .advance(       next_ch         )
1319 
        );
1320 
// RR Arbiter for priority 1
1321 
wb_dma_ch_arb u2(
1322 
        .clk(           clk             ),
1323 
        .rst(           rst             ),
1324 
        .req(           req_p1          ),
1325 10 rudi 
        .gnt(           gnt_p1_d        ),
1326 5 rudi 
        .advance(       next_ch         )
1327 
        );
1328 
 
1329 
// RR Arbiter for priority 2
1330 
wb_dma_ch_arb u3(
1331 
        .clk(           clk             ),
1332 
        .rst(           rst             ),
1333 
        .req(           req_p2          ),
1334 10 rudi 
        .gnt(           gnt_p2_d        ),
1335 5 rudi 
        .advance(       next_ch         )
1336 
        );
1337 
// RR Arbiter for priority 3
1338 
wb_dma_ch_arb u4(
1339 
        .clk(           clk             ),
1340 
        .rst(           rst             ),
1341 
        .req(           req_p3          ),
1342 10 rudi 
        .gnt(           gnt_p3_d        ),
1343 5 rudi 
        .advance(       next_ch         )
1344 
        );
1345 
// RR Arbiter for priority 4
1346 
wb_dma_ch_arb u5(
1347 
        .clk(           clk             ),
1348 
        .rst(           rst             ),
1349 
        .req(           req_p4          ),
1350 10 rudi 
        .gnt(           gnt_p4_d        ),
1351 5 rudi 
        .advance(       next_ch         )
1352 
        );
1353 
// RR Arbiter for priority 5
1354 
wb_dma_ch_arb u6(
1355 
        .clk(           clk             ),
1356 
        .rst(           rst             ),
1357 
        .req(           req_p5          ),
1358 10 rudi 
        .gnt(           gnt_p5_d        ),
1359 5 rudi 
        .advance(       next_ch         )
1360 
        );
1361 
// RR Arbiter for priority 6
1362 
wb_dma_ch_arb u7(
1363 
        .clk(           clk             ),
1364 
        .rst(           rst             ),
1365 
        .req(           req_p6          ),
1366 10 rudi 
        .gnt(           gnt_p6_d        ),
1367 5 rudi 
        .advance(       next_ch         )
1368 
        );
1369 
// RR Arbiter for priority 7
1370 
wb_dma_ch_arb u8(
1371 
        .clk(           clk             ),
1372 
        .rst(           rst             ),
1373 
        .req(           req_p7          ),
1374 10 rudi 
        .gnt(           gnt_p7_d        ),
1375 5 rudi 
        .advance(       next_ch         )
1376 
        );
1377 
 
1378 10 rudi 
// Select grant based on number of priorities
1379 
assign gnt_p0 = gnt_p0_d;
1380 
assign gnt_p1 = gnt_p1_d;
1381 
assign gnt_p2 = (pri_sel==2'd0) ? 5'h0 : gnt_p2_d;
1382 
assign gnt_p3 = (pri_sel==2'd0) ? 5'h0 : gnt_p3_d;
1383 
assign gnt_p4 = (pri_sel==2'd2) ? gnt_p4_d : 5'h0;
1384 
assign gnt_p5 = (pri_sel==2'd2) ? gnt_p5_d : 5'h0;
1385 
assign gnt_p6 = (pri_sel==2'd2) ? gnt_p6_d : 5'h0;
1386 
assign gnt_p7 = (pri_sel==2'd2) ? gnt_p7_d : 5'h0;
1387 5 rudi 
 
1388 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.