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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_ch_sel.v] - Blame information for rev 8

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1 5 rudi 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
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////  WISHBONE DMA Channel Select                                ////
4 
////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
7 
////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
13 
////                                                             ////
14 
//// Copyright (C) 2001 Rudolf Usselmann                         ////
15 
////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
20 
//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
27 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
37 
 
38 
//  CVS Log
39 
//
40 8 rudi 
//  $Id: wb_dma_ch_sel.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
41 5 rudi 
//
42 8 rudi 
//  $Date: 2001-08-15 05:40:30 $
43 
//  $Revision: 1.2 $
44 5 rudi 
//  $Author: rudi $
45 
//  $Locker:  $
46 
//  $State: Exp $
47 
//
48 
// Change History:
49 
//               $Log: not supported by cvs2svn $
50 8 rudi 
//               Revision 1.1  2001/07/29 08:57:02  rudi
51 
//
52 
//
53 
//               1) Changed Directory Structure
54 
//               2) Added restart signal (REST)
55 
//
56 5 rudi 
//               Revision 1.4  2001/06/14 08:52:00  rudi
57 
//
58 
//
59 
//               Changed arbiter module name.
60 
//
61 
//               Revision 1.3  2001/06/13 02:26:48  rudi
62 
//
63 
//
64 
//               Small changes after running lint.
65 
//
66 
//               Revision 1.2  2001/06/05 10:22:36  rudi
67 
//
68 
//
69 
//               - Added Support of up to 31 channels
70 
//               - Added support for 2,4 and 8 priority levels
71 
//               - Now can have up to 31 channels
72 
//               - Added many configuration items
73 
//               - Changed reset to async
74 
//
75 
//               Revision 1.1.1.1  2001/03/19 13:10:35  rudi
76 
//               Initial Release
77 
//
78 
//
79 
//
80 
 
81 
`include "wb_dma_defines.v"
82 
 
83 
module wb_dma_ch_sel(clk, rst,
84 
 
85 
        // DMA Request Lines
86 
        req_i, ack_o, nd_i,
87 
 
88 
        // DMA Registers Inputs
89 
        pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1,
90 
        pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1,
91 
        pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1,
92 
        pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1,
93 
        pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1,
94 
        pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1,
95 
        pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1,
96 
        pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1,
97 
        pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1,
98 
        pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1,
99 
        pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1,
100 
        pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1,
101 
        pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1,
102 
        pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1,
103 
        pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1,
104 
        pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1,
105 
        pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1,
106 
        pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1,
107 
        pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1,
108 
        pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1,
109 
        pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1,
110 
        pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1,
111 
        pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1,
112 
        pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1,
113 
        pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1,
114 
        pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1,
115 
        pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1,
116 
        pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1,
117 
        pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1,
118 
        pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1,
119 
        pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1,
120 
 
121 
        // DMA Registers Write Back Channel Select
122 
        ch_sel, ndnr,
123 
 
124 
        // DMA Engine Interface
125 
        de_start, ndr, csr, pointer, txsz, adr0, adr1, am0, am1,
126 
        pointer_s, next_ch, de_ack, dma_busy
127 
        );
128 
 
129 
input           clk, rst;
130 
 
131 
// DMA Request Lines
132 
input   [30:0]   req_i;
133 
output  [30:0]   ack_o;
134 
input   [30:0]   nd_i;
135 
 
136 
// Channel Registers Inputs
137 
input   [31:0]   pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;
138 
input   [31:0]   pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;
139 
input   [31:0]   pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;
140 
input   [31:0]   pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;
141 
input   [31:0]   pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;
142 
input   [31:0]   pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;
143 
input   [31:0]   pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;
144 
input   [31:0]   pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;
145 
input   [31:0]   pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;
146 
input   [31:0]   pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;
147 
input   [31:0]   pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;
148 
input   [31:0]   pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;
149 
input   [31:0]   pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;
150 
input   [31:0]   pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;
151 
input   [31:0]   pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;
152 
input   [31:0]   pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;
153 
input   [31:0]   pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;
154 
input   [31:0]   pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;
155 
input   [31:0]   pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;
156 
input   [31:0]   pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;
157 
input   [31:0]   pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;
158 
input   [31:0]   pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;
159 
input   [31:0]   pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;
160 
input   [31:0]   pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;
161 
input   [31:0]   pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;
162 
input   [31:0]   pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;
163 
input   [31:0]   pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;
164 
input   [31:0]   pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;
165 
input   [31:0]   pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;
166 
input   [31:0]   pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;
167 
input   [31:0]   pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;
168 
 
169 
output  [4:0]    ch_sel;         // Write Back Channel Select
170 
output  [30:0]   ndnr;           // Next Descriptor No Request
171 
 
172 
output          de_start;       // Start DMA Engine Indicator
173 
output          ndr;            // Next Descriptor With Request (for current channel)
174 
output  [31:0]   csr;            // Selected Channel CSR
175 
output  [31:0]   pointer;        // LL Descriptor pointer
176 
output  [31:0]   pointer_s;      // LL Descriptor previous pointer
177 
output  [31:0]   txsz;           // Selected Channel Transfer Size
178 
output  [31:0]   adr0, adr1;     // Selected Channel Addresses
179 
output  [31:0]   am0, am1;       // Selected Channel Address Masks
180 
 
181 
input           next_ch;        // Indicates the DMA Engine is done
182 
                                // with current transfer
183 
input           de_ack;         // DMA engine ack output
184 
 
185 
input           dma_busy;
186 
 
187 
////////////////////////////////////////////////////////////////////
188 
//
189 
// Local Wires and Registers
190 
//
191 
 
192 
reg     [30:0]   ack_o;
193 
wire    [30:0]   valid;          // Indicates which channel is valid
194 
reg             valid_sel;
195 
reg     [30:0]   req_r;          // Channel Request inputs
196 
reg     [30:0]   ndr_r;          // Next Descriptor Registered (and Request)
197 
reg     [30:0]   ndnr;           // Next Descriptor Registered (and Not Request)
198 
wire    [2:0]    pri_out;        // Highest unserviced priority
199 
wire    [2:0]    pri0, pri1, pri2, pri3;         // Channel Priorities
200 
wire    [2:0]    pri4, pri5, pri6, pri7;
201 
wire    [2:0]    pri8, pri9, pri10, pri11;
202 
wire    [2:0]    pri12, pri13, pri14, pri15;
203 
wire    [2:0]    pri16, pri17, pri18, pri19;
204 
wire    [2:0]    pri20, pri21, pri22, pri23;
205 
wire    [2:0]    pri24, pri25, pri26, pri27;
206 
wire    [2:0]    pri28, pri29, pri30;
207 
reg     [4:0]    ch_sel_d;
208 
reg     [4:0]    ch_sel_r;
209 
 
210 
reg             ndr;
211 
reg             next_start;
212 
reg             de_start_r;
213 
reg     [31:0]   csr;            // Selected Channel CSR
214 
reg     [31:0]   pointer;
215 
reg     [31:0]   pointer_s;
216 
reg     [31:0]   txsz;           // Selected Channel Transfer Size
217 
reg     [31:0]   adr0, adr1;     // Selected Channel Addresses
218 
reg     [31:0]   am0, am1;       // Selected Channel Address Masks
219 
 
220 
                                // Arbiter Request Inputs
221 
wire    [30:0]   req_p0, req_p1, req_p2, req_p3;
222 
wire    [30:0]   req_p4, req_p5, req_p6, req_p7;
223 
wire    [30:0]   req_p8, req_p9, req_p10, req_p11;
224 
wire    [30:0]   req_p12, req_p13, req_p14, req_p15;
225 
wire    [30:0]   req_p16, req_p17, req_p18, req_p19;
226 
wire    [30:0]   req_p20, req_p21, req_p22, req_p23;
227 
wire    [30:0]   req_p24, req_p25, req_p26, req_p27;
228 
wire    [30:0]   req_p28, req_p29, req_p30;
229 
                                // Arbiter Grant Outputs
230 
wire    [4:0]    gnt_p0, gnt_p1, gnt_p2, gnt_p3;
231 
wire    [4:0]    gnt_p4, gnt_p5, gnt_p6, gnt_p7;
232 
wire    [4:0]    gnt_p8, gnt_p9, gnt_p10, gnt_p11;
233 
wire    [4:0]    gnt_p12, gnt_p13, gnt_p14, gnt_p15;
234 
wire    [4:0]    gnt_p16, gnt_p17, gnt_p18, gnt_p19;
235 
wire    [4:0]    gnt_p20, gnt_p21, gnt_p22, gnt_p23;
236 
wire    [4:0]    gnt_p24, gnt_p25, gnt_p26, gnt_p27;
237 
wire    [4:0]    gnt_p28, gnt_p29, gnt_p30;
238 
 
239 
 
240 
////////////////////////////////////////////////////////////////////
241 
//
242 
// Aliases
243 
//
244 
 
245 8 rudi 
`ifdef WDMA_PRI_8
246 5 rudi 
assign pri0 = ch0_csr[15:13];
247 
assign pri1 = ch1_csr[15:13];
248 
assign pri2 = ch2_csr[15:13];
249 
assign pri3 = ch3_csr[15:13];
250 
assign pri4 = ch4_csr[15:13];
251 
assign pri5 = ch5_csr[15:13];
252 
assign pri6 = ch6_csr[15:13];
253 
assign pri7 = ch7_csr[15:13];
254 
assign pri8 = ch8_csr[15:13];
255 
assign pri9 = ch9_csr[15:13];
256 
assign pri10 = ch10_csr[15:13];
257 
assign pri11 = ch11_csr[15:13];
258 
assign pri12 = ch12_csr[15:13];
259 
assign pri13 = ch13_csr[15:13];
260 
assign pri14 = ch14_csr[15:13];
261 
assign pri15 = ch15_csr[15:13];
262 
assign pri16 = ch16_csr[15:13];
263 
assign pri17 = ch17_csr[15:13];
264 
assign pri18 = ch18_csr[15:13];
265 
assign pri19 = ch19_csr[15:13];
266 
assign pri20 = ch20_csr[15:13];
267 
assign pri21 = ch21_csr[15:13];
268 
assign pri22 = ch22_csr[15:13];
269 
assign pri23 = ch23_csr[15:13];
270 
assign pri24 = ch24_csr[15:13];
271 
assign pri25 = ch25_csr[15:13];
272 
assign pri26 = ch26_csr[15:13];
273 
assign pri27 = ch27_csr[15:13];
274 
assign pri28 = ch28_csr[15:13];
275 
assign pri29 = ch29_csr[15:13];
276 
assign pri30 = ch30_csr[15:13];
277 
`else
278 8 rudi 
`ifdef WDMA_PRI_4
279 5 rudi 
assign pri0 = {1'b0, ch0_csr[14:13]};
280 
assign pri1 = {1'b0, ch1_csr[14:13]};
281 
assign pri2 = {1'b0, ch2_csr[14:13]};
282 
assign pri3 = {1'b0, ch3_csr[14:13]};
283 
assign pri4 = {1'b0, ch4_csr[14:13]};
284 
assign pri5 = {1'b0, ch5_csr[14:13]};
285 
assign pri6 = {1'b0, ch6_csr[14:13]};
286 
assign pri7 = {1'b0, ch7_csr[14:13]};
287 
assign pri8 = {1'b0, ch8_csr[14:13]};
288 
assign pri9 = {1'b0, ch9_csr[14:13]};
289 
assign pri10 = {1'b0, ch10_csr[14:13]};
290 
assign pri11 = {1'b0, ch11_csr[14:13]};
291 
assign pri12 = {1'b0, ch12_csr[14:13]};
292 
assign pri13 = {1'b0, ch13_csr[14:13]};
293 
assign pri14 = {1'b0, ch14_csr[14:13]};
294 
assign pri15 = {1'b0, ch15_csr[14:13]};
295 
assign pri16 = {1'b0, ch16_csr[14:13]};
296 
assign pri17 = {1'b0, ch17_csr[14:13]};
297 
assign pri18 = {1'b0, ch18_csr[14:13]};
298 
assign pri19 = {1'b0, ch19_csr[14:13]};
299 
assign pri20 = {1'b0, ch20_csr[14:13]};
300 
assign pri21 = {1'b0, ch21_csr[14:13]};
301 
assign pri22 = {1'b0, ch22_csr[14:13]};
302 
assign pri23 = {1'b0, ch23_csr[14:13]};
303 
assign pri24 = {1'b0, ch24_csr[14:13]};
304 
assign pri25 = {1'b0, ch25_csr[14:13]};
305 
assign pri26 = {1'b0, ch26_csr[14:13]};
306 
assign pri27 = {1'b0, ch27_csr[14:13]};
307 
assign pri28 = {1'b0, ch28_csr[14:13]};
308 
assign pri29 = {1'b0, ch29_csr[14:13]};
309 
assign pri30 = {1'b0, ch30_csr[14:13]};
310 
`else
311 
assign pri0 = {2'b0, ch0_csr[13]};
312 
assign pri1 = {2'b0, ch1_csr[13]};
313 
assign pri2 = {2'b0, ch2_csr[13]};
314 
assign pri3 = {2'b0, ch3_csr[13]};
315 
assign pri4 = {2'b0, ch4_csr[13]};
316 
assign pri5 = {2'b0, ch5_csr[13]};
317 
assign pri6 = {2'b0, ch6_csr[13]};
318 
assign pri7 = {2'b0, ch7_csr[13]};
319 
assign pri8 = {2'b0, ch8_csr[13]};
320 
assign pri9 = {2'b0, ch9_csr[13]};
321 
assign pri10 = {2'b0, ch10_csr[13]};
322 
assign pri11 = {2'b0, ch11_csr[13]};
323 
assign pri12 = {2'b0, ch12_csr[13]};
324 
assign pri13 = {2'b0, ch13_csr[13]};
325 
assign pri14 = {2'b0, ch14_csr[13]};
326 
assign pri15 = {2'b0, ch15_csr[13]};
327 
assign pri16 = {2'b0, ch16_csr[13]};
328 
assign pri17 = {2'b0, ch17_csr[13]};
329 
assign pri18 = {2'b0, ch18_csr[13]};
330 
assign pri19 = {2'b0, ch19_csr[13]};
331 
assign pri20 = {2'b0, ch20_csr[13]};
332 
assign pri21 = {2'b0, ch21_csr[13]};
333 
assign pri22 = {2'b0, ch22_csr[13]};
334 
assign pri23 = {2'b0, ch23_csr[13]};
335 
assign pri24 = {2'b0, ch24_csr[13]};
336 
assign pri25 = {2'b0, ch25_csr[13]};
337 
assign pri26 = {2'b0, ch26_csr[13]};
338 
assign pri27 = {2'b0, ch27_csr[13]};
339 
assign pri28 = {2'b0, ch28_csr[13]};
340 
assign pri29 = {2'b0, ch29_csr[13]};
341 
assign pri30 = {2'b0, ch30_csr[13]};
342 
`endif
343 
`endif
344 
 
345 
////////////////////////////////////////////////////////////////////
346 
//
347 
// Misc logic
348 
//
349 
 
350 
// Chanel Valid flag
351 
// The valid flag is asserted when the channel is enabled,
352 
// and is either in "normal mode" (software control) or
353 
// "hw handshake mode" (reqN control)
354 
// validN = ch_enabled & (sw_mode | (hw_mode & reqN) )
355 
 
356 
always @(posedge clk)
357 
        req_r <= #1 req_i & ~ack_o;
358 
 
359 8 rudi 
assign valid[0] = ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1);
360 
assign valid[1] = ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1);
361 
assign valid[2] = ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1);
362 
assign valid[3] = ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1);
363 
assign valid[4] = ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1);
364 
assign valid[5] = ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1);
365 
assign valid[6] = ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1);
366 
assign valid[7] = ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1);
367 
assign valid[8] = ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1);
368 
assign valid[9] = ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1);
369 
assign valid[10] = ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1);
370 
assign valid[11] = ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1);
371 
assign valid[12] = ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1);
372 
assign valid[13] = ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1);
373 
assign valid[14] = ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1);
374 
assign valid[15] = ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1);
375 
assign valid[16] = ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1);
376 
assign valid[17] = ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1);
377 
assign valid[18] = ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1);
378 
assign valid[19] = ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1);
379 
assign valid[20] = ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1);
380 
assign valid[21] = ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1);
381 
assign valid[22] = ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1);
382 
assign valid[23] = ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1);
383 
assign valid[24] = ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1);
384 
assign valid[25] = ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1);
385 
assign valid[26] = ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1);
386 
assign valid[27] = ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1);
387 
assign valid[28] = ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1);
388 
assign valid[29] = ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1);
389 
assign valid[30] = ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1);
390 5 rudi 
 
391 
always @(posedge clk)
392 
        ndr_r <= #1 nd_i & req_i;
393 
 
394 
always @(posedge clk)
395 
        ndnr <= #1 nd_i & ~req_i;
396 
 
397 
// Start Signal for DMA engine
398 
assign de_start = (valid_sel & !de_start_r ) | next_start;
399 
 
400 
always @(posedge clk)
401 
        de_start_r <= #1 valid_sel;
402 
 
403 
always @(posedge clk)
404 
        next_start <= #1 next_ch & valid_sel;
405 
 
406 
// Ack outputs for HW handshake mode
407 
always @(posedge clk)
408 8 rudi 
        ack_o[0] <= #1 (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack;
409 5 rudi 
 
410 
always @(posedge clk)
411 8 rudi 
        ack_o[1] <= #1 (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack;
412 5 rudi 
 
413 
always @(posedge clk)
414 8 rudi 
        ack_o[2] <= #1 (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack;
415 5 rudi 
 
416 
always @(posedge clk)
417 8 rudi 
        ack_o[3] <= #1 (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack;
418 5 rudi 
 
419 
always @(posedge clk)
420 8 rudi 
        ack_o[4] <= #1 (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack;
421 5 rudi 
 
422 
always @(posedge clk)
423 8 rudi 
        ack_o[5] <= #1 (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack;
424 5 rudi 
 
425 
always @(posedge clk)
426 8 rudi 
        ack_o[6] <= #1 (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack;
427 5 rudi 
 
428 
always @(posedge clk)
429 8 rudi 
        ack_o[7] <= #1 (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack;
430 5 rudi 
 
431 
always @(posedge clk)
432 8 rudi 
        ack_o[8] <= #1 (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack;
433 5 rudi 
 
434 
always @(posedge clk)
435 8 rudi 
        ack_o[9] <= #1 (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack;
436 5 rudi 
 
437 
always @(posedge clk)
438 8 rudi 
        ack_o[10] <= #1 (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack;
439 5 rudi 
 
440 
always @(posedge clk)
441 8 rudi 
        ack_o[11] <= #1 (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack;
442 5 rudi 
 
443 
always @(posedge clk)
444 8 rudi 
        ack_o[12] <= #1 (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack;
445 5 rudi 
 
446 
always @(posedge clk)
447 8 rudi 
        ack_o[13] <= #1 (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack;
448 5 rudi 
 
449 
always @(posedge clk)
450 8 rudi 
        ack_o[14] <= #1 (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack;
451 5 rudi 
 
452 
always @(posedge clk)
453 8 rudi 
        ack_o[15] <= #1 (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack;
454 5 rudi 
 
455 
always @(posedge clk)
456 8 rudi 
        ack_o[16] <= #1 (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack;
457 5 rudi 
 
458 
always @(posedge clk)
459 8 rudi 
        ack_o[17] <= #1 (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack;
460 5 rudi 
 
461 
always @(posedge clk)
462 8 rudi 
        ack_o[18] <= #1 (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack;
463 5 rudi 
 
464 
always @(posedge clk)
465 8 rudi 
        ack_o[19] <= #1 (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack;
466 5 rudi 
 
467 
always @(posedge clk)
468 8 rudi 
        ack_o[20] <= #1 (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack;
469 5 rudi 
 
470 
always @(posedge clk)
471 8 rudi 
        ack_o[21] <= #1 (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack;
472 5 rudi 
 
473 
always @(posedge clk)
474 8 rudi 
        ack_o[22] <= #1 (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack;
475 5 rudi 
 
476 
always @(posedge clk)
477 8 rudi 
        ack_o[23] <= #1 (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack;
478 5 rudi 
 
479 
always @(posedge clk)
480 8 rudi 
        ack_o[24] <= #1 (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack;
481 5 rudi 
 
482 
always @(posedge clk)
483 8 rudi 
        ack_o[25] <= #1 (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack;
484 5 rudi 
 
485 
always @(posedge clk)
486 8 rudi 
        ack_o[26] <= #1 (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack;
487 5 rudi 
 
488 
always @(posedge clk)
489 8 rudi 
        ack_o[27] <= #1 (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack;
490 5 rudi 
 
491 
always @(posedge clk)
492 8 rudi 
        ack_o[28] <= #1 (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack;
493 5 rudi 
 
494 
always @(posedge clk)
495 8 rudi 
        ack_o[29] <= #1 (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack;
496 5 rudi 
 
497 
always @(posedge clk)
498 8 rudi 
        ack_o[30] <= #1 (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack;
499 5 rudi 
 
500 
// Channel Select
501 
always @(posedge clk or negedge rst)
502 
        if(!rst)        ch_sel_r <= #1 0;
503 
        else
504 
        if(de_start)    ch_sel_r <= #1 ch_sel_d;
505 
 
506 
assign ch_sel = !dma_busy ? ch_sel_d : ch_sel_r;
507 
 
508 
////////////////////////////////////////////////////////////////////
509 
//
510 
// Select Registers based on arbiter (and priority) outputs
511 
//
512 
 
513 
always @(ch_sel or valid)
514 
        case(ch_sel)            // synopsys parallel_case full_case
515 
           5'h0:        valid_sel = valid[0];
516 
           5'h1:        valid_sel = valid[1];
517 
           5'h2:        valid_sel = valid[2];
518 
           5'h3:        valid_sel = valid[3];
519 
           5'h4:        valid_sel = valid[4];
520 
           5'h5:        valid_sel = valid[5];
521 
           5'h6:        valid_sel = valid[6];
522 
           5'h7:        valid_sel = valid[7];
523 
           5'h8:        valid_sel = valid[8];
524 
           5'h9:        valid_sel = valid[9];
525 
           5'ha:        valid_sel = valid[10];
526 
           5'hb:        valid_sel = valid[11];
527 
           5'hc:        valid_sel = valid[12];
528 
           5'hd:        valid_sel = valid[13];
529 
           5'he:        valid_sel = valid[14];
530 
           5'hf:        valid_sel = valid[15];
531 
           5'h10:       valid_sel = valid[16];
532 
           5'h11:       valid_sel = valid[17];
533 
           5'h12:       valid_sel = valid[18];
534 
           5'h13:       valid_sel = valid[19];
535 
           5'h14:       valid_sel = valid[20];
536 
           5'h15:       valid_sel = valid[21];
537 
           5'h16:       valid_sel = valid[22];
538 
           5'h17:       valid_sel = valid[23];
539 
           5'h18:       valid_sel = valid[24];
540 
           5'h19:       valid_sel = valid[25];
541 
           5'h1a:       valid_sel = valid[26];
542 
           5'h1b:       valid_sel = valid[27];
543 
           5'h1c:       valid_sel = valid[28];
544 
           5'h1d:       valid_sel = valid[29];
545 
           5'h1e:       valid_sel = valid[30];
546 
        endcase
547 
 
548 
always @(ch_sel or ndr_r)
549 
        case(ch_sel)            // synopsys parallel_case full_case
550 
           5'h0:        ndr = ndr_r[0];
551 
           5'h1:        ndr = ndr_r[1];
552 
           5'h2:        ndr = ndr_r[2];
553 
           5'h3:        ndr = ndr_r[3];
554 
           5'h4:        ndr = ndr_r[4];
555 
           5'h5:        ndr = ndr_r[5];
556 
           5'h6:        ndr = ndr_r[6];
557 
           5'h7:        ndr = ndr_r[7];
558 
           5'h8:        ndr = ndr_r[8];
559 
           5'h9:        ndr = ndr_r[9];
560 
           5'ha:        ndr = ndr_r[10];
561 
           5'hb:        ndr = ndr_r[11];
562 
           5'hc:        ndr = ndr_r[12];
563 
           5'hd:        ndr = ndr_r[13];
564 
           5'he:        ndr = ndr_r[14];
565 
           5'hf:        ndr = ndr_r[15];
566 
           5'h10:       ndr = ndr_r[16];
567 
           5'h11:       ndr = ndr_r[17];
568 
           5'h12:       ndr = ndr_r[18];
569 
           5'h13:       ndr = ndr_r[19];
570 
           5'h14:       ndr = ndr_r[20];
571 
           5'h15:       ndr = ndr_r[21];
572 
           5'h16:       ndr = ndr_r[22];
573 
           5'h17:       ndr = ndr_r[23];
574 
           5'h18:       ndr = ndr_r[24];
575 
           5'h19:       ndr = ndr_r[25];
576 
           5'h1a:       ndr = ndr_r[26];
577 
           5'h1b:       ndr = ndr_r[27];
578 
           5'h1c:       ndr = ndr_r[28];
579 
           5'h1d:       ndr = ndr_r[29];
580 
           5'h1e:       ndr = ndr_r[30];
581 
        endcase
582 
 
583 
always @(ch_sel or pointer0 or pointer1 or pointer2 or pointer3 or pointer4
584 
                or pointer5 or pointer6 or pointer7 or pointer8 or pointer9
585 
                or pointer10 or pointer11 or pointer12 or pointer13 or pointer14
586 
                or pointer15 or pointer16 or pointer17 or pointer18 or pointer19
587 
                or pointer20 or pointer21 or pointer22 or pointer23 or pointer24
588 
                or pointer25 or pointer26 or pointer27 or pointer28 or pointer29
589 
                or pointer30 )
590 
        case(ch_sel)            // synopsys parallel_case full_case
591 
           5'h0:        pointer = pointer0;
592 
           5'h1:        pointer = pointer1;
593 
           5'h2:        pointer = pointer2;
594 
           5'h3:        pointer = pointer3;
595 
           5'h4:        pointer = pointer4;
596 
           5'h5:        pointer = pointer5;
597 
           5'h6:        pointer = pointer6;
598 
           5'h7:        pointer = pointer7;
599 
           5'h8:        pointer = pointer8;
600 
           5'h9:        pointer = pointer9;
601 
           5'ha:        pointer = pointer10;
602 
           5'hb:        pointer = pointer11;
603 
           5'hc:        pointer = pointer12;
604 
           5'hd:        pointer = pointer13;
605 
           5'he:        pointer = pointer14;
606 
           5'hf:        pointer = pointer15;
607 
           5'h10:       pointer = pointer16;
608 
           5'h11:       pointer = pointer17;
609 
           5'h12:       pointer = pointer18;
610 
           5'h13:       pointer = pointer19;
611 
           5'h14:       pointer = pointer20;
612 
           5'h15:       pointer = pointer21;
613 
           5'h16:       pointer = pointer22;
614 
           5'h17:       pointer = pointer23;
615 
           5'h18:       pointer = pointer24;
616 
           5'h19:       pointer = pointer25;
617 
           5'h1a:       pointer = pointer26;
618 
           5'h1b:       pointer = pointer27;
619 
           5'h1c:       pointer = pointer28;
620 
           5'h1d:       pointer = pointer29;
621 
           5'h1e:       pointer = pointer30;
622 
        endcase
623 
 
624 
always @(ch_sel or pointer0_s or pointer1_s or pointer2_s or pointer3_s or pointer4_s
625 
                or pointer5_s or pointer6_s or pointer7_s or pointer8_s or pointer9_s
626 
                or pointer10_s or pointer11_s or pointer12_s or pointer13_s or pointer14_s
627 
                or pointer15_s or pointer16_s or pointer17_s or pointer18_s or pointer19_s
628 
                or pointer20_s or pointer21_s or pointer22_s or pointer23_s or pointer24_s
629 
                or pointer25_s or pointer26_s or pointer27_s or pointer28_s or pointer29_s
630 
                or pointer30_s )
631 
        case(ch_sel)            // synopsys parallel_case full_case
632 
           5'h0:        pointer_s = pointer0_s;
633 
           5'h1:        pointer_s = pointer1_s;
634 
           5'h2:        pointer_s = pointer2_s;
635 
           5'h3:        pointer_s = pointer3_s;
636 
           5'h4:        pointer_s = pointer4_s;
637 
           5'h5:        pointer_s = pointer5_s;
638 
           5'h6:        pointer_s = pointer6_s;
639 
           5'h7:        pointer_s = pointer7_s;
640 
           5'h8:        pointer_s = pointer8_s;
641 
           5'h9:        pointer_s = pointer9_s;
642 
           5'ha:        pointer_s = pointer10_s;
643 
           5'hb:        pointer_s = pointer11_s;
644 
           5'hc:        pointer_s = pointer12_s;
645 
           5'hd:        pointer_s = pointer13_s;
646 
           5'he:        pointer_s = pointer14_s;
647 
           5'hf:        pointer_s = pointer15_s;
648 
           5'h10:       pointer_s = pointer16_s;
649 
           5'h11:       pointer_s = pointer17_s;
650 
           5'h12:       pointer_s = pointer18_s;
651 
           5'h13:       pointer_s = pointer19_s;
652 
           5'h14:       pointer_s = pointer20_s;
653 
           5'h15:       pointer_s = pointer21_s;
654 
           5'h16:       pointer_s = pointer22_s;
655 
           5'h17:       pointer_s = pointer23_s;
656 
           5'h18:       pointer_s = pointer24_s;
657 
           5'h19:       pointer_s = pointer25_s;
658 
           5'h1a:       pointer_s = pointer26_s;
659 
           5'h1b:       pointer_s = pointer27_s;
660 
           5'h1c:       pointer_s = pointer28_s;
661 
           5'h1d:       pointer_s = pointer29_s;
662 
           5'h1e:       pointer_s = pointer30_s;
663 
        endcase
664 
 
665 
always @(ch_sel or ch0_csr or ch1_csr or ch2_csr or ch3_csr or ch4_csr
666 
                or ch5_csr or ch6_csr or ch7_csr or ch8_csr or ch9_csr
667 
                or ch10_csr or ch11_csr or ch12_csr or ch13_csr or ch14_csr
668 
                or ch15_csr or ch16_csr or ch17_csr or ch18_csr or ch19_csr
669 
                or ch20_csr or ch21_csr or ch22_csr or ch23_csr or ch24_csr
670 
                or ch25_csr or ch26_csr or ch27_csr or ch28_csr or ch29_csr
671 
                or ch30_csr )
672 
        case(ch_sel)            // synopsys parallel_case full_case
673 
           5'h0:        csr = ch0_csr;
674 
           5'h1:        csr = ch1_csr;
675 
           5'h2:        csr = ch2_csr;
676 
           5'h3:        csr = ch3_csr;
677 
           5'h4:        csr = ch4_csr;
678 
           5'h5:        csr = ch5_csr;
679 
           5'h6:        csr = ch6_csr;
680 
           5'h7:        csr = ch7_csr;
681 
           5'h8:        csr = ch8_csr;
682 
           5'h9:        csr = ch9_csr;
683 
           5'ha:        csr = ch10_csr;
684 
           5'hb:        csr = ch11_csr;
685 
           5'hc:        csr = ch12_csr;
686 
           5'hd:        csr = ch13_csr;
687 
           5'he:        csr = ch14_csr;
688 
           5'hf:        csr = ch15_csr;
689 
           5'h10:       csr = ch16_csr;
690 
           5'h11:       csr = ch17_csr;
691 
           5'h12:       csr = ch18_csr;
692 
           5'h13:       csr = ch19_csr;
693 
           5'h14:       csr = ch20_csr;
694 
           5'h15:       csr = ch21_csr;
695 
           5'h16:       csr = ch22_csr;
696 
           5'h17:       csr = ch23_csr;
697 
           5'h18:       csr = ch24_csr;
698 
           5'h19:       csr = ch25_csr;
699 
           5'h1a:       csr = ch26_csr;
700 
           5'h1b:       csr = ch27_csr;
701 
           5'h1c:       csr = ch28_csr;
702 
           5'h1d:       csr = ch29_csr;
703 
           5'h1e:       csr = ch30_csr;
704 
        endcase
705 
 
706 
always @(ch_sel or ch0_txsz or ch1_txsz or ch2_txsz or ch3_txsz or ch4_txsz
707 
                or ch5_txsz or ch6_txsz or ch7_txsz or ch8_txsz or ch9_txsz
708 
                or ch10_txsz or ch11_txsz or ch12_txsz or ch13_txsz or ch14_txsz
709 
                or ch15_txsz or ch16_txsz or ch17_txsz or ch18_txsz or ch19_txsz
710 
                or ch20_txsz or ch21_txsz or ch22_txsz or ch23_txsz or ch24_txsz
711 
                or ch25_txsz or ch26_txsz or ch27_txsz or ch28_txsz or ch29_txsz
712 
                or ch30_txsz )
713 
        case(ch_sel)            // synopsys parallel_case full_case
714 
           5'h0:        txsz = ch0_txsz;
715 
           5'h1:        txsz = ch1_txsz;
716 
           5'h2:        txsz = ch2_txsz;
717 
           5'h3:        txsz = ch3_txsz;
718 
           5'h4:        txsz = ch4_txsz;
719 
           5'h5:        txsz = ch5_txsz;
720 
           5'h6:        txsz = ch6_txsz;
721 
           5'h7:        txsz = ch7_txsz;
722 
           5'h8:        txsz = ch8_txsz;
723 
           5'h9:        txsz = ch9_txsz;
724 
           5'ha:        txsz = ch10_txsz;
725 
           5'hb:        txsz = ch11_txsz;
726 
           5'hc:        txsz = ch12_txsz;
727 
           5'hd:        txsz = ch13_txsz;
728 
           5'he:        txsz = ch14_txsz;
729 
           5'hf:        txsz = ch15_txsz;
730 
           5'h10:       txsz = ch16_txsz;
731 
           5'h11:       txsz = ch17_txsz;
732 
           5'h12:       txsz = ch18_txsz;
733 
           5'h13:       txsz = ch19_txsz;
734 
           5'h14:       txsz = ch20_txsz;
735 
           5'h15:       txsz = ch21_txsz;
736 
           5'h16:       txsz = ch22_txsz;
737 
           5'h17:       txsz = ch23_txsz;
738 
           5'h18:       txsz = ch24_txsz;
739 
           5'h19:       txsz = ch25_txsz;
740 
           5'h1a:       txsz = ch26_txsz;
741 
           5'h1b:       txsz = ch27_txsz;
742 
           5'h1c:       txsz = ch28_txsz;
743 
           5'h1d:       txsz = ch29_txsz;
744 
           5'h1e:       txsz = ch30_txsz;
745 
        endcase
746 
 
747 
always @(ch_sel or ch0_adr0 or ch1_adr0 or ch2_adr0 or ch3_adr0 or ch4_adr0
748 
                or ch5_adr0 or ch6_adr0 or ch7_adr0 or ch8_adr0 or ch9_adr0
749 
                or ch10_adr0 or ch11_adr0 or ch12_adr0 or ch13_adr0 or ch14_adr0
750 
                or ch15_adr0 or ch16_adr0 or ch17_adr0 or ch18_adr0 or ch19_adr0
751 
                or ch20_adr0 or ch21_adr0 or ch22_adr0 or ch23_adr0 or ch24_adr0
752 
                or ch25_adr0 or ch26_adr0 or ch27_adr0 or ch28_adr0 or ch29_adr0
753 
                or ch30_adr0 )
754 
        case(ch_sel)            // synopsys parallel_case full_case
755 
           5'h0:        adr0 = ch0_adr0;
756 
           5'h1:        adr0 = ch1_adr0;
757 
           5'h2:        adr0 = ch2_adr0;
758 
           5'h3:        adr0 = ch3_adr0;
759 
           5'h4:        adr0 = ch4_adr0;
760 
           5'h5:        adr0 = ch5_adr0;
761 
           5'h6:        adr0 = ch6_adr0;
762 
           5'h7:        adr0 = ch7_adr0;
763 
           5'h8:        adr0 = ch8_adr0;
764 
           5'h9:        adr0 = ch9_adr0;
765 
           5'ha:        adr0 = ch10_adr0;
766 
           5'hb:        adr0 = ch11_adr0;
767 
           5'hc:        adr0 = ch12_adr0;
768 
           5'hd:        adr0 = ch13_adr0;
769 
           5'he:        adr0 = ch14_adr0;
770 
           5'hf:        adr0 = ch15_adr0;
771 
           5'h10:       adr0 = ch16_adr0;
772 
           5'h11:       adr0 = ch17_adr0;
773 
           5'h12:       adr0 = ch18_adr0;
774 
           5'h13:       adr0 = ch19_adr0;
775 
           5'h14:       adr0 = ch20_adr0;
776 
           5'h15:       adr0 = ch21_adr0;
777 
           5'h16:       adr0 = ch22_adr0;
778 
           5'h17:       adr0 = ch23_adr0;
779 
           5'h18:       adr0 = ch24_adr0;
780 
           5'h19:       adr0 = ch25_adr0;
781 
           5'h1a:       adr0 = ch26_adr0;
782 
           5'h1b:       adr0 = ch27_adr0;
783 
           5'h1c:       adr0 = ch28_adr0;
784 
           5'h1d:       adr0 = ch29_adr0;
785 
           5'h1e:       adr0 = ch30_adr0;
786 
        endcase
787 
 
788 
always @(ch_sel or ch0_adr1 or ch1_adr1 or ch2_adr1 or ch3_adr1 or ch4_adr1
789 
                or ch5_adr1 or ch6_adr1 or ch7_adr1 or ch8_adr1 or ch9_adr1
790 
                or ch10_adr1 or ch11_adr1 or ch12_adr1 or ch13_adr1 or ch14_adr1
791 
                or ch15_adr1 or ch16_adr1 or ch17_adr1 or ch18_adr1 or ch19_adr1
792 
                or ch20_adr1 or ch21_adr1 or ch22_adr1 or ch23_adr1 or ch24_adr1
793 
                or ch25_adr1 or ch26_adr1 or ch27_adr1 or ch28_adr1 or ch29_adr1
794 
                or ch30_adr1 )
795 
        case(ch_sel)            // synopsys parallel_case full_case
796 
           5'h0:        adr1 = ch0_adr1;
797 
           5'h1:        adr1 = ch1_adr1;
798 
           5'h2:        adr1 = ch2_adr1;
799 
           5'h3:        adr1 = ch3_adr1;
800 
           5'h4:        adr1 = ch4_adr1;
801 
           5'h5:        adr1 = ch5_adr1;
802 
           5'h6:        adr1 = ch6_adr1;
803 
           5'h7:        adr1 = ch7_adr1;
804 
           5'h8:        adr1 = ch8_adr1;
805 
           5'h9:        adr1 = ch9_adr1;
806 
           5'ha:        adr1 = ch10_adr1;
807 
           5'hb:        adr1 = ch11_adr1;
808 
           5'hc:        adr1 = ch12_adr1;
809 
           5'hd:        adr1 = ch13_adr1;
810 
           5'he:        adr1 = ch14_adr1;
811 
           5'hf:        adr1 = ch15_adr1;
812 
           5'h10:       adr1 = ch16_adr1;
813 
           5'h11:       adr1 = ch17_adr1;
814 
           5'h12:       adr1 = ch18_adr1;
815 
           5'h13:       adr1 = ch19_adr1;
816 
           5'h14:       adr1 = ch20_adr1;
817 
           5'h15:       adr1 = ch21_adr1;
818 
           5'h16:       adr1 = ch22_adr1;
819 
           5'h17:       adr1 = ch23_adr1;
820 
           5'h18:       adr1 = ch24_adr1;
821 
           5'h19:       adr1 = ch25_adr1;
822 
           5'h1a:       adr1 = ch26_adr1;
823 
           5'h1b:       adr1 = ch27_adr1;
824 
           5'h1c:       adr1 = ch28_adr1;
825 
           5'h1d:       adr1 = ch29_adr1;
826 
           5'h1e:       adr1 = ch30_adr1;
827 
        endcase
828 
 
829 
always @(ch_sel or ch0_am0 or ch1_am0 or ch2_am0 or ch3_am0 or ch4_am0
830 
                or ch5_am0 or ch6_am0 or ch7_am0 or ch8_am0 or ch9_am0
831 
                or ch10_am0 or ch11_am0 or ch12_am0 or ch13_am0 or ch14_am0
832 
                or ch15_am0 or ch16_am0 or ch17_am0 or ch18_am0 or ch19_am0
833 
                or ch20_am0 or ch21_am0 or ch22_am0 or ch23_am0 or ch24_am0
834 
                or ch25_am0 or ch26_am0 or ch27_am0 or ch28_am0 or ch29_am0
835 
                or ch30_am0 )
836 
        case(ch_sel)            // synopsys parallel_case full_case
837 
           5'h0:        am0 = ch0_am0;
838 
           5'h1:        am0 = ch1_am0;
839 
           5'h2:        am0 = ch2_am0;
840 
           5'h3:        am0 = ch3_am0;
841 
           5'h4:        am0 = ch4_am0;
842 
           5'h5:        am0 = ch5_am0;
843 
           5'h6:        am0 = ch6_am0;
844 
           5'h7:        am0 = ch7_am0;
845 
           5'h8:        am0 = ch8_am0;
846 
           5'h9:        am0 = ch9_am0;
847 
           5'ha:        am0 = ch10_am0;
848 
           5'hb:        am0 = ch11_am0;
849 
           5'hc:        am0 = ch12_am0;
850 
           5'hd:        am0 = ch13_am0;
851 
           5'he:        am0 = ch14_am0;
852 
           5'hf:        am0 = ch15_am0;
853 
           5'h10:       am0 = ch16_am0;
854 
           5'h11:       am0 = ch17_am0;
855 
           5'h12:       am0 = ch18_am0;
856 
           5'h13:       am0 = ch19_am0;
857 
           5'h14:       am0 = ch20_am0;
858 
           5'h15:       am0 = ch21_am0;
859 
           5'h16:       am0 = ch22_am0;
860 
           5'h17:       am0 = ch23_am0;
861 
           5'h18:       am0 = ch24_am0;
862 
           5'h19:       am0 = ch25_am0;
863 
           5'h1a:       am0 = ch26_am0;
864 
           5'h1b:       am0 = ch27_am0;
865 
           5'h1c:       am0 = ch28_am0;
866 
           5'h1d:       am0 = ch29_am0;
867 
           5'h1e:       am0 = ch30_am0;
868 
        endcase
869 
 
870 
always @(ch_sel or ch0_am1 or ch1_am1 or ch2_am1 or ch3_am1 or ch4_am1
871 
                or ch5_am1 or ch6_am1 or ch7_am1 or ch8_am1 or ch9_am1
872 
                or ch10_am1 or ch11_am1 or ch12_am1 or ch13_am1 or ch14_am1
873 
                or ch15_am1 or ch16_am1 or ch17_am1 or ch18_am1 or ch19_am1
874 
                or ch20_am1 or ch21_am1 or ch22_am1 or ch23_am1 or ch24_am1
875 
                or ch25_am1 or ch26_am1 or ch27_am1 or ch28_am1 or ch29_am1
876 
                or ch30_am1 )
877 
        case(ch_sel)            // synopsys parallel_case full_case
878 
           5'h0:        am1 = ch0_am1;
879 
           5'h1:        am1 = ch1_am1;
880 
           5'h2:        am1 = ch2_am1;
881 
           5'h3:        am1 = ch3_am1;
882 
           5'h4:        am1 = ch4_am1;
883 
           5'h5:        am1 = ch5_am1;
884 
           5'h6:        am1 = ch6_am1;
885 
           5'h7:        am1 = ch7_am1;
886 
           5'h8:        am1 = ch8_am1;
887 
           5'h9:        am1 = ch9_am1;
888 
           5'ha:        am1 = ch10_am1;
889 
           5'hb:        am1 = ch11_am1;
890 
           5'hc:        am1 = ch12_am1;
891 
           5'hd:        am1 = ch13_am1;
892 
           5'he:        am1 = ch14_am1;
893 
           5'hf:        am1 = ch15_am1;
894 
           5'h10:       am1 = ch16_am1;
895 
           5'h11:       am1 = ch17_am1;
896 
           5'h12:       am1 = ch18_am1;
897 
           5'h13:       am1 = ch19_am1;
898 
           5'h14:       am1 = ch20_am1;
899 
           5'h15:       am1 = ch21_am1;
900 
           5'h16:       am1 = ch22_am1;
901 
           5'h17:       am1 = ch23_am1;
902 
           5'h18:       am1 = ch24_am1;
903 
           5'h19:       am1 = ch25_am1;
904 
           5'h1a:       am1 = ch26_am1;
905 
           5'h1b:       am1 = ch27_am1;
906 
           5'h1c:       am1 = ch28_am1;
907 
           5'h1d:       am1 = ch29_am1;
908 
           5'h1e:       am1 = ch30_am1;
909 
        endcase
910 
 
911 
////////////////////////////////////////////////////////////////////
912 
//
913 
// Actual Chanel Arbiter and Priority Encoder
914 
//
915 
 
916 
// Select the arbiter for current highest priority
917 
always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3 or gnt_p4
918 
                or gnt_p5 or gnt_p6 or gnt_p7 )
919 
        case(pri_out)           // synopsys parallel_case full_case
920 
           3'h0:        ch_sel_d = gnt_p0;
921 
           3'h1:        ch_sel_d = gnt_p1;
922 
           3'h2:        ch_sel_d = gnt_p2;
923 
           3'h3:        ch_sel_d = gnt_p3;
924 
           3'h4:        ch_sel_d = gnt_p4;
925 
           3'h5:        ch_sel_d = gnt_p5;
926 
           3'h6:        ch_sel_d = gnt_p6;
927 
           3'h7:        ch_sel_d = gnt_p7;
928 
        endcase
929 
 
930 
 
931 
// Priority Encoder
932 
wb_dma_ch_pri_enc       u0(
933 
                .clk(           clk             ),
934 
                .valid(         valid           ),
935 
                .pri0(          pri0            ),
936 
                .pri1(          pri1            ),
937 
                .pri2(          pri2            ),
938 
                .pri3(          pri3            ),
939 
                .pri4(          pri4            ),
940 
                .pri5(          pri5            ),
941 
                .pri6(          pri6            ),
942 
                .pri7(          pri7            ),
943 
                .pri8(          pri8            ),
944 
                .pri9(          pri9            ),
945 
                .pri10(         pri10           ),
946 
                .pri11(         pri11           ),
947 
                .pri12(         pri12           ),
948 
                .pri13(         pri13           ),
949 
                .pri14(         pri14           ),
950 
                .pri15(         pri15           ),
951 
                .pri16(         pri16           ),
952 
                .pri17(         pri17           ),
953 
                .pri18(         pri18           ),
954 
                .pri19(         pri19           ),
955 
                .pri20(         pri20           ),
956 
                .pri21(         pri21           ),
957 
                .pri22(         pri22           ),
958 
                .pri23(         pri23           ),
959 
                .pri24(         pri24           ),
960 
                .pri25(         pri25           ),
961 
                .pri26(         pri26           ),
962 
                .pri27(         pri27           ),
963 
                .pri28(         pri28           ),
964 
                .pri29(         pri29           ),
965 
                .pri30(         pri30           ),
966 
                .pri_out(       pri_out         )
967 
                );
968 
 
969 
// Arbiter request lines
970 
// Generate request depending on priority and valid bits
971 
 
972 
assign req_p0[0] = valid[0] & (pri0==3'h0);
973 
assign req_p0[1] = valid[1] & (pri1==3'h0);
974 
assign req_p0[2] = valid[2] & (pri2==3'h0);
975 
assign req_p0[3] = valid[3] & (pri3==3'h0);
976 
assign req_p0[4] = valid[4] & (pri4==3'h0);
977 
assign req_p0[5] = valid[5] & (pri5==3'h0);
978 
assign req_p0[6] = valid[6] & (pri6==3'h0);
979 
assign req_p0[7] = valid[7] & (pri7==3'h0);
980 
assign req_p0[8] = valid[8] & (pri8==3'h0);
981 
assign req_p0[9] = valid[9] & (pri9==3'h0);
982 
assign req_p0[10] = valid[10] & (pri10==3'h0);
983 
assign req_p0[11] = valid[11] & (pri11==3'h0);
984 
assign req_p0[12] = valid[12] & (pri12==3'h0);
985 
assign req_p0[13] = valid[13] & (pri13==3'h0);
986 
assign req_p0[14] = valid[14] & (pri14==3'h0);
987 
assign req_p0[15] = valid[15] & (pri15==3'h0);
988 
assign req_p0[16] = valid[16] & (pri16==3'h0);
989 
assign req_p0[17] = valid[17] & (pri17==3'h0);
990 
assign req_p0[18] = valid[18] & (pri18==3'h0);
991 
assign req_p0[19] = valid[19] & (pri19==3'h0);
992 
assign req_p0[20] = valid[20] & (pri20==3'h0);
993 
assign req_p0[21] = valid[21] & (pri21==3'h0);
994 
assign req_p0[22] = valid[22] & (pri22==3'h0);
995 
assign req_p0[23] = valid[23] & (pri23==3'h0);
996 
assign req_p0[24] = valid[24] & (pri24==3'h0);
997 
assign req_p0[25] = valid[25] & (pri25==3'h0);
998 
assign req_p0[26] = valid[26] & (pri26==3'h0);
999 
assign req_p0[27] = valid[27] & (pri27==3'h0);
1000 
assign req_p0[28] = valid[28] & (pri28==3'h0);
1001 
assign req_p0[29] = valid[29] & (pri29==3'h0);
1002 
assign req_p0[30] = valid[30] & (pri30==3'h0);
1003 
 
1004 
assign req_p1[0] = valid[0] & (pri0==3'h1);
1005 
assign req_p1[1] = valid[1] & (pri1==3'h1);
1006 
assign req_p1[2] = valid[2] & (pri2==3'h1);
1007 
assign req_p1[3] = valid[3] & (pri3==3'h1);
1008 
assign req_p1[4] = valid[4] & (pri4==3'h1);
1009 
assign req_p1[5] = valid[5] & (pri5==3'h1);
1010 
assign req_p1[6] = valid[6] & (pri6==3'h1);
1011 
assign req_p1[7] = valid[7] & (pri7==3'h1);
1012 
assign req_p1[8] = valid[8] & (pri8==3'h1);
1013 
assign req_p1[9] = valid[9] & (pri9==3'h1);
1014 
assign req_p1[10] = valid[10] & (pri10==3'h1);
1015 
assign req_p1[11] = valid[11] & (pri11==3'h1);
1016 
assign req_p1[12] = valid[12] & (pri12==3'h1);
1017 
assign req_p1[13] = valid[13] & (pri13==3'h1);
1018 
assign req_p1[14] = valid[14] & (pri14==3'h1);
1019 
assign req_p1[15] = valid[15] & (pri15==3'h1);
1020 
assign req_p1[16] = valid[16] & (pri16==3'h1);
1021 
assign req_p1[17] = valid[17] & (pri17==3'h1);
1022 
assign req_p1[18] = valid[18] & (pri18==3'h1);
1023 
assign req_p1[19] = valid[19] & (pri19==3'h1);
1024 
assign req_p1[20] = valid[20] & (pri20==3'h1);
1025 
assign req_p1[21] = valid[21] & (pri21==3'h1);
1026 
assign req_p1[22] = valid[22] & (pri22==3'h1);
1027 
assign req_p1[23] = valid[23] & (pri23==3'h1);
1028 
assign req_p1[24] = valid[24] & (pri24==3'h1);
1029 
assign req_p1[25] = valid[25] & (pri25==3'h1);
1030 
assign req_p1[26] = valid[26] & (pri26==3'h1);
1031 
assign req_p1[27] = valid[27] & (pri27==3'h1);
1032 
assign req_p1[28] = valid[28] & (pri28==3'h1);
1033 
assign req_p1[29] = valid[29] & (pri29==3'h1);
1034 
assign req_p1[30] = valid[30] & (pri30==3'h1);
1035 
 
1036 
assign req_p2[0] = valid[0] & (pri0==3'h2);
1037 
assign req_p2[1] = valid[1] & (pri1==3'h2);
1038 
assign req_p2[2] = valid[2] & (pri2==3'h2);
1039 
assign req_p2[3] = valid[3] & (pri3==3'h2);
1040 
assign req_p2[4] = valid[4] & (pri4==3'h2);
1041 
assign req_p2[5] = valid[5] & (pri5==3'h2);
1042 
assign req_p2[6] = valid[6] & (pri6==3'h2);
1043 
assign req_p2[7] = valid[7] & (pri7==3'h2);
1044 
assign req_p2[8] = valid[8] & (pri8==3'h2);
1045 
assign req_p2[9] = valid[9] & (pri9==3'h2);
1046 
assign req_p2[10] = valid[10] & (pri10==3'h2);
1047 
assign req_p2[11] = valid[11] & (pri11==3'h2);
1048 
assign req_p2[12] = valid[12] & (pri12==3'h2);
1049 
assign req_p2[13] = valid[13] & (pri13==3'h2);
1050 
assign req_p2[14] = valid[14] & (pri14==3'h2);
1051 
assign req_p2[15] = valid[15] & (pri15==3'h2);
1052 
assign req_p2[16] = valid[16] & (pri16==3'h2);
1053 
assign req_p2[17] = valid[17] & (pri17==3'h2);
1054 
assign req_p2[18] = valid[18] & (pri18==3'h2);
1055 
assign req_p2[19] = valid[19] & (pri19==3'h2);
1056 
assign req_p2[20] = valid[20] & (pri20==3'h2);
1057 
assign req_p2[21] = valid[21] & (pri21==3'h2);
1058 
assign req_p2[22] = valid[22] & (pri22==3'h2);
1059 
assign req_p2[23] = valid[23] & (pri23==3'h2);
1060 
assign req_p2[24] = valid[24] & (pri24==3'h2);
1061 
assign req_p2[25] = valid[25] & (pri25==3'h2);
1062 
assign req_p2[26] = valid[26] & (pri26==3'h2);
1063 
assign req_p2[27] = valid[27] & (pri27==3'h2);
1064 
assign req_p2[28] = valid[28] & (pri28==3'h2);
1065 
assign req_p2[29] = valid[29] & (pri29==3'h2);
1066 
assign req_p2[30] = valid[30] & (pri30==3'h2);
1067 
 
1068 
assign req_p3[0] = valid[0] & (pri0==3'h3);
1069 
assign req_p3[1] = valid[1] & (pri1==3'h3);
1070 
assign req_p3[2] = valid[2] & (pri2==3'h3);
1071 
assign req_p3[3] = valid[3] & (pri3==3'h3);
1072 
assign req_p3[4] = valid[4] & (pri4==3'h3);
1073 
assign req_p3[5] = valid[5] & (pri5==3'h3);
1074 
assign req_p3[6] = valid[6] & (pri6==3'h3);
1075 
assign req_p3[7] = valid[7] & (pri7==3'h3);
1076 
assign req_p3[8] = valid[8] & (pri8==3'h3);
1077 
assign req_p3[9] = valid[9] & (pri9==3'h3);
1078 
assign req_p3[10] = valid[10] & (pri10==3'h3);
1079 
assign req_p3[11] = valid[11] & (pri11==3'h3);
1080 
assign req_p3[12] = valid[12] & (pri12==3'h3);
1081 
assign req_p3[13] = valid[13] & (pri13==3'h3);
1082 
assign req_p3[14] = valid[14] & (pri14==3'h3);
1083 
assign req_p3[15] = valid[15] & (pri15==3'h3);
1084 
assign req_p3[16] = valid[16] & (pri16==3'h3);
1085 
assign req_p3[17] = valid[17] & (pri17==3'h3);
1086 
assign req_p3[18] = valid[18] & (pri18==3'h3);
1087 
assign req_p3[19] = valid[19] & (pri19==3'h3);
1088 
assign req_p3[20] = valid[20] & (pri20==3'h3);
1089 
assign req_p3[21] = valid[21] & (pri21==3'h3);
1090 
assign req_p3[22] = valid[22] & (pri22==3'h3);
1091 
assign req_p3[23] = valid[23] & (pri23==3'h3);
1092 
assign req_p3[24] = valid[24] & (pri24==3'h3);
1093 
assign req_p3[25] = valid[25] & (pri25==3'h3);
1094 
assign req_p3[26] = valid[26] & (pri26==3'h3);
1095 
assign req_p3[27] = valid[27] & (pri27==3'h3);
1096 
assign req_p3[28] = valid[28] & (pri28==3'h3);
1097 
assign req_p3[29] = valid[29] & (pri29==3'h3);
1098 
assign req_p3[30] = valid[30] & (pri30==3'h3);
1099 
 
1100 
assign req_p4[0] = valid[0] & (pri0==3'h4);
1101 
assign req_p4[1] = valid[1] & (pri1==3'h4);
1102 
assign req_p4[2] = valid[2] & (pri2==3'h4);
1103 
assign req_p4[3] = valid[3] & (pri3==3'h4);
1104 
assign req_p4[4] = valid[4] & (pri4==3'h4);
1105 
assign req_p4[5] = valid[5] & (pri5==3'h4);
1106 
assign req_p4[6] = valid[6] & (pri6==3'h4);
1107 
assign req_p4[7] = valid[7] & (pri7==3'h4);
1108 
assign req_p4[8] = valid[8] & (pri8==3'h4);
1109 
assign req_p4[9] = valid[9] & (pri9==3'h4);
1110 
assign req_p4[10] = valid[10] & (pri10==3'h4);
1111 
assign req_p4[11] = valid[11] & (pri11==3'h4);
1112 
assign req_p4[12] = valid[12] & (pri12==3'h4);
1113 
assign req_p4[13] = valid[13] & (pri13==3'h4);
1114 
assign req_p4[14] = valid[14] & (pri14==3'h4);
1115 
assign req_p4[15] = valid[15] & (pri15==3'h4);
1116 
assign req_p4[16] = valid[16] & (pri16==3'h4);
1117 
assign req_p4[17] = valid[17] & (pri17==3'h4);
1118 
assign req_p4[18] = valid[18] & (pri18==3'h4);
1119 
assign req_p4[19] = valid[19] & (pri19==3'h4);
1120 
assign req_p4[20] = valid[20] & (pri20==3'h4);
1121 
assign req_p4[21] = valid[21] & (pri21==3'h4);
1122 
assign req_p4[22] = valid[22] & (pri22==3'h4);
1123 
assign req_p4[23] = valid[23] & (pri23==3'h4);
1124 
assign req_p4[24] = valid[24] & (pri24==3'h4);
1125 
assign req_p4[25] = valid[25] & (pri25==3'h4);
1126 
assign req_p4[26] = valid[26] & (pri26==3'h4);
1127 
assign req_p4[27] = valid[27] & (pri27==3'h4);
1128 
assign req_p4[28] = valid[28] & (pri28==3'h4);
1129 
assign req_p4[29] = valid[29] & (pri29==3'h4);
1130 
assign req_p4[30] = valid[30] & (pri30==3'h4);
1131 
 
1132 
assign req_p5[0] = valid[0] & (pri0==3'h5);
1133 
assign req_p5[1] = valid[1] & (pri1==3'h5);
1134 
assign req_p5[2] = valid[2] & (pri2==3'h5);
1135 
assign req_p5[3] = valid[3] & (pri3==3'h5);
1136 
assign req_p5[4] = valid[4] & (pri4==3'h5);
1137 
assign req_p5[5] = valid[5] & (pri5==3'h5);
1138 
assign req_p5[6] = valid[6] & (pri6==3'h5);
1139 
assign req_p5[7] = valid[7] & (pri7==3'h5);
1140 
assign req_p5[8] = valid[8] & (pri8==3'h5);
1141 
assign req_p5[9] = valid[9] & (pri9==3'h5);
1142 
assign req_p5[10] = valid[10] & (pri10==3'h5);
1143 
assign req_p5[11] = valid[11] & (pri11==3'h5);
1144 
assign req_p5[12] = valid[12] & (pri12==3'h5);
1145 
assign req_p5[13] = valid[13] & (pri13==3'h5);
1146 
assign req_p5[14] = valid[14] & (pri14==3'h5);
1147 
assign req_p5[15] = valid[15] & (pri15==3'h5);
1148 
assign req_p5[16] = valid[16] & (pri16==3'h5);
1149 
assign req_p5[17] = valid[17] & (pri17==3'h5);
1150 
assign req_p5[18] = valid[18] & (pri18==3'h5);
1151 
assign req_p5[19] = valid[19] & (pri19==3'h5);
1152 
assign req_p5[20] = valid[20] & (pri20==3'h5);
1153 
assign req_p5[21] = valid[21] & (pri21==3'h5);
1154 
assign req_p5[22] = valid[22] & (pri22==3'h5);
1155 
assign req_p5[23] = valid[23] & (pri23==3'h5);
1156 
assign req_p5[24] = valid[24] & (pri24==3'h5);
1157 
assign req_p5[25] = valid[25] & (pri25==3'h5);
1158 
assign req_p5[26] = valid[26] & (pri26==3'h5);
1159 
assign req_p5[27] = valid[27] & (pri27==3'h5);
1160 
assign req_p5[28] = valid[28] & (pri28==3'h5);
1161 
assign req_p5[29] = valid[29] & (pri29==3'h5);
1162 
assign req_p5[30] = valid[30] & (pri30==3'h5);
1163 
 
1164 
assign req_p6[0] = valid[0] & (pri0==3'h6);
1165 
assign req_p6[1] = valid[1] & (pri1==3'h6);
1166 
assign req_p6[2] = valid[2] & (pri2==3'h6);
1167 
assign req_p6[3] = valid[3] & (pri3==3'h6);
1168 
assign req_p6[4] = valid[4] & (pri4==3'h6);
1169 
assign req_p6[5] = valid[5] & (pri5==3'h6);
1170 
assign req_p6[6] = valid[6] & (pri6==3'h6);
1171 
assign req_p6[7] = valid[7] & (pri7==3'h6);
1172 
assign req_p6[8] = valid[8] & (pri8==3'h6);
1173 
assign req_p6[9] = valid[9] & (pri9==3'h6);
1174 
assign req_p6[10] = valid[10] & (pri10==3'h6);
1175 
assign req_p6[11] = valid[11] & (pri11==3'h6);
1176 
assign req_p6[12] = valid[12] & (pri12==3'h6);
1177 
assign req_p6[13] = valid[13] & (pri13==3'h6);
1178 
assign req_p6[14] = valid[14] & (pri14==3'h6);
1179 
assign req_p6[15] = valid[15] & (pri15==3'h6);
1180 
assign req_p6[16] = valid[16] & (pri16==3'h6);
1181 
assign req_p6[17] = valid[17] & (pri17==3'h6);
1182 
assign req_p6[18] = valid[18] & (pri18==3'h6);
1183 
assign req_p6[19] = valid[19] & (pri19==3'h6);
1184 
assign req_p6[20] = valid[20] & (pri20==3'h6);
1185 
assign req_p6[21] = valid[21] & (pri21==3'h6);
1186 
assign req_p6[22] = valid[22] & (pri22==3'h6);
1187 
assign req_p6[23] = valid[23] & (pri23==3'h6);
1188 
assign req_p6[24] = valid[24] & (pri24==3'h6);
1189 
assign req_p6[25] = valid[25] & (pri25==3'h6);
1190 
assign req_p6[26] = valid[26] & (pri26==3'h6);
1191 
assign req_p6[27] = valid[27] & (pri27==3'h6);
1192 
assign req_p6[28] = valid[28] & (pri28==3'h6);
1193 
assign req_p6[29] = valid[29] & (pri29==3'h6);
1194 
assign req_p6[30] = valid[30] & (pri30==3'h6);
1195 
 
1196 
assign req_p7[0] = valid[0] & (pri0==3'h7);
1197 
assign req_p7[1] = valid[1] & (pri1==3'h7);
1198 
assign req_p7[2] = valid[2] & (pri2==3'h7);
1199 
assign req_p7[3] = valid[3] & (pri3==3'h7);
1200 
assign req_p7[4] = valid[4] & (pri4==3'h7);
1201 
assign req_p7[5] = valid[5] & (pri5==3'h7);
1202 
assign req_p7[6] = valid[6] & (pri6==3'h7);
1203 
assign req_p7[7] = valid[7] & (pri7==3'h7);
1204 
assign req_p7[8] = valid[8] & (pri8==3'h7);
1205 
assign req_p7[9] = valid[9] & (pri9==3'h7);
1206 
assign req_p7[10] = valid[10] & (pri10==3'h7);
1207 
assign req_p7[11] = valid[11] & (pri11==3'h7);
1208 
assign req_p7[12] = valid[12] & (pri12==3'h7);
1209 
assign req_p7[13] = valid[13] & (pri13==3'h7);
1210 
assign req_p7[14] = valid[14] & (pri14==3'h7);
1211 
assign req_p7[15] = valid[15] & (pri15==3'h7);
1212 
assign req_p7[16] = valid[16] & (pri16==3'h7);
1213 
assign req_p7[17] = valid[17] & (pri17==3'h7);
1214 
assign req_p7[18] = valid[18] & (pri18==3'h7);
1215 
assign req_p7[19] = valid[19] & (pri19==3'h7);
1216 
assign req_p7[20] = valid[20] & (pri20==3'h7);
1217 
assign req_p7[21] = valid[21] & (pri21==3'h7);
1218 
assign req_p7[22] = valid[22] & (pri22==3'h7);
1219 
assign req_p7[23] = valid[23] & (pri23==3'h7);
1220 
assign req_p7[24] = valid[24] & (pri24==3'h7);
1221 
assign req_p7[25] = valid[25] & (pri25==3'h7);
1222 
assign req_p7[26] = valid[26] & (pri26==3'h7);
1223 
assign req_p7[27] = valid[27] & (pri27==3'h7);
1224 
assign req_p7[28] = valid[28] & (pri28==3'h7);
1225 
assign req_p7[29] = valid[29] & (pri29==3'h7);
1226 
assign req_p7[30] = valid[30] & (pri30==3'h7);
1227 
 
1228 
// RR Arbiter for priority 0
1229 
wb_dma_ch_arb u1(
1230 
        .clk(           clk             ),
1231 
        .rst(           rst             ),
1232 
        .req(           req_p0          ),
1233 
        .gnt(           gnt_p0          ),
1234 
        .advance(       next_ch         )
1235 
        );
1236 
// RR Arbiter for priority 1
1237 
wb_dma_ch_arb u2(
1238 
        .clk(           clk             ),
1239 
        .rst(           rst             ),
1240 
        .req(           req_p1          ),
1241 
        .gnt(           gnt_p1          ),
1242 
        .advance(       next_ch         )
1243 
        );
1244 
 
1245 8 rudi 
`ifdef WDMA_PRI_4
1246 5 rudi 
// RR Arbiter for priority 2
1247 
wb_dma_ch_arb u3(
1248 
        .clk(           clk             ),
1249 
        .rst(           rst             ),
1250 
        .req(           req_p2          ),
1251 
        .gnt(           gnt_p2          ),
1252 
        .advance(       next_ch         )
1253 
        );
1254 
// RR Arbiter for priority 3
1255 
wb_dma_ch_arb u4(
1256 
        .clk(           clk             ),
1257 
        .rst(           rst             ),
1258 
        .req(           req_p3          ),
1259 
        .gnt(           gnt_p3          ),
1260 
        .advance(       next_ch         )
1261 
        );
1262 
`endif
1263 
 
1264 8 rudi 
`ifdef WDMA_PRI_8
1265 5 rudi 
// RR Arbiter for priority 2
1266 
wb_dma_ch_arb u3(
1267 
        .clk(           clk             ),
1268 
        .rst(           rst             ),
1269 
        .req(           req_p2          ),
1270 
        .gnt(           gnt_p2          ),
1271 
        .advance(       next_ch         )
1272 
        );
1273 
// RR Arbiter for priority 3
1274 
wb_dma_ch_arb u4(
1275 
        .clk(           clk             ),
1276 
        .rst(           rst             ),
1277 
        .req(           req_p3          ),
1278 
        .gnt(           gnt_p3          ),
1279 
        .advance(       next_ch         )
1280 
        );
1281 
// RR Arbiter for priority 4
1282 
wb_dma_ch_arb u5(
1283 
        .clk(           clk             ),
1284 
        .rst(           rst             ),
1285 
        .req(           req_p4          ),
1286 
        .gnt(           gnt_p4          ),
1287 
        .advance(       next_ch         )
1288 
        );
1289 
// RR Arbiter for priority 5
1290 
wb_dma_ch_arb u6(
1291 
        .clk(           clk             ),
1292 
        .rst(           rst             ),
1293 
        .req(           req_p5          ),
1294 
        .gnt(           gnt_p5          ),
1295 
        .advance(       next_ch         )
1296 
        );
1297 
// RR Arbiter for priority 6
1298 
wb_dma_ch_arb u7(
1299 
        .clk(           clk             ),
1300 
        .rst(           rst             ),
1301 
        .req(           req_p6          ),
1302 
        .gnt(           gnt_p6          ),
1303 
        .advance(       next_ch         )
1304 
        );
1305 
// RR Arbiter for priority 7
1306 
wb_dma_ch_arb u8(
1307 
        .clk(           clk             ),
1308 
        .rst(           rst             ),
1309 
        .req(           req_p7          ),
1310 
        .gnt(           gnt_p7          ),
1311 
        .advance(       next_ch         )
1312 
        );
1313 
`endif
1314 
 
1315 
// Ground unused outputs
1316 8 rudi 
`ifdef WDMA_PRI_8
1317 5 rudi 
// Do nothing
1318 
`else
1319 
assign gnt_p4 = 0;
1320 
assign gnt_p5 = 0;
1321 
assign gnt_p6 = 0;
1322 
assign gnt_p7 = 0;
1323 8 rudi 
`ifdef WDMA_PRI_4
1324 5 rudi 
// Do nothing
1325 
`else
1326 
assign gnt_p2 = 0;
1327 
assign gnt_p3 = 0;
1328 
`endif
1329 
`endif
1330 
 
1331 
endmodule

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