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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_defines.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE DMA Definitions                                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_dma_defines.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
//
//  $Date: 2001-07-29 08:57:02 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/06/05 10:22:37  rudi
//
//
//               - Added Support of up to 31 channels
//               - Added support for 2,4 and 8 priority levels
//               - Now can have up to 31 channels
//               - Added many configuration items
//               - Changed reset to async
//
//               Revision 1.1.1.1  2001/03/19 13:11:09  rudi
//               Initial Release
//
//
//
 
`timescale 1ns / 10ps
 
// Identify how many channels are in this implementation
`define CH_COUNT        4
 
`define HAVE_CH1        1
`define HAVE_CH2        1
`define HAVE_CH3        1
 
/*
`define HAVE_CH4        1
`define HAVE_CH5        1
`define HAVE_CH6        1
`define HAVE_CH7        1
`define HAVE_CH8        1
`define HAVE_CH9        1
`define HAVE_CH10       1
`define HAVE_CH11       1
`define HAVE_CH12       1
`define HAVE_CH13       1
`define HAVE_CH14       1
`define HAVE_CH15       1
`define HAVE_CH16       1
`define HAVE_CH17       1
`define HAVE_CH18       1
`define HAVE_CH19       1
`define HAVE_CH20       1
`define HAVE_CH21       1
`define HAVE_CH22       1
`define HAVE_CH23       1
`define HAVE_CH24       1
`define HAVE_CH25       1
`define HAVE_CH26       1
`define HAVE_CH27       1
`define HAVE_CH28       1
`define HAVE_CH29       1
`define HAVE_CH30       1
*/
 
`define HAVE_ARS0       1
`define HAVE_ARS1       1
`define HAVE_ARS2       1
`define HAVE_ARS3       1
`define HAVE_ARS4       1
`define HAVE_ARS5       1
`define HAVE_ARS6       1
`define HAVE_ARS7       1
`define HAVE_ARS8       1
`define HAVE_ARS9       1
`define HAVE_ARS10      1
`define HAVE_ARS11      1
`define HAVE_ARS12      1
`define HAVE_ARS13      1
`define HAVE_ARS14      1
`define HAVE_ARS15      1
`define HAVE_ARS16      1
`define HAVE_ARS17      1
`define HAVE_ARS18      1
`define HAVE_ARS19      1
`define HAVE_ARS20      1
`define HAVE_ARS21      1
`define HAVE_ARS22      1
`define HAVE_ARS23      1
`define HAVE_ARS24      1
`define HAVE_ARS25      1
`define HAVE_ARS26      1
`define HAVE_ARS27      1
`define HAVE_ARS28      1
`define HAVE_ARS29      1
`define HAVE_ARS30      1
 
`define HAVE_ED0        1
`define HAVE_ED1        1
`define HAVE_ED2        1
`define HAVE_ED3        1
`define HAVE_ED4        1
`define HAVE_ED5        1
`define HAVE_ED6        1
`define HAVE_ED7        1
`define HAVE_ED8        1
`define HAVE_ED9        1
`define HAVE_ED10       1
`define HAVE_ED11       1
`define HAVE_ED12       1
`define HAVE_ED13       1
`define HAVE_ED14       1
`define HAVE_ED15       1
`define HAVE_ED16       1
`define HAVE_ED17       1
`define HAVE_ED18       1
`define HAVE_ED19       1
`define HAVE_ED20       1
`define HAVE_ED21       1
`define HAVE_ED22       1
`define HAVE_ED23       1
`define HAVE_ED24       1
`define HAVE_ED25       1
`define HAVE_ED26       1
`define HAVE_ED27       1
`define HAVE_ED28       1
`define HAVE_ED29       1
`define HAVE_ED30       1
 
`define HAVE_CBUF0      1
`define HAVE_CBUF1      1
`define HAVE_CBUF2      1
`define HAVE_CBUF3      1
`define HAVE_CBUF4      1
`define HAVE_CBUF5      1
`define HAVE_CBUF6      1
`define HAVE_CBUF7      1
`define HAVE_CBUF8      1
`define HAVE_CBUF9      1
`define HAVE_CBUF10     1
`define HAVE_CBUF11     1
`define HAVE_CBUF12     1
`define HAVE_CBUF13     1
`define HAVE_CBUF14     1
`define HAVE_CBUF15     1
`define HAVE_CBUF16     1
`define HAVE_CBUF17     1
`define HAVE_CBUF18     1
`define HAVE_CBUF19     1
`define HAVE_CBUF20     1
`define HAVE_CBUF21     1
`define HAVE_CBUF22     1
`define HAVE_CBUF23     1
`define HAVE_CBUF24     1
`define HAVE_CBUF25     1
`define HAVE_CBUF26     1
`define HAVE_CBUF27     1
`define HAVE_CBUF28     1
`define HAVE_CBUF29     1
`define HAVE_CBUF30     1
 
// The two define statements below select the number of priorities
// that the DMA engine supports.
// if PRI_8 is defined, 8 levels of priorities are supported. If PRI_4
// is defined then 4 levels of priorities are supported. If neither is
// defined then two levels of priorities are supported.
// PRI_4 and PRI_8 should never be both defined at the same time.
//`define PRI_8 1
`define PRI_4   1
 
 
// This define selects how the slave interface determines if
// the internal register file or pass through mode are selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
// NOTE: The entire pass-through mode is implemented in combinatorial
// logic only. So the more address lines we look at and compare here
// the higher will be the initial delay when pass-through mode is selected.
// Here we look at the top 8 address bit. If they are all 1, the
// register file is selected. Use this with caution !!!
`define REG_SEL         (wb_addr_i[31:24] == 8'hff)
 
 
// CSR Bits
`define CH_EN           0
`define DST_SEL         1
`define SRC_SEL         2
`define INC_DST         3
`define INC_SRC         4
`define MODE            5
`define ARS             6
`define USE_ED          7
`define WRB             8
`define STOP            9
`define BUSY            10
`define DONE            11
`define ERR             12
`define ED_EOL          20
 
 

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Subversion Repositories wb_dma

[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_defines.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE DMA Definitions ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_dma_defines.v,v 1.1 2001-07-29 08:57:02 rudi Exp $`
41			`//`
42			`// $Date: 2001-07-29 08:57:02 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`// Revision 1.2 2001/06/05 10:22:37 rudi`
51			`//`
52			`//`
53			`// - Added Support of up to 31 channels`
54			`// - Added support for 2,4 and 8 priority levels`
55			`// - Now can have up to 31 channels`
56			`// - Added many configuration items`
57			`// - Changed reset to async`
58			`//`
59			`// Revision 1.1.1.1 2001/03/19 13:11:09 rudi`
60			`// Initial Release`
61			`//`
62			`//`
63			`//`
64
65			`timescale 1ns / 10ps
66
67			`// Identify how many channels are in this implementation`
68			`define CH_COUNT 4
69
70			`define HAVE_CH1 1
71			`define HAVE_CH2 1
72			`define HAVE_CH3 1
73
74			`/*`
75			`define HAVE_CH4 1
76			`define HAVE_CH5 1
77			`define HAVE_CH6 1
78			`define HAVE_CH7 1
79			`define HAVE_CH8 1
80			`define HAVE_CH9 1
81			`define HAVE_CH10 1
82			`define HAVE_CH11 1
83			`define HAVE_CH12 1
84			`define HAVE_CH13 1
85			`define HAVE_CH14 1
86			`define HAVE_CH15 1
87			`define HAVE_CH16 1
88			`define HAVE_CH17 1
89			`define HAVE_CH18 1
90			`define HAVE_CH19 1
91			`define HAVE_CH20 1
92			`define HAVE_CH21 1
93			`define HAVE_CH22 1
94			`define HAVE_CH23 1
95			`define HAVE_CH24 1
96			`define HAVE_CH25 1
97			`define HAVE_CH26 1
98			`define HAVE_CH27 1
99			`define HAVE_CH28 1
100			`define HAVE_CH29 1
101			`define HAVE_CH30 1
102			`*/`
103
104			`define HAVE_ARS0 1
105			`define HAVE_ARS1 1
106			`define HAVE_ARS2 1
107			`define HAVE_ARS3 1
108			`define HAVE_ARS4 1
109			`define HAVE_ARS5 1
110			`define HAVE_ARS6 1
111			`define HAVE_ARS7 1
112			`define HAVE_ARS8 1
113			`define HAVE_ARS9 1
114			`define HAVE_ARS10 1
115			`define HAVE_ARS11 1
116			`define HAVE_ARS12 1
117			`define HAVE_ARS13 1
118			`define HAVE_ARS14 1
119			`define HAVE_ARS15 1
120			`define HAVE_ARS16 1
121			`define HAVE_ARS17 1
122			`define HAVE_ARS18 1
123			`define HAVE_ARS19 1
124			`define HAVE_ARS20 1
125			`define HAVE_ARS21 1
126			`define HAVE_ARS22 1
127			`define HAVE_ARS23 1
128			`define HAVE_ARS24 1
129			`define HAVE_ARS25 1
130			`define HAVE_ARS26 1
131			`define HAVE_ARS27 1
132			`define HAVE_ARS28 1
133			`define HAVE_ARS29 1
134			`define HAVE_ARS30 1
135
136			`define HAVE_ED0 1
137			`define HAVE_ED1 1
138			`define HAVE_ED2 1
139			`define HAVE_ED3 1
140			`define HAVE_ED4 1
141			`define HAVE_ED5 1
142			`define HAVE_ED6 1
143			`define HAVE_ED7 1
144			`define HAVE_ED8 1
145			`define HAVE_ED9 1
146			`define HAVE_ED10 1
147			`define HAVE_ED11 1
148			`define HAVE_ED12 1
149			`define HAVE_ED13 1
150			`define HAVE_ED14 1
151			`define HAVE_ED15 1
152			`define HAVE_ED16 1
153			`define HAVE_ED17 1
154			`define HAVE_ED18 1
155			`define HAVE_ED19 1
156			`define HAVE_ED20 1
157			`define HAVE_ED21 1
158			`define HAVE_ED22 1
159			`define HAVE_ED23 1
160			`define HAVE_ED24 1
161			`define HAVE_ED25 1
162			`define HAVE_ED26 1
163			`define HAVE_ED27 1
164			`define HAVE_ED28 1
165			`define HAVE_ED29 1
166			`define HAVE_ED30 1
167
168			`define HAVE_CBUF0 1
169			`define HAVE_CBUF1 1
170			`define HAVE_CBUF2 1
171			`define HAVE_CBUF3 1
172			`define HAVE_CBUF4 1
173			`define HAVE_CBUF5 1
174			`define HAVE_CBUF6 1
175			`define HAVE_CBUF7 1
176			`define HAVE_CBUF8 1
177			`define HAVE_CBUF9 1
178			`define HAVE_CBUF10 1
179			`define HAVE_CBUF11 1
180			`define HAVE_CBUF12 1
181			`define HAVE_CBUF13 1
182			`define HAVE_CBUF14 1
183			`define HAVE_CBUF15 1
184			`define HAVE_CBUF16 1
185			`define HAVE_CBUF17 1
186			`define HAVE_CBUF18 1
187			`define HAVE_CBUF19 1
188			`define HAVE_CBUF20 1
189			`define HAVE_CBUF21 1
190			`define HAVE_CBUF22 1
191			`define HAVE_CBUF23 1
192			`define HAVE_CBUF24 1
193			`define HAVE_CBUF25 1
194			`define HAVE_CBUF26 1
195			`define HAVE_CBUF27 1
196			`define HAVE_CBUF28 1
197			`define HAVE_CBUF29 1
198			`define HAVE_CBUF30 1
199
200			`// The two define statements below select the number of priorities`
201			`// that the DMA engine supports.`
202			`// if PRI_8 is defined, 8 levels of priorities are supported. If PRI_4`
203			`// is defined then 4 levels of priorities are supported. If neither is`
204			`// defined then two levels of priorities are supported.`
205			`// PRI_4 and PRI_8 should never be both defined at the same time.`
206			//`define PRI_8 1
207			`define PRI_4 1
208
209
210			`// This define selects how the slave interface determines if`
211			`// the internal register file or pass through mode are selected.`
212			`// This should be a simple address decoder. "wb_addr_i" is the`
213			`// WISHBONE address bus (32 bits wide).`
214			`// NOTE: The entire pass-through mode is implemented in combinatorial`
215			`// logic only. So the more address lines we look at and compare here`
216			`// the higher will be the initial delay when pass-through mode is selected.`
217			`// Here we look at the top 8 address bit. If they are all 1, the`
218			`// register file is selected. Use this with caution !!!`
219			`define REG_SEL (wb_addr_i[31:24] == 8'hff)
220
221
222			`// CSR Bits`
223			`define CH_EN 0
224			`define DST_SEL 1
225			`define SRC_SEL 2
226			`define INC_DST 3
227			`define INC_SRC 4
228			`define MODE 5
229			`define ARS 6
230			`define USE_ED 7
231			`define WRB 8
232			`define STOP 9
233			`define BUSY 10
234			`define DONE 11
235			`define ERR 12
236			`define ED_EOL 20
237
238