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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_defines.v] - Blame information for rev 8

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE DMA Definitions                                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_dma_defines.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
//  $Date: 2001-08-15 05:40:30 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.2  2001/06/05 10:22:37  rudi
//
//
//               - Added Support of up to 31 channels
//               - Added support for 2,4 and 8 priority levels
//               - Now can have up to 31 channels
//               - Added many configuration items
//               - Changed reset to async
//
//               Revision 1.1.1.1  2001/03/19 13:11:09  rudi
//               Initial Release
//
//
//
 
`timescale 1ns / 10ps
 
// Identify how many channels are in this implementation
`define WDMA_CH_COUNT   4
 
`define WDMA_HAVE_CH1   1
`define WDMA_HAVE_CH2   1
`define WDMA_HAVE_CH3   1
 
/*
`define WDMA_HAVE_CH4   1
`define WDMA_HAVE_CH5   1
`define WDMA_HAVE_CH6   1
`define WDMA_HAVE_CH7   1
`define WDMA_HAVE_CH8   1
`define WDMA_HAVE_CH9   1
`define WDMA_HAVE_CH10  1
`define WDMA_HAVE_CH11  1
`define WDMA_HAVE_CH12  1
`define WDMA_HAVE_CH13  1
`define WDMA_HAVE_CH14  1
`define WDMA_HAVE_CH15  1
`define WDMA_HAVE_CH16  1
`define WDMA_HAVE_CH17  1
`define WDMA_HAVE_CH18  1
`define WDMA_HAVE_CH19  1
`define WDMA_HAVE_CH20  1
`define WDMA_HAVE_CH21  1
`define WDMA_HAVE_CH22  1
`define WDMA_HAVE_CH23  1
`define WDMA_HAVE_CH24  1
`define WDMA_HAVE_CH25  1
`define WDMA_HAVE_CH26  1
`define WDMA_HAVE_CH27  1
`define WDMA_HAVE_CH28  1
`define WDMA_HAVE_CH29  1
`define WDMA_HAVE_CH30  1
*/
 
`define WDMA_HAVE_ARS0          1
`define WDMA_HAVE_ARS1          1
`define WDMA_HAVE_ARS2          1
`define WDMA_HAVE_ARS3          1
`define WDMA_HAVE_ARS4          1
`define WDMA_HAVE_ARS5          1
`define WDMA_HAVE_ARS6          1
`define WDMA_HAVE_ARS7          1
`define WDMA_HAVE_ARS8          1
`define WDMA_HAVE_ARS9          1
`define WDMA_HAVE_ARS10         1
`define WDMA_HAVE_ARS11         1
`define WDMA_HAVE_ARS12         1
`define WDMA_HAVE_ARS13         1
`define WDMA_HAVE_ARS14         1
`define WDMA_HAVE_ARS15         1
`define WDMA_HAVE_ARS16         1
`define WDMA_HAVE_ARS17         1
`define WDMA_HAVE_ARS18         1
`define WDMA_HAVE_ARS19         1
`define WDMA_HAVE_ARS20         1
`define WDMA_HAVE_ARS21         1
`define WDMA_HAVE_ARS22         1
`define WDMA_HAVE_ARS23         1
`define WDMA_HAVE_ARS24         1
`define WDMA_HAVE_ARS25         1
`define WDMA_HAVE_ARS26         1
`define WDMA_HAVE_ARS27         1
`define WDMA_HAVE_ARS28         1
`define WDMA_HAVE_ARS29         1
`define WDMA_HAVE_ARS30         1
 
`define WDMA_HAVE_ED0           1
`define WDMA_HAVE_ED1           1
`define WDMA_HAVE_ED2           1
`define WDMA_HAVE_ED3           1
`define WDMA_HAVE_ED4           1
`define WDMA_HAVE_ED5           1
`define WDMA_HAVE_ED6           1
`define WDMA_HAVE_ED7           1
`define WDMA_HAVE_ED8           1
`define WDMA_HAVE_ED9           1
`define WDMA_HAVE_ED10          1
`define WDMA_HAVE_ED11          1
`define WDMA_HAVE_ED12          1
`define WDMA_HAVE_ED13          1
`define WDMA_HAVE_ED14          1
`define WDMA_HAVE_ED15          1
`define WDMA_HAVE_ED16          1
`define WDMA_HAVE_ED17          1
`define WDMA_HAVE_ED18          1
`define WDMA_HAVE_ED19          1
`define WDMA_HAVE_ED20          1
`define WDMA_HAVE_ED21          1
`define WDMA_HAVE_ED22          1
`define WDMA_HAVE_ED23          1
`define WDMA_HAVE_ED24          1
`define WDMA_HAVE_ED25          1
`define WDMA_HAVE_ED26          1
`define WDMA_HAVE_ED27          1
`define WDMA_HAVE_ED28          1
`define WDMA_HAVE_ED29          1
`define WDMA_HAVE_ED30          1
 
`define WDMA_HAVE_CBUF0         1
`define WDMA_HAVE_CBUF1         1
`define WDMA_HAVE_CBUF2         1
`define WDMA_HAVE_CBUF3         1
`define WDMA_HAVE_CBUF4         1
`define WDMA_HAVE_CBUF5         1
`define WDMA_HAVE_CBUF6         1
`define WDMA_HAVE_CBUF7         1
`define WDMA_HAVE_CBUF8         1
`define WDMA_HAVE_CBUF9         1
`define WDMA_HAVE_CBUF10        1
`define WDMA_HAVE_CBUF11        1
`define WDMA_HAVE_CBUF12        1
`define WDMA_HAVE_CBUF13        1
`define WDMA_HAVE_CBUF14        1
`define WDMA_HAVE_CBUF15        1
`define WDMA_HAVE_CBUF16        1
`define WDMA_HAVE_CBUF17        1
`define WDMA_HAVE_CBUF18        1
`define WDMA_HAVE_CBUF19        1
`define WDMA_HAVE_CBUF20        1
`define WDMA_HAVE_CBUF21        1
`define WDMA_HAVE_CBUF22        1
`define WDMA_HAVE_CBUF23        1
`define WDMA_HAVE_CBUF24        1
`define WDMA_HAVE_CBUF25        1
`define WDMA_HAVE_CBUF26        1
`define WDMA_HAVE_CBUF27        1
`define WDMA_HAVE_CBUF28        1
`define WDMA_HAVE_CBUF29        1
`define WDMA_HAVE_CBUF30        1
 
// The two define statements below select the number of priorities
// that the DMA engine supports.
// if WDMA_PRI_8 is defined, 8 levels of priorities are supported. If
// WDMA_PRI_4 is defined then 4 levels of priorities are supported.
// If neither is defined then two levels of priorities are supported.
// WDMA_PRI_4 and WDMA_PRI_8 should never be both defined at the same
// time.
 
//`define WDMA_PRI_8    1
`define WDMA_PRI_4      1
 
// This define selects how the slave interface determines if
// the internal register file or pass through mode are selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
// NOTE: The entire pass-through mode is implemented in combinatorial
// logic only. So the more address lines we look at and compare here
// the higher will be the initial delay when pass-through mode is selected.
// Here we look at the top 8 address bit. If they are all 1, the
// register file is selected. Use this with caution !!!
`define WDMA_REG_SEL            (wb_addr_i[31:24] == 8'hff)
 
 
// CSR Bits
`define WDMA_CH_EN              0
`define WDMA_DST_SEL            1
`define WDMA_SRC_SEL            2
`define WDMA_INC_DST            3
`define WDMA_INC_SRC            4
`define WDMA_MODE               5
`define WDMA_ARS                6
`define WDMA_USE_ED             7
`define WDMA_WRB                8
`define WDMA_STOP               9
`define WDMA_BUSY               10
`define WDMA_DONE               11
`define WDMA_ERR                12
`define WDMA_ED_EOL             20
 

Line No.	Rev	Author	Line
1	5	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE DMA Definitions ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	8	rudi	`// $Id: wb_dma_defines.v,v 1.2 2001-08-15 05:40:30 rudi Exp $`
41	5	rudi	`//`
42	8	rudi	`// $Date: 2001-08-15 05:40:30 $`
43			`// $Revision: 1.2 $`
44	5	rudi	`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	8	rudi	`// Revision 1.1 2001/07/29 08:57:02 rudi`
51			`//`
52			`//`
53			`// 1) Changed Directory Structure`
54			`// 2) Added restart signal (REST)`
55			`//`
56	5	rudi	`// Revision 1.2 2001/06/05 10:22:37 rudi`
57			`//`
58			`//`
59			`// - Added Support of up to 31 channels`
60			`// - Added support for 2,4 and 8 priority levels`
61			`// - Now can have up to 31 channels`
62			`// - Added many configuration items`
63			`// - Changed reset to async`
64			`//`
65			`// Revision 1.1.1.1 2001/03/19 13:11:09 rudi`
66			`// Initial Release`
67			`//`
68			`//`
69			`//`
70
71			`timescale 1ns / 10ps
72
73			`// Identify how many channels are in this implementation`
74	8	rudi	`define WDMA_CH_COUNT 4
75	5	rudi
76	8	rudi	`define WDMA_HAVE_CH1 1
77			`define WDMA_HAVE_CH2 1
78			`define WDMA_HAVE_CH3 1
79	5	rudi
80			`/*`
81	8	rudi	`define WDMA_HAVE_CH4 1
82			`define WDMA_HAVE_CH5 1
83			`define WDMA_HAVE_CH6 1
84			`define WDMA_HAVE_CH7 1
85			`define WDMA_HAVE_CH8 1
86			`define WDMA_HAVE_CH9 1
87			`define WDMA_HAVE_CH10 1
88			`define WDMA_HAVE_CH11 1
89			`define WDMA_HAVE_CH12 1
90			`define WDMA_HAVE_CH13 1
91			`define WDMA_HAVE_CH14 1
92			`define WDMA_HAVE_CH15 1
93			`define WDMA_HAVE_CH16 1
94			`define WDMA_HAVE_CH17 1
95			`define WDMA_HAVE_CH18 1
96			`define WDMA_HAVE_CH19 1
97			`define WDMA_HAVE_CH20 1
98			`define WDMA_HAVE_CH21 1
99			`define WDMA_HAVE_CH22 1
100			`define WDMA_HAVE_CH23 1
101			`define WDMA_HAVE_CH24 1
102			`define WDMA_HAVE_CH25 1
103			`define WDMA_HAVE_CH26 1
104			`define WDMA_HAVE_CH27 1
105			`define WDMA_HAVE_CH28 1
106			`define WDMA_HAVE_CH29 1
107			`define WDMA_HAVE_CH30 1
108	5	rudi	`*/`
109
110	8	rudi	`define WDMA_HAVE_ARS0 1
111			`define WDMA_HAVE_ARS1 1
112			`define WDMA_HAVE_ARS2 1
113			`define WDMA_HAVE_ARS3 1
114			`define WDMA_HAVE_ARS4 1
115			`define WDMA_HAVE_ARS5 1
116			`define WDMA_HAVE_ARS6 1
117			`define WDMA_HAVE_ARS7 1
118			`define WDMA_HAVE_ARS8 1
119			`define WDMA_HAVE_ARS9 1
120			`define WDMA_HAVE_ARS10 1
121			`define WDMA_HAVE_ARS11 1
122			`define WDMA_HAVE_ARS12 1
123			`define WDMA_HAVE_ARS13 1
124			`define WDMA_HAVE_ARS14 1
125			`define WDMA_HAVE_ARS15 1
126			`define WDMA_HAVE_ARS16 1
127			`define WDMA_HAVE_ARS17 1
128			`define WDMA_HAVE_ARS18 1
129			`define WDMA_HAVE_ARS19 1
130			`define WDMA_HAVE_ARS20 1
131			`define WDMA_HAVE_ARS21 1
132			`define WDMA_HAVE_ARS22 1
133			`define WDMA_HAVE_ARS23 1
134			`define WDMA_HAVE_ARS24 1
135			`define WDMA_HAVE_ARS25 1
136			`define WDMA_HAVE_ARS26 1
137			`define WDMA_HAVE_ARS27 1
138			`define WDMA_HAVE_ARS28 1
139			`define WDMA_HAVE_ARS29 1
140			`define WDMA_HAVE_ARS30 1
141	5	rudi
142	8	rudi	`define WDMA_HAVE_ED0 1
143			`define WDMA_HAVE_ED1 1
144			`define WDMA_HAVE_ED2 1
145			`define WDMA_HAVE_ED3 1
146			`define WDMA_HAVE_ED4 1
147			`define WDMA_HAVE_ED5 1
148			`define WDMA_HAVE_ED6 1
149			`define WDMA_HAVE_ED7 1
150			`define WDMA_HAVE_ED8 1
151			`define WDMA_HAVE_ED9 1
152			`define WDMA_HAVE_ED10 1
153			`define WDMA_HAVE_ED11 1
154			`define WDMA_HAVE_ED12 1
155			`define WDMA_HAVE_ED13 1
156			`define WDMA_HAVE_ED14 1
157			`define WDMA_HAVE_ED15 1
158			`define WDMA_HAVE_ED16 1
159			`define WDMA_HAVE_ED17 1
160			`define WDMA_HAVE_ED18 1
161			`define WDMA_HAVE_ED19 1
162			`define WDMA_HAVE_ED20 1
163			`define WDMA_HAVE_ED21 1
164			`define WDMA_HAVE_ED22 1
165			`define WDMA_HAVE_ED23 1
166			`define WDMA_HAVE_ED24 1
167			`define WDMA_HAVE_ED25 1
168			`define WDMA_HAVE_ED26 1
169			`define WDMA_HAVE_ED27 1
170			`define WDMA_HAVE_ED28 1
171			`define WDMA_HAVE_ED29 1
172			`define WDMA_HAVE_ED30 1
173	5	rudi
174	8	rudi	`define WDMA_HAVE_CBUF0 1
175			`define WDMA_HAVE_CBUF1 1
176			`define WDMA_HAVE_CBUF2 1
177			`define WDMA_HAVE_CBUF3 1
178			`define WDMA_HAVE_CBUF4 1
179			`define WDMA_HAVE_CBUF5 1
180			`define WDMA_HAVE_CBUF6 1
181			`define WDMA_HAVE_CBUF7 1
182			`define WDMA_HAVE_CBUF8 1
183			`define WDMA_HAVE_CBUF9 1
184			`define WDMA_HAVE_CBUF10 1
185			`define WDMA_HAVE_CBUF11 1
186			`define WDMA_HAVE_CBUF12 1
187			`define WDMA_HAVE_CBUF13 1
188			`define WDMA_HAVE_CBUF14 1
189			`define WDMA_HAVE_CBUF15 1
190			`define WDMA_HAVE_CBUF16 1
191			`define WDMA_HAVE_CBUF17 1
192			`define WDMA_HAVE_CBUF18 1
193			`define WDMA_HAVE_CBUF19 1
194			`define WDMA_HAVE_CBUF20 1
195			`define WDMA_HAVE_CBUF21 1
196			`define WDMA_HAVE_CBUF22 1
197			`define WDMA_HAVE_CBUF23 1
198			`define WDMA_HAVE_CBUF24 1
199			`define WDMA_HAVE_CBUF25 1
200			`define WDMA_HAVE_CBUF26 1
201			`define WDMA_HAVE_CBUF27 1
202			`define WDMA_HAVE_CBUF28 1
203			`define WDMA_HAVE_CBUF29 1
204			`define WDMA_HAVE_CBUF30 1
205	5	rudi
206			`// The two define statements below select the number of priorities`
207			`// that the DMA engine supports.`
208	8	rudi	`// if WDMA_PRI_8 is defined, 8 levels of priorities are supported. If`
209			`// WDMA_PRI_4 is defined then 4 levels of priorities are supported.`
210			`// If neither is defined then two levels of priorities are supported.`
211			`// WDMA_PRI_4 and WDMA_PRI_8 should never be both defined at the same`
212			`// time.`
213	5	rudi
214	8	rudi	//`define WDMA_PRI_8 1
215			`define WDMA_PRI_4 1
216	5	rudi
217			`// This define selects how the slave interface determines if`
218			`// the internal register file or pass through mode are selected.`
219			`// This should be a simple address decoder. "wb_addr_i" is the`
220			`// WISHBONE address bus (32 bits wide).`
221			`// NOTE: The entire pass-through mode is implemented in combinatorial`
222			`// logic only. So the more address lines we look at and compare here`
223			`// the higher will be the initial delay when pass-through mode is selected.`
224			`// Here we look at the top 8 address bit. If they are all 1, the`
225			`// register file is selected. Use this with caution !!!`
226	8	rudi	`define WDMA_REG_SEL (wb_addr_i[31:24] == 8'hff)
227	5	rudi
228
229			`// CSR Bits`
230	8	rudi	`define WDMA_CH_EN 0
231			`define WDMA_DST_SEL 1
232			`define WDMA_SRC_SEL 2
233			`define WDMA_INC_DST 3
234			`define WDMA_INC_SRC 4
235			`define WDMA_MODE 5
236			`define WDMA_ARS 6
237			`define WDMA_USE_ED 7
238			`define WDMA_WRB 8
239			`define WDMA_STOP 9
240			`define WDMA_BUSY 10
241			`define WDMA_DONE 11
242			`define WDMA_ERR 12
243			`define WDMA_ED_EOL 20
244	5	rudi

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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_defines.v] - Blame information for rev 8