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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_inc30r.v] - Blame information for rev 5

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1 5 rudi
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE DMA Primitives                                    ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2001 Rudolf Usselmann                         ////
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////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: wb_dma_inc30r.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
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//
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//  $Date: 2001-07-29 08:57:02 $
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//  $Revision: 1.1 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.2  2001/06/05 10:22:37  rudi
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//
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//
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//               - Added Support of up to 31 channels
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//               - Added support for 2,4 and 8 priority levels
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//               - Now can have up to 31 channels
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//               - Added many configuration items
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//               - Changed reset to async
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//
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//               Revision 1.1.1.1  2001/03/19 13:11:12  rudi
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//               Initial Release
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//
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//
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//
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`include "wb_dma_defines.v"
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module wb_dma_inc30r(clk, in, out);
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input           clk;
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input   [29:0]   in;
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output  [29:0]   out;
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// INC30_CENTER indicates the center bit of the 30 bit incrementor
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// so it can be easily manually optimized for best performance
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parameter       INC30_CENTER = 16;
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reg     [INC30_CENTER:0] out_r;
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always @(posedge clk)
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        out_r <= #1 in[(INC30_CENTER - 1):0] + 1;
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assign out[29:INC30_CENTER] = in[29:INC30_CENTER] + out_r[INC30_CENTER];
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assign out[(INC30_CENTER - 1):0]  = out_r;
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endmodule
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