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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_pri_enc_sub.v] - Blame information for rev 17

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE DMA Priority Encoder Sub-Module                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_dma_pri_enc_sub.v,v 1.4 2002-02-01 01:54:45 rudi Exp $
//
//  $Date: 2002-02-01 01:54:45 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2001/10/19 04:35:04  rudi
//
//               - Made the core parameterized
//
//               Revision 1.2  2001/08/15 05:40:30  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Added Section 3.10, describing DMA restart.
//
//               Revision 1.1  2001/08/07 08:00:43  rudi
//
//
//               Split up priority encoder modules to separate files
//
//
//
//
//
//
 
`include "wb_dma_defines.v"
 
// Priority Encoder
//
// Determines the channel with the highest priority, also takes
// the valid bit in consideration
 
module wb_dma_pri_enc_sub(valid, pri_in, pri_out);
 
parameter [3:0]  ch_conf = 4'b0000;
parameter [1:0]  pri_sel = 2'd0;
 
input           valid;
input   [2:0]    pri_in;
output  [7:0]    pri_out;
 
wire    [7:0]    pri_out;
reg     [7:0]    pri_out_d;
reg     [7:0]    pri_out_d0;
reg     [7:0]    pri_out_d1;
reg     [7:0]    pri_out_d2;
 
assign pri_out = ch_conf[0] ? pri_out_d : 8'h0;
 
// Select Configured Priority
always @(pri_sel or pri_out_d0 or pri_out_d1 or  pri_out_d2)
        case(pri_sel)           // synopsys parallel_case full_case
           2'd0: pri_out_d = pri_out_d0;
           2'd1: pri_out_d = pri_out_d1;
           2'd2: pri_out_d = pri_out_d2;
        endcase
 
// 8 Priority Levels
always @(valid or pri_in)
        if(!valid)              pri_out_d2 = 8'b0000_0001;
        else
        if(pri_in==3'h0)        pri_out_d2 = 8'b0000_0001;
        else
        if(pri_in==3'h1)        pri_out_d2 = 8'b0000_0010;
        else
        if(pri_in==3'h2)        pri_out_d2 = 8'b0000_0100;
        else
        if(pri_in==3'h3)        pri_out_d2 = 8'b0000_1000;
        else
        if(pri_in==3'h4)        pri_out_d2 = 8'b0001_0000;
        else
        if(pri_in==3'h5)        pri_out_d2 = 8'b0010_0000;
        else
        if(pri_in==3'h6)        pri_out_d2 = 8'b0100_0000;
        else                    pri_out_d2 = 8'b1000_0000;
 
// 4 Priority Levels
always @(valid or pri_in)
        if(!valid)              pri_out_d1 = 8'b0000_0001;
        else
        if(pri_in==3'h0)        pri_out_d1 = 8'b0000_0001;
        else
        if(pri_in==3'h1)        pri_out_d1 = 8'b0000_0010;
        else
        if(pri_in==3'h2)        pri_out_d1 = 8'b0000_0100;
        else                    pri_out_d1 = 8'b0000_1000;
 
// 2 Priority Levels
always @(valid or pri_in)
        if(!valid)              pri_out_d0 = 8'b0000_0001;
        else
        if(pri_in==3'h0)        pri_out_d0 = 8'b0000_0001;
        else                    pri_out_d0 = 8'b0000_0010;
 
endmodule
 

Line No.	Rev	Author	Line
1	6	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE DMA Priority Encoder Sub-Module ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	15	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17	6	rudi	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	15	rudi	`// $Id: wb_dma_pri_enc_sub.v,v 1.4 2002-02-01 01:54:45 rudi Exp $`
42	6	rudi	`//`
43	15	rudi	`// $Date: 2002-02-01 01:54:45 $`
44			`// $Revision: 1.4 $`
45	6	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	15	rudi	`// Revision 1.3 2001/10/19 04:35:04 rudi`
52			`//`
53			`// - Made the core parameterized`
54			`//`
55	10	rudi	`// Revision 1.2 2001/08/15 05:40:30 rudi`
56			`//`
57			`// - Changed IO names to be more clear.`
58			`// - Uniquifyed define names to be core specific.`
59			`// - Added Section 3.10, describing DMA restart.`
60			`//`
61	8	rudi	`// Revision 1.1 2001/08/07 08:00:43 rudi`
62	6	rudi	`//`
63			`//`
64	8	rudi	`// Split up priority encoder modules to separate files`
65	6	rudi	`//`
66			`//`
67			`//`
68	8	rudi	`//`
69			`//`
70			`//`
71	6	rudi
72			`include "wb_dma_defines.v"
73
74			`// Priority Encoder`
75			`//`
76			`// Determines the channel with the highest priority, also takes`
77			`// the valid bit in consideration`
78
79			`module wb_dma_pri_enc_sub(valid, pri_in, pri_out);`
80	10	rudi
81			`parameter [3:0] ch_conf = 4'b0000;`
82			`parameter [1:0] pri_sel = 2'd0;`
83
84	6	rudi	`input valid;`
85			`input [2:0] pri_in;`
86			`output [7:0] pri_out;`
87
88	10	rudi	`wire [7:0] pri_out;`
89			`reg [7:0] pri_out_d;`
90			`reg [7:0] pri_out_d0;`
91			`reg [7:0] pri_out_d1;`
92			`reg [7:0] pri_out_d2;`
93	6	rudi
94	10	rudi	`assign pri_out = ch_conf[0] ? pri_out_d : 8'h0;`
95
96			`// Select Configured Priority`
97			`always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2)`
98			`case(pri_sel) // synopsys parallel_case full_case`
99			`2'd0: pri_out_d = pri_out_d0;`
100			`2'd1: pri_out_d = pri_out_d1;`
101			`2'd2: pri_out_d = pri_out_d2;`
102			`endcase`
103
104			`// 8 Priority Levels`
105	6	rudi	`always @(valid or pri_in)`
106	10	rudi	`if(!valid) pri_out_d2 = 8'b0000_0001;`
107	6	rudi	`else`
108	10	rudi	`if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001;`
109	6	rudi	`else`
110	10	rudi	`if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010;`
111	6	rudi	`else`
112	10	rudi	`if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100;`
113	6	rudi	`else`
114	10	rudi	`if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000;`
115	6	rudi	`else`
116	10	rudi	`if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000;`
117	6	rudi	`else`
118	10	rudi	`if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000;`
119	6	rudi	`else`
120	10	rudi	`if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000;`
121			`else pri_out_d2 = 8'b1000_0000;`
122
123			`// 4 Priority Levels`
124	6	rudi	`always @(valid or pri_in)`
125	10	rudi	`if(!valid) pri_out_d1 = 8'b0000_0001;`
126	6	rudi	`else`
127	10	rudi	`if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001;`
128	6	rudi	`else`
129	10	rudi	`if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010;`
130	6	rudi	`else`
131	10	rudi	`if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100;`
132			`else pri_out_d1 = 8'b0000_1000;`
133
134			`// 2 Priority Levels`
135	6	rudi	`always @(valid or pri_in)`
136	10	rudi	`if(!valid) pri_out_d0 = 8'b0000_0001;`
137	6	rudi	`else`
138	10	rudi	`if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001;`
139			`else pri_out_d0 = 8'b0000_0010;`
140	6	rudi
141			`endmodule`
142

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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_pri_enc_sub.v] - Blame information for rev 17